CN102709183B - The method being used for producing the semiconductor devices - Google Patents
The method being used for producing the semiconductor devices Download PDFInfo
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- CN102709183B CN102709183B CN201110075392.4A CN201110075392A CN102709183B CN 102709183 B CN102709183 B CN 102709183B CN 201110075392 A CN201110075392 A CN 201110075392A CN 102709183 B CN102709183 B CN 102709183B
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 229910052796 boron Inorganic materials 0.000 claims abstract description 58
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 57
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 31
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 229910052986 germanium hydride Inorganic materials 0.000 claims description 15
- 238000010276 construction Methods 0.000 claims description 12
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims description 11
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 4
- 230000035755 proliferation Effects 0.000 claims description 4
- 230000001629 suppression Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 6
- 238000012545 processing Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 123
- 239000007789 gas Substances 0.000 description 36
- 239000013078 crystal Substances 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 239000002356 single layer Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
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- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 229910003822 SiHCl3 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- -1 boron ion Chemical class 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
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- 230000007423 decrease Effects 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
Abstract
The present invention provides a kind of method being used for producing the semiconductor devices, and described method includes: provides Semiconductor substrate, is formed with grid structure on the semiconductor substrate, and will be formed in described Semiconductor substrate in the part of source/drain region and be formed with groove；Selective epitaxial growth method is used to form boron diffusion impervious layer in uniform thickness on the bottom and sidewall of described groove；And use selective epitaxial growth method to form boracic germanium silicon stressor layers on described boron diffusion impervious layer.The method according to the invention can suppress the boron being entrained in SiGe stressor layers by original position SiGeB stress introducing technology to be diffused in channel region due to follow-up Technology for Heating Processing, thus effectively prevent short-channel effect, and then improve the electric property of the PMOS transistor ultimately formed.
Description
Technical field
The present invention relates to semiconductor fabrication process, and in particular to a kind of method being used for producing the semiconductor devices.
Background technology
At present, the principal element affecting field-effect transistor performance is the mobility of carrier.In scene effect transistor, because the size calculating journey 002 carrier mobility directly affects the size of electric current in raceway groove, the decline of carrier mobility not only can reduce the switch speed of transistor, but also resistance difference when can make on an off reduces.Therefore, in the development of complementary metal oxide semiconductor field effect transistor (CMOS), it is effectively improved one of emphasis that carrier mobility always is that transistor arrangement designs.
Conventionally, P-type mos field-effect transistor (PMOS) and N-type mos field effect transistor (NMOS) are separately processed by cmos device manufacturing technology, such as, compressive stress material is used in the manufacture method of PMOS device, and in nmos device, use tensile stress material, to apply suitable stress to channel region, thus improve the mobility of carrier.Wherein, embedded germanium silicon (SiGe) technology (hereinafter referred to as eSiGe technology) becomes one of major technique of PMOS stress engineering owing to it can apply suitable compressive stress to channel region to improve the mobility in hole.Generally, the embedded germanium silicon stress forming germanium silicon stressor layers in the source/drain region of PMOS transistor is used to introduce technology.
On the other hand, in order to reduce the heat budget in manufacture process, the most commonly used original position (in-situ) SiGeB stress introduces technology, i.e., boron doping is carried out, for forming the source/drain region of PMOS device while by selective epitaxial method growth SiGe stressor layers.But, during follow-up Technology for Heating Processing (such as, annealing optimization process etc.), mix boron due to instantaneous enhanced diffustion effect to channel region horizontal proliferation, the effective length making channel region shortens, thus causes short-channel effect, and then makes the electric property of PMOS device be deteriorated.
Accordingly, it would be desirable to develop a kind of method for making embedded germanium silicon strain PMOS device structure, to solve the problems referred to above.
Summary of the invention
For the deficiencies in the prior art, the present invention provides a kind of method being used for producing the semiconductor devices, described method includes: provides Semiconductor substrate, is formed with grid structure on the semiconductor substrate, and will be formed in described Semiconductor substrate in the part of source/drain region and be formed with groove；Selective epitaxial growth method is used to form boron diffusion impervious layer in uniform thickness on the bottom and sidewall of described groove；And use selective epitaxial growth method to form boracic germanium silicon stressor layers on described boron diffusion impervious layer.
Preferably, described boron diffusion impervious layer is pure SiGe inculating crystal layer.
Preferably, the thickness of described boron diffusion impervious layer is 5～300 angstroms.
Preferably, described boron diffusion impervious layer is multiple structure.
Preferably, described boron diffusion impervious layer is by SiGe layer and the n-layer laminated construction of Si layer stacked above one another or by the p layer stacked structure of SiGe layer and SiC layer stacked above one another, and wherein, n, p are the integer more than or equal to 2.
Preferably, the thickness of constitute described boron diffusion impervious layer each layer is 10～50 angstroms.
Preferably, form the source gas that described boron diffusion impervious layer used to comprise containing silicon source gas and the gas Han ge source.
Preferably, forming the selective epitaxial growth that described boron diffusion impervious layer used is to carry out under pressure is 1～100 torr and process conditions that temperature is 500～1000 degrees Celsius.
Preferably, formed the selective epitaxial growth that described boron diffusion impervious layer used be pressure be 5～50 torr, the flow velocity of HCl be 30～150sccm, GeH4Flow velocity be 2～100sccm, SiH2Cl2Flow velocity be 10～500sccm and GeH4/SiH2Cl2Process conditions that velocity ratio is 1: 5～1: 250 under carry out.
Preferably, form the source gas that described boron diffusion impervious layer used and also comprise carbonaceous sources gas.
Preferably, described twice selective epitaxial growth is carried out in same technological reaction chamber.
Preferably, described semiconductor device is that embedded germanium silicon strains PMOS device.
Preferably, described method also includes: after forming described boracic germanium silicon stressor layers, forms silicon cap layer in described boracic germanium silicon stressor layers.
Preferably, described grid structure includes gate dielectric, gate material layers and the grid hard masking layer stacked gradually.
The method according to the invention can suppress the boron being entrained in SiGe stressor layers by original position SiGeB stress introducing technology to be diffused in channel region due to follow-up Technology for Heating Processing, thus effectively prevent short-channel effect, and then improve the electric property of the PMOS transistor ultimately formed.Additionally, the method can also be mutually compatible with conventional CMOS manufacturing process.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, it is used for explaining the principle of the present invention.
In accompanying drawing:
Figure 1A-1C is to illustrate that method makes embedded germanium silicon according to an exemplary embodiment of the present invention to strain the schematic cross sectional view in PMOS device configuration process；
Fig. 2 shows according to an exemplary embodiment of the present invention for making the flow chart of the method for embedded germanium silicon strain PMOS device structure；And
Fig. 3 shows the curve chart of the variation tendency of impurity concentration in Semiconductor substrate.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to the restricted root exemplary embodiment according to the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to include plural form.In addition, it is to be further understood that, when using term " to comprise " in this manual and/or time " including ", it indicates and there is described feature, entirety, step, operation, element and/or assembly, but does not precludes the presence or addition of other features one or more, entirety, step, operation, element, assembly and/or combinations thereof.
[exemplary embodiment]
Describe method according to an exemplary embodiment of the present invention next, with reference to Figure 1A-1C and Fig. 2 and make the detailed step of embedded germanium silicon strain PMOS device structure.
Refer to Figure 1A-1C, the method according to an exemplary embodiment of the present invention that illustrated therein is makes the schematic cross sectional view in embedded germanium silicon strain PMOS device configuration process.
First, as shown in Figure 1A, it is provided that Semiconductor substrate 101, described Semiconductor substrate 101 is formed with grid structure 110, and will be formed in Semiconductor substrate 101 part of source/drain region is formed groove 102.
Wherein, the degree of depth of groove 102 can be such as 20～90nm.The constituent material of Semiconductor substrate 101 can use unadulterated monocrystal silicon, monocrystal silicon, silicon-on-insulator (SOI) or germanium silicon (SiGe) etc. doped with impurity.As example, in the present embodiment, Semiconductor substrate 101 selects single crystal silicon material to constitute.
As an example, grid structure 110 can include gate dielectric 103, gate material layers 104 and the grid hard masking layer 105 stacked gradually, as shown in Figure 1A.Gate dielectric 103 can include oxide, e.g., silicon dioxide (SiO2) layer.Gate material layers 104 can include one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer.Wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride layer can include titanium nitride (TiN) layer；Conductive metal oxide layer can include titanium oxide (IrO2) layer；Metal silicide layer can include titanium silicide (TiSi) layer.Grid hard masking layer 105 can include one or more in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon.Wherein, oxide skin(coating) can include boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethyl orthosilicate (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD).Nitride layer can include silicon nitride (Si3N4) layer.Oxynitride layer can include silicon oxynitride (SiON) layer.
As another example, grid structure 110 can be Semiconductor Oxide-Nitride Oxide-quasiconductor (SONOS) layer stacked gate structure.
As example, Semiconductor substrate 101 can also be formed and be positioned at grid structure 110 both sides and the offset by gap wall construction 106 against grid structure 110.Wherein, offset by gap wall construction 106 can include at least one of which oxide skin(coating) and/or at least one of which nitride layer.It should be noted that offset by gap wall construction 106 is optional and nonessential, its be mainly used in follow-up be etched or during ion implanting the sidewall of protection grid structure 110 injury-free.
Additionally, should give it is noted that the front-end devices structure that described herein and accompanying drawing is painted is not restrictive, but can also have other structures.Such as, Semiconductor substrate 101 can also be formed with isolation channel, buried regions etc..In addition, for PMOS transistor, Semiconductor substrate 101 can also be formed with N trap (not shown), and before forming grid structure 110, whole N trap can carry out once low dose of boron inject, for adjusting the threshold voltage V of PMOS transistorth。
Then, as shown in Figure 1B, selective epitaxial growth method is used to form a boron diffusion impervious layer 107 in uniform thickness on the bottom and sidewall of groove 102.Different from existing technique, boron diffusion impervious layer 107 the most bottom-up (bottom-up) grows, but grows on the bottom and sidewall of groove simultaneously.Further, since need to reserve enough spaces, so boron diffusion impervious layer 107 can not be the thickest, in case filling up whole groove for the boracic germanium silicon stressor layers being subsequently formed.Such as, the thickness of boron diffusion impervious layer 107 may be about 5～300 angstroms.
As example, in the present embodiment, boron diffusion impervious layer 107 is single layer structure, for example, it is possible to be pure SiGe inculating crystal layer.
As example, the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE) can be used for forming the selective epitaxial growth of boron diffusion impervious layer 107.Described selective epitaxial growth can be carried out in UHV/CVD reaction chamber.Described selective epitaxial growth is to carry out under pressure is 1～100 torr and process conditions that temperature is 500～1000 degrees Celsius.
As example, the source gas that formation boron diffusion impervious layer 107 is used can comprise containing silicon source gas, and also can comprise containing at least one in ge source gas and carbonaceous sources gas.Wherein, described can be SiH containing silicon source gas4、SiH2Cl2(DCS)、SiHCl3(TCS) or its combination in any, described can be GeH containing ge source gas4, and described carbonaceous sources gas can be C2H4、H3Si-CH2-SiH2-CH3Or a combination thereof.Additionally, described source gas can also comprise H2And HCl.Wherein, H2As carrier gas (carriergas), HCl is as selective gas.
When boron diffusion impervious layer 107 uses the single layer structure being made up of pure SiGe inculating crystal layer, as an example, described source gas can comprise SiH4、GeH4、H2And HCl.Wherein, SiH4Flow velocity be 10～1000sccm, GeH4Flow velocity be 1～the flow velocity of 50sccm, HCl is 10～1000sccm and H2Flow velocity be 100～50000sccm.Here, sccm is under standard state, namely 1 atmospheric pressure, the flow of 1 cubic centimetre (1ml/min) per minute under 25 degrees Celsius.As another example, described source gas can comprise SiH2Cl2、GeH4、H2And HCl.Wherein, SiH2Cl2Flow velocity be 10～1000sccm, GeH4Flow velocity be 1～the flow velocity of 50sccm, HCl is 10～1000sccm and H2Flow velocity be 100～50000sccm.Preferably, pressure be 5～50 torr, the flow velocity of HCl be 30～150sccm, GeH4Flow velocity be 2～150sccm, SiH2Cl2Flow velocity be 10～500sccm and GeH4/SiH2Cl2The process conditions that velocity ratio is 1: 5～1: 250 under carry out selective epitaxial growth.This is because with this understanding, epitaxial growth speed on the bottom of groove 102 and sidewall can reach substantially the same, it is thus possible to obtain pure SiGe inculating crystal layer in uniform thickness, i.e. the thickness of the SiGe inculating crystal layer on bottom portion of groove is substantially the same with the thickness of the SiGe inculating crystal layer in recess sidewall.
In addition to single layer structure, boron diffusion impervious layer 107 can also be multiple structure.Such as, described boron diffusion impervious layer can be by SiGe layer and the n-layer laminated construction of Si layer stacked above one another or by the p layer stacked structure of SiGe layer and SiC layer stacked above one another.Wherein, n, p are the integer more than or equal to 2.In the middle of each layer constituting laminated construction, the thickness of each layer all can be 20～50 angstroms.It is noted herein that, described multiple structure includes the laminated construction of only one of which SiGe/Si layer.Contrast to single layer structure compare, such multiple structure can more effectively suppress boron horizontal proliferation.
When boron diffusion impervious layer 107 uses SiGe/Si/SiGe laminated construction (i.e., n is 3) time, described selective epitaxial growth actually includes three phases, in each stage, different source gas compositions can be selected, to form the SiGe monolayer or Si monolayer being constituted laminated construction respectively.Such as, in the first stage, source gas can comprise SiH4、GeH4、H2And HCl, to form SiGe layer, in second stage, source gas can comprise SiH4、H2And HCl, to form Si layer, and in the phase III, source gas can comprise the source gas identical with the source gas of first stage, again to form SiGe layer.Certainly, the source gas being different from the first stage can also be used to form in the phase III.Here, need to attention is that, although various the various of source gas that may construct and used for forming such multiple structure not enumerating multiple structure may form, but these may be readily apparent that by composition to those skilled in the art.Such as, boron diffusion impervious layer 107 can also be SiGe/Si/SiGe/Si laminated construction (that is, n is 4) or SiGe/SiC/SiGe/SiC laminated construction (that is, p is 4) etc..
In addition, also need to be explained, unlike the prior art, according to the present invention, the boron diffusion impervious layer 107 that thickness is substantially the same can be formed such that it is able to effectively suppress the boron horizontal proliferation in the boracic SiGe stressor layers being subsequently generated on the bottom of groove 102 with sidewall.
Finally, as shown in Figure 1 C, selective epitaxial growth method is used to form boracic SiGe stressor layers 108 on boron diffusion impervious layer 107.
As example, can use and the previous technique identical for the selective epitaxial growth forming boron diffusion impervious layer 107 for forming the selective epitaxial growth of boracic SiGe stressor layers 108, such as, low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) or molecular beam epitaxy (MBE) etc..Certainly, twice extension can also use different technique.Twice selective epitaxial growth can be carried out in same reaction chamber, and such as, twice extension all uses (in-situ) epitaxy technology in situ.It is to carry out under pressure is 1～100 torr and process conditions that temperature is 500～1000 degrees Celsius for forming the selective epitaxial growth of boracic SiGe stressor layers 108.
As example, the source gas that formation boracic SiGe stressor layers 108 is used can comprise containing silicon source gas, containing boron source gas and the gas Han ge source.Wherein, described SiH is comprised containing silicon source gas4、SiH2Cl2And SiHCl (DCS)3(TCS) at least one in, described comprises B containing boron source gas2H6And BH3In at least one, and described be GeH containing ge source gas4.Additionally, the source gas that formation boracic SiGe stressor layers 108 is used can also comprise H2And HCl.Wherein, H2As carrier gas, HCl is as selective gas.
As an example, the source gas that formation boracic SiGe stressor layers 108 is used can comprise SiH4、GeH4、B2H6、H2And HCl.Wherein, SiH4、GeH4And B2H6Flow velocity be 1～500sccm, H2Flow velocity be 100～50000sccm, and the flow velocity of HCl is 10～1000sccm.As another example, the source gas that formation boracic SiGe stressor layers 108 is used can comprise SiH2Cl2、GeH4、BH3、H2And HCl.Wherein, SiH4、GeH4And B2H6Flow velocity be 1～500sccm, H2Flow velocity be 100～50000sccm, and the flow velocity of HCl is 10～1000sccm.Here, need to attention is that, although not enumerating the various of source gas may form, but these may be readily apparent that by composition to those skilled in the art.And, the process conditions and the parameter that form boracic SiGe stressor layers the most also can easily be known.
Here, more specifically, the method for above-mentioned making boracic SiGe stressor layers is merely exemplary, and nonrestrictive.Additive method can be used to form boracic SiGe stressor layers, such as, first on boron diffusion impervious layer, form one layer of pure SiGe stressor layers by selective epitaxial growth, the most again by ion implantation technology by boron ion implanting to this layer SiGe stressor layers, be consequently formed boracic SiGe stressor layers.
So far, the method according to an exemplary embodiment of the present invention that completes makes whole processing steps of embedded germanium silicon strain PMOS device structure.
Here, need to be explained, utilize the PMOS device structure that the method according to the invention makes, subsequent technique (such as, annealing optimization process, self-aligned silicide process and metal interconnection etc.) can be passed through and complete the making of whole PMOS transistor.Certainly, PMOS transistor alleged by the present invention also includes the PMOS transistor in cmos device.Here, special instruction is a bit, generally being formed after boracic SiGe stressor layers, one layer of monocrystalline silicon layer or the relatively low SiGe layer (also known as silicon cap layer (Sicap)) of germanium concentration can be formed the most again, before interconnecting at metal, form self-aligned silicide.
Refer to Fig. 2, illustrated therein is the flow chart of method according to an exemplary embodiment of the present invention, for schematically illustrating the flow process of whole method.
First, in step s 201, it is provided that Semiconductor substrate, it is formed with grid structure on the semiconductor substrate, and will be formed in described Semiconductor substrate in the part of source/drain region and be formed with groove.
Then, in step S202, selective epitaxial growth method is used to form boron diffusion impervious layer in uniform thickness on the bottom and sidewall of described groove.
Finally, in step S203, selective epitaxial growth method is used to form boracic SiGe stressor layers on described boron diffusion impervious layer.
Here, it should be noted that, although the upper surface of boracic SiGe stressor layers is shown as the upper surface flush with Semiconductor substrate in Figure 1A-1C, but this is only exemplary, present invention additionally comprises the upper surface of boracic SiGe stressor layers and the inequal situation of upper surface of Semiconductor substrate.Such as, applying suitable stress in order to ensure to channel region, the SiGe stressor layers of grid structure both sides the most all can be higher than the upper surface of Semiconductor substrate.
[beneficial effects of the present invention]
Below, the beneficial effect that Fig. 3 illustrates that exemplary embodiment of the present is obtained will be combined.This curve chart utilizes MonteCarlo method to carry out computer-aided test (TCAD) emulation under SynopsysTsuprem4&Medici simulated environment and obtain.Wherein, single crystal silicon material is selected to constitute Semiconductor substrate.As the example of the present invention, source/drain region stress introduces structure and uses the situation of SiGe inculating crystal layer/boracic SiGe stressor layers/Si cap layers multiple structure.And conventionally, source/drain region stress introduces structure and uses boracic SiGe stressor layers/Si cap layer structure.
Refer to Fig. 3, illustrated therein is the variation tendency of impurity concentration in bulk silicon substrate.Abscissa is the degree of depth from surface of silicon, and left side vertical coordinate is the boron impurity concentration in silicon substrate, and right side vertical coordinate is the degree of germanium in silicon substrate.Needing special instruction a bit, silicon substrate referred to herein includes boron diffusion impervious layer and boracic SiGe layer.
In Fig. 3, shown in curve L11 and curve L12, it is respectively the boron near by source/drain region in the PMOS device structure of the method making of the present invention and the concentration profile of germanium.It is respectively in the PMOS device structure made by existing method the boron near source/drain region and the concentration profile of germanium shown in curve L21 and curve L22.
It is clear that owing to the present invention defines a layer thickness uniform SiGe inculating crystal layer, so restrained effectively boron diffusion outside boracic SiGe stressor layers in advance being formed before boracic SiGe stressor layers on the bottom and sidewall of groove from Fig. 3.Need to be understood by, although the contrast effect of curve L11 Yu L21 illustrate only the improvement that boron is diffused on silicon substrate depth direction, but it is not difficult to deduce by reasonable prediction, boron is diffused on the direction vertical with silicon substrate depth direction (that is, on parallel with raceway groove direction) can be improved too.
[industrial applicibility of the present invention]
The semiconductor device manufactured according to embodiment as above can be applicable in multiple integrated circuit (IC).Such as, IC according to the present invention can be memory circuitry, such as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) or read only memory (ROM) etc..IC according to the present invention can also is that logical device, such as programmable logic array (PLA), special IC (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or any other circuit devcies.Such as, may be used in consumer electronic products according to the IC chip of the present invention, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention in described scope of embodiments.Additionally, it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (7)
1. the method being used for producing the semiconductor devices, described method includes:
Thering is provided Semiconductor substrate, be formed with grid structure on the semiconductor substrate, and will be formed in described Semiconductor substrate and be formed with groove in the part of source/drain region, the degree of depth of described groove is 20～90nm；
Selective epitaxial growth method is used to form the boron diffusion impervious layer of the boron horizontal proliferation in the boracic germanium silicon stressor layers that suppression is subsequently generated in uniform thickness on the bottom and sidewall of described groove, wherein, described boron diffusion impervious layer is by SiGe layer and the n-layer laminated construction of Si layer stacked above one another or for by the p layer stacked structure of SiGe layer and SiC layer stacked above one another, wherein, n, p are the integer more than or equal to 2；And
Selective epitaxial growth method is used to form boracic germanium silicon stressor layers on described boron diffusion impervious layer；
Wherein, the thickness of constitute described boron diffusion impervious layer each layer is 20～50 angstroms；
Forming the selective epitaxial growth that described boron diffusion impervious layer used is to carry out under the process conditions that temperature is 500～1000 degrees Celsius, formed the selective epitaxial growth that described boron diffusion impervious layer used be pressure be 5～50 torr, the flow velocity of HCl be 30～150sccm, GeH4Flow velocity be 2～100sccm, SiH2Cl2Flow velocity be 10～500sccm and GeH4/SiH2Cl2The process conditions that velocity ratio is 1:5～1:250 under carry out, so that described boron diffusion impervious layer grows on the bottom and sidewall of groove simultaneously.
Method the most according to claim 1, it is characterised in that form the source gas that described boron diffusion impervious layer used and comprise containing silicon source gas and the gas Han ge source.
Method the most according to claim 2, it is characterised in that form the source gas that described boron diffusion impervious layer used and also comprise carbonaceous sources gas.
Method the most according to claim 1, it is characterised in that twice selective epitaxial growth is carried out in same technological reaction chamber.
Method the most according to claim 1, it is characterised in that described semiconductor device is that embedded germanium silicon strains PMOS device.
Method the most according to claim 1, it is characterised in that farther include: after forming described boracic germanium silicon stressor layers, forms silicon cap layer in described boracic germanium silicon stressor layers.
Method the most according to claim 1, it is characterised in that described grid structure includes gate dielectric, gate material layers and the grid hard masking layer stacked gradually.
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| CN103779216B (en) * | 2012-10-18 | 2016-09-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of semiconductor device |
| CN103794559A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for preparing same |
| US8890119B2 (en) | 2012-12-18 | 2014-11-18 | Intel Corporation | Vertical nanowire transistor with axially engineered semiconductor and gate metallization |
| CN104064464A (en) * | 2013-03-21 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN104201108B (en) * | 2014-08-27 | 2017-11-07 | 上海集成电路研发中心有限公司 | The manufacture method of SiGe source /drain region |
| CN106611789B (en) * | 2015-10-26 | 2019-07-02 | 中芯国际集成电路制造(上海)有限公司 | Fin formula field effect transistor and forming method thereof |
| CN107302028B (en) * | 2016-04-15 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108962987B (en) * | 2017-05-19 | 2020-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
| US10727131B2 (en) * | 2017-06-16 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain epitaxy re-shaping |
| CN113013232A (en) * | 2021-02-24 | 2021-06-22 | 上海华力集成电路制造有限公司 | Method for improving device performance through selective epitaxy |
| CN115863396B (en) * | 2023-01-29 | 2023-05-12 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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