CN104022043A - Groove type power MOSFET with split gates and manufacturing method - Google Patents
Groove type power MOSFET with split gates and manufacturing method Download PDFInfo
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- CN104022043A CN104022043A CN201410267324.1A CN201410267324A CN104022043A CN 104022043 A CN104022043 A CN 104022043A CN 201410267324 A CN201410267324 A CN 201410267324A CN 104022043 A CN104022043 A CN 104022043A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention relates to a semiconductor device managed by a power source, and particularly provides a power MOSFET and a corresponding manufacturing method, wherein split gates are introduced into the power MOSFET of a groove structure. Shield gates at the lower portion inside active grooves or termination grooves are electrically led out and are connected to a source electrode metal layer on the upper surface of a silicon wafer, so that the shield gates and a source electrode are equipotential, and control gates at the upper portion inside the active grooves or the termination grooves are insulated from the shield gates.
Description
Technical field
The present invention relates to a kind of semiconductor device of power management, more precisely, the present invention aims to provide and a kind ofly in the power MOSFET tube of groove structure, introduces splitting bar and corresponding preparation method is provided.
Background technology
For the semiconductor device being conventionally used in power electronic system and power management, power metal oxide semiconductor field-effect transistor MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), or isolated-gate field effect transistor (IGFET), extensively introduced.
It is efficient, the device for power switching that new development is got up after MOSFET for groove type power MOS FET, and it adopts groove-shaped grid structure field effect transistor, and it is high by (>=10 that it has not only inherited metal-oxide-semiconductor field effect transistor input impedance
8Ω), the advantage of drive current little (0.1 about μ A), the good characteristic such as also there is withstand voltage height, operating current is large, power output is high, transconductance linearity is good, switching speed is fast.Just because of it, the advantage of electron tube and power transistor is rolled into one, therefore in the circuit such as Switching Power Supply, inverter, voltage amplifier, power amplifier, obtain extensive use.Therefore, high-breakdown-voltage, large electric current, low on-resistance are the most key indexs of power MOSFET.But concerning power MOSFET, can obtain high-breakdown-voltage and low on-resistance hardly simultaneously, thereby reach the object of power consumption less when large current work, need in puncture voltage and two indexs of conducting resistance, compromise mutually.
For optimised devices structure as far as possible reaches higher puncture voltage and the object of low on-resistance, groove type double-layer grid power field effect transistor (Split Gate MOSFET) is arisen at the historic moment.It is mainly by groove bottom integrated one improve puncture voltage with the field plate effect of the shield grid of source shorted.Therefore, under the requirement of same breakdown voltage, can reduce by increasing the doping content of silicon epitaxy layer the conducting resistance of power MOSFET, thus the power consumption while reducing large current work.But this layer of shielded gate structures greatly increased the difficulty that technique realizes, and increased the processing cost of device.
The present invention is intended to reduce light shield level as far as possible, and simplified processing process, realize groove type double-layer grid structure power MOSFET device, both reduced difficulty of processing, thereby reduced processing cost, and can realize high-breakdown-voltage, low on-resistance and improve rate of finished products.Finally strengthened the market competitiveness of device.
Existing groove type double-layer grid power MOS FET is in order to realize the object of shield grid and source shorted, or shield grid is directly received to groove top, or realizes by open deep hole on shield grid.Front a kind of scheme need to increase light shield level, and need very expensive technique to realize, as the oxide layer increasing between shield grid light shield and the double-deck grid of another layer of light shield thickening increased the puncture voltage between double-deck grid afterwards, and reduce the parasitic capacitance between double-deck grid.And this scheme need to adopt as very expensive techniques such as high concentration plasma reinforced chemical vapor deposition (High Density Plasma Chemical Vapor Deposition) and cmps (CMP-Chemical Mechanical Polish), thereby strengthened device fabrication difficulty, reduce technology controlling and process precision, be unfavorable for realizing high yield.Rear a kind of scheme also need to dug out deep hole by the place of shield grid and source shorted, by chemical vapour deposition (CVD) metal, realizes.Need to after shield grid, increase so on the one hand one deck light shield with retain need to be above the shield grid with source shorted thick oxide layer, need to adopt the expensive process such as HDP and CMP equally.And on shield grid, open the chemical gaseous phase depositing process realization metallization that deep hole need to be expensive, increase technology difficulty and increased device reliability risk.
This programme, by changing process sequence, looks for another way, and has both reduced light shield level, does not also need expensive technique, has realized groove type double-layer grid structure power MOSFET.
Summary of the invention
In one embodiment, a kind of preparation method of the groove-type power device with splitting bar, comprise the following steps: the top of steps A, an epitaxial loayer on base substrate etches a termination groove and a plurality of active groove, wherein, termination groove can not be also annular and being just arranged side by side with active groove, only when add field plate on substrate time, need to set termination groove and be annular; Step B, first insulating barrier of generation, be covered in termination groove and active groove sidewall and bottom separately, is covered on the end face of epitaxial loayer simultaneously; Step C, at termination groove, active groove under-filled electric conducting material separately, as shield grid; Step D, etching remove termination groove, active groove the first insulating barrier on upper portion side wall place and epitaxial loayer end face separately, and above each shield grid, prepare a separator; Step e, generate the second insulating barrier, cover termination groove and active groove separately on the exposed sidewall in top, be covered on the end face of epitaxial loayer simultaneously; Step F, at termination groove, active groove top filled conductive material separately, as control gate step G, in termination groove etching control gate and separator, define one or more through holes that expose shield grid; Step H, a top medium layer that has merged the second insulating barrier on epitaxial loayer end face of formation, be covered on epitaxial loayer end face and each control gate, synchronously forms the sidewall that a sidepiece dielectric layer is attached to through hole; Step I, filled conductive material are to through hole; Step J, an insulating passivation layer of formation are covered on top medium layer and through hole; Step K, etching insulating passivation layer at least form first set contact hole wherein, fill subsequently metal plug to first set contact hole and on top medium layer, depositing a metal layer at top, the metal plug arranging in first set contact hole is electrically connected electric conducting material and the metal layer at top in through hole.
Said method, in step C, comprises the following steps: deposits conductive material for the first time, covers the top of the first insulating barrier on epitaxial loayer end face, and be filled in termination groove and active groove; Return and carve electric conducting material, retain termination groove, the active groove electric conducting material of bottom separately, as shield grid.
Said method, in step D, comprises the following steps: deposition insulant, is covered in the top of the first insulating barrier on epitaxial loayer end face, and is filled in termination groove and active groove top separately; Return to carve and to remove insulant, and return to carve to remove and be covered in termination groove, active groove the first insulating barrier on upper portion side wall place and epitaxial loayer end face separately, a nationality that retains each shield grid top is returned the separator of carving and staying by insulant.
Said method, in step F, comprises the following steps: deposits conductive material for the second time, covers the top of the second insulating barrier on epitaxial loayer end face, and be filled in the top of termination groove and active groove; Return and carve electric conducting material, retain termination groove, the active groove electric conducting material on top separately, as control gate.
Said method, in step G, comprises the following steps: on the second insulating barrier top on epitaxial loayer end face and the top of each control gate, form a photoresist layer; Nationality is controlled the opening of gate region for inner minute in photoresist layer for exposing termination groove, control gate and the separator in etching termination groove, forms one or more through holes that expose shield grid downwards.
Said method, in step H, comprise the following steps: above the second insulating barrier on epitaxial loayer end face, prepare the insulating medium layer with the identical material of the second insulating barrier, original the second insulating barrier on this SI semi-insulation dielectric layer and epitaxial loayer end face merges and forms in a top medium layer, and this top medium layer is covered on epitaxial loayer end face and each control gate; The synchronous another part insulating medium layer forming is also attached on the sidewall that through hole is exposed to form sidepiece dielectric layer.
Said method, after step H, comprise the following steps: directly utilize top medium layer as etch mask, dry etching removes in the step that generates top medium layer and sidepiece dielectric layer and is synchronously covered in the insulating medium layer at the exposed region place of the shield grid below through hole.
Said method, in step I, comprises the following steps: deposits conductive material for the third time, covers the top of the top medium layer on epitaxial loayer end face and be filled in through hole; Return and carve electric conducting material, retain the electric conducting material in through hole.
Said method, in step F, G, H, I after any one step, but before step J, further comprising the steps of: at least at the top of the epitaxial loayer of termination groove inner side, to implant alloy and form a body layer, be centered around each active groove top around; Near and the one source pole layer implanting alloy formation epitaxial loayer end face at the top of body layer.
Said method, when step K etching insulating passivation layer, also comprise downwards etching insulating passivation layer, top medium layer, source layer and body layer successively, form and extend in body layer and second overlapping contact hole between adjacent active groove or between active groove and termination groove; And also in the second cover contact hole, fill metal plug subsequently, the metal plug in formed metal layer at top and the second cover contact hole forms in electrical contact.
Said method, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at electric conducting material in described through hole, thereby the metal plug of filling in first set contact hole is electrically connected the electric conducting material in through hole.
Said method, in step I, comprise the following steps: when returning the electric conducting material depositing for the third time quarter, also retain a part of electric conducting material overlap on termination groove as a field plate, wherein, this part electric conducting material termination groove outside expansion in the horizontal direction that forms this field plate is extended, until extend near epitaxial loayer periphery edge.
Said method, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at this field plate, thereby the metal plug of filling in first set contact hole is electrically connected to the electric conducting material in the through hole of field plate below via field plate.
In the device architecture of an optional embodiment, a kind of groove-type power device with splitting bar, comprising: base substrate and be positioned at the epitaxial loayer on base substrate; Be formed in epitaxial loayer one for example termination groove and a plurality of active groove of annular, wherein, termination groove can not be also annular and be just arranged side by side with active groove, it is annular only when add field plate on substrate time, need to setting termination groove; Be filled in respectively active groove, termination groove separately bottom shield grid and be filled in their control gates on top separately, between a control gate of each shield grid and its top, be provided with a separator insulation; At least be formed on termination groove inner side epitaxial loayer top and be centered around each active groove top body layer around, and the one source pole layer that is formed on body layer top; Run through successively downwards on one or more sidewalls of control gate, separator in termination groove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole; The top medium layer that is positioned on epitaxial loayer end face and each control gate is covered and be positioned at an insulating passivation layer on top medium layer; Downwards run through successively insulating passivation layer, top medium layer and source layer and extend to body layer in and second overlapping contact hole between adjacent active groove or between active groove and termination groove, and running through insulating passivation layer downwards and aim at the first set contact hole of the interior electric conducting material of described through hole; Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer; The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.
In another optional embodiment, a kind of groove-type power device with splitting bar comprises: base substrate and be positioned at an epitaxial loayer on base substrate; Be formed in epitaxial loayer one for example termination groove and a plurality of active groove of annular, wherein, termination groove can not be also annular and being just arranged side by side with active groove, and it is annular only when add field plate on substrate time, need to setting termination groove; Be filled in respectively active groove, termination groove separately bottom shield grid and be filled in their control gates on top separately, between a control gate nationality of each shield grid and its top, be provided with a separator; At least be formed on termination groove inner side epitaxial loayer top and be centered around each active groove top body layer around, and the one source pole layer that is formed on body layer top; Run through successively downwards on one or more sidewalls of control gate, separator in termination groove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole; A top medium layer that is positioned on epitaxial loayer end face and each control gate is covered; Be positioned on top medium layer and overlap on the field plate on termination groove, field plate outwards extends to the outside of termination groove in the horizontal direction; When being arranged on top medium layer, also envelope the insulating passivation layer of described field plate; Downwards run through successively insulating passivation layer, top medium layer and source layer and extend to body layer in and second overlapping contact hole between adjacent active groove or between active groove and termination groove, and running through insulating passivation layer downwards and aim at the first set contact hole of this field plate; Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer; The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.
Preparation method at other with the groove-type power device of splitting bar, has cancelled termination groove, comprises the following steps: the top of steps A, an epitaxial loayer on base substrate etches a plurality of grooves that are arranged in parallel; Step B, first insulating barrier of generation, be covered in each trenched side-wall and bottom, and be covered on the end face of epitaxial loayer; Step C, at the under-filled electric conducting material of groove, as shield grid; Step D, etching remove the first insulating barrier on groove upper portion side wall place and epitaxial loayer end face, and above each shield grid, prepare a separator; Step e, generate the second insulating barrier, on the exposed sidewall in covering groove top, be covered on the end face of epitaxial loayer simultaneously; Step F, at groove top filled conductive material, as control gate; Step G, in part groove etching control gate and separator, define one or more through holes that expose shield grid; Step H, a top medium layer that has merged the second insulating barrier on epitaxial loayer end face of formation, be covered on epitaxial loayer end face and each control gate, synchronously forms the sidewall that a sidepiece dielectric layer is attached to through hole; Step I, filled conductive material are to through hole; Step J, an insulating passivation layer of formation are covered on top medium layer and through hole; Step K, etching insulating passivation layer at least form first set contact hole wherein, fill subsequently metal plug to first set contact hole and on top medium layer, depositing a metal layer at top, the metal plug arranging in first set contact hole is electrically connected electric conducting material and the metal layer at top in through hole.Here the groove sayed can be active groove.
Said method, in step C, comprises the following steps: deposits conductive material for the first time, covers the top of the first insulating barrier on epitaxial loayer end face, and be filled in groove; Return and carve electric conducting material, retain the electric conducting material of groove bottom, as shield grid.
Said method, in step D, comprises the following steps: deposition insulant, is covered in the top of the first insulating barrier on epitaxial loayer end face, and is filled in the top in groove; Return and remove insulant quarter, and remove the first insulating barrier being covered on groove upper portion side wall place and epitaxial loayer end face time quarter, a nationality that retains each shield grid top is returned the separator of carving and staying by insulant.
Said method, in step F, comprises the following steps: deposits conductive material for the second time, covers the top of the second insulating barrier on epitaxial loayer end face, and be filled in the top of groove; Return and carve electric conducting material, retain the electric conducting material on groove top, as control gate.
Said method, in step G, comprises step: on the second insulating barrier top on epitaxial loayer end face and the top of each control gate, form a photoresist layer; Nationality is controlled the opening of gate region for inner minute in photoresist layer for exposing pregroove, control gate and the separator in this pregroove of etching, forms one or more through holes that expose shield grid downwards.
Said method, in step H, comprise the following steps: above the second insulating barrier on epitaxial loayer end face, prepare the insulating medium layer with the identical material of the second insulating barrier, original the second insulating barrier on this SI semi-insulation dielectric layer and epitaxial loayer end face merges and forms in a top medium layer, and this top medium layer is covered on epitaxial loayer end face and each control gate; The synchronous another part insulating medium layer forming is also attached on the sidewall that through hole is exposed to form sidepiece dielectric layer.
Said method, after step H, comprise the following steps: directly utilize top medium layer as etch mask, dry etching removes in the step that generates top medium layer and sidepiece dielectric layer and is synchronously covered in the insulating medium layer at the exposed region place of the shield grid below through hole.
Said method, in step I, comprises the following steps: deposits conductive material for the third time, covers the top of the top medium layer on epitaxial loayer end face and be filled in through hole; Return and carve electric conducting material, retain the electric conducting material in through hole.
Said method, after step F, G, H, any one step of I, but before step J, comprise the following steps: in all a plurality of grooves, outermost two grooves of take are boundary, alloy need be implanted in the top that limits the epitaxial loayer of their inner sides, and at least the top of the epitaxial loayer inside outermost groove is implanted alloy and formed a body layer, is centered around each groove top around; Near and the one source pole layer implanting alloy formation epitaxial loayer end face at the top of body layer.
Said method, when step K etching insulating passivation layer, also comprises downwards etching insulating passivation layer, top medium layer, source layer and body layer successively, forms the second cover contact hole extending in body layer and between adjacent trenches; And also in the second cover contact hole, fill metal plug subsequently, the metal plug in formed metal layer at top and the second cover contact hole forms in electrical contact.
Said method, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at electric conducting material in described through hole, thereby the metal plug of filling in first set contact hole is electrically connected the electric conducting material in through hole.
In other optional embodiment, a kind of groove-type power device with splitting bar, has cancelled termination groove, comprising: base substrate and be positioned at an epitaxial loayer on base substrate; Be formed on a plurality of grooves in epitaxial loayer; Be filled in the shield grid and the control gate that is filled in groove top of groove bottom, between each shield grid and a control gate of its top, be provided with a separator insulation; Among a plurality of grooves side by side, the epitaxial loayer top of the inner side of outermost two grooves (for boundary) is formed with a body layer, body layer is centered around each groove top around, an and source layer that is formed on body layer top, can certainly form body layer at the epitaxial loayer top in the outside of outermost two grooves (being boundary), formation source layer also can adulterate at the top of this part body layer in outside; Run through successively downwards on one or more sidewalls of control gate, separator in a part of pregroove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole; The top medium layer that is positioned on epitaxial loayer end face and each control gate is covered and be positioned at an insulating passivation layer on top medium layer; Run through successively insulating passivation layer, top medium layer and source layer downwards and extend to the second cover contact hole in body layer and between adjacent trenches, and run through the first set contact hole of electric conducting material in insulating passivation layer aligned through holes downwards; Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer; The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.Here the groove sayed can be active groove.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.Yet appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Figure 1A～1Q is method flow schematic diagram of the present invention.
Fig. 2 fills at active groove and termination groove top the method schematic diagram that the polysilicon depositing is for the second time prepared thereafter body layer and source layer again.
Fig. 3 prepares the method schematic diagram of body layer and source layer again etch through hole in the polysilicon of active groove and the filling of termination groove top after.
Fig. 4 is the method schematic diagram that forms top medium layer and prepare body layer and source layer again on epitaxial loayer end face after through-hole side wall adheres to sidepiece dielectric layer.
Fig. 5 A～5C is that flow process based on Figure 1A～1Q but this extra field plate are used in device.
Fig. 6 is the local schematic top plan view of chip.
Fig. 7 is that chip is prepared after this field plate local schematic top plan view substantially.
Embodiment
In Figure 1A, a substrate comprises the base substrate 101a of a heavy doping N+ type, and also comprise and be positioned at of base substrate 101a top than base substrate and the lower light dope N-type epitaxial loayer 101b of doping content, can set base substrate 101a, epitaxial loayer 101b is the first conduction type.On the end face of epitaxial loayer 101b, deposition forms an illustrated hard mask layer 200, silicon dioxide layer for example, utilize known photoetching technique that default channel patterns is transferred in a photoresist layer not illustrating in the drawings, photoresist layer covers on hard mask layer 200, then using photoresist layer as etch mask, and utilize plasma etching or wet etching to offer opening figure in hard mask layer 200, the hard mask layer 200 of then usining with opening figure is as etch mask, thereby further at the top of epitaxial loayer 101b in the dry method mode of plasma, etch a plurality of active groove 102a and a termination groove 102b.A plurality of active groove 102a that are arranged side by side are arranged at the active area that this substrate is positioned at termination groove 102b inner side.In another alternative embodiment for preparing groove, directly spin coating photoresist is on epitaxial loayer 101b end face, replace hard mask layer 200, the photoresist layer of then usining with channel patterns is directly as etch mask, and with the dry etching of plasma, be exposed to the epitaxial loayer 101b region at photoresist layer split shed figure place, prepare active groove 102a and termination groove 102b, last photoresist layer need the same with hard mask layer 200 is stripped from.
In Figure 1B, in sidewall separately of active groove 102a and termination groove 102b and bottom by the thermal oxidation method sacrificial oxide layer of anticipating out not shown in the figures of growing, and then peel off sacrificial oxide layer in the mode of wet etching, sacrificial oxide layer is transiting product, for repairing the damage of trench wall and the inwall of formation even surface, and the bottom corners of corners groove.And then be for example thermal oxidation silicon layer by thermal oxide growth layer, the first insulating barrier 103 as a part of thickness, after again by the thicker for example oxide layer of low-pressure chemical vapor phase deposition (LPCVD) method growth one deck, the first insulating barrier 103 as another part thickness, LPCVD is used for further increasing the thickness of the first insulating barrier 103, the first insulating barrier 103 can be understood to be a composite bed, comprises thin silicon oxide layer and thick CVD oxide layer.Again pass through a high annealing to improve oxide layer compactness, thereby finally make the gross thickness of the first insulating barrier 103 reach design thickness value thereafter.In addition, at some in other alternative embodiment, the preparation implementation method of the first insulating barrier 103 has simple by step of thermal oxidation, or by LPCVD method, grows merely, usings for example oxide layer of the certain thickness densification that reaches required as the first insulating barrier 103.The first insulating barrier 103 is covered in active groove 102a and termination groove 102b whole sidewall and bottom separately, is also covered on the end face of epitaxial loayer 101b simultaneously.
In Fig. 1 C, the method for example depositing by LPCVD, forms illustrated electric conducting material 104, grows for example in-situ doped polysilicon with certain expection one-tenth-value thickness 1/10, and according to the present invention's spirit, this is deposits conductive material 104 for the first time.As shown in the figure, electric conducting material 104 covers the top of the first insulating barrier 103 on epitaxial loayer 101b end face, and electric conducting material 104 is also filled in the inner space of active groove 102a and termination groove 102b simultaneously.
In Fig. 1 D, the method of using plasma dry etching, returns and carves electric conducting material 104, does not adopt any extra mask here, and directly electric conducting material 104 being etched into the required degree of depth, the surface that as far as possible makes the etching of electric conducting material 104 form is comparatively smooth.Thereby utilize back quarter, remove that a part of electric conducting material 104 that is positioned at the first insulating barrier 103 tops on epitaxial loayer 101b end face, while active groove 102a and termination groove 102b separately that a part of electric conducting material 104 on top are also removed, thus, the just just leaving gap space on active groove 102a and termination groove 102b top separately.As shown in Fig. 1 D, only retain active groove 102a and the termination groove 102b electric conducting material 104 of bottom separately, as shield grid (Shield gate) 104a.
In Fig. 1 E, by method growth and the deposition insulant 105 of LPCVD, for example prepare silicon oxide layer, and by the annealing operation of higher temperatures, realize densification LPCVD insulant 105, insulant 105 is filled full active groove 102a and termination groove 102b top separately, and the aforementioned clearance space forming on groove top is insulated thing 105 completely and fills completely, and insulant 105 is covered in the top of the first insulating barrier 103 on epitaxial loayer 101b end face toward contact.In fact, insulant 105 is analogs of the same material of the first insulating barrier 103, when generating insulant 105, it with the first insulating barrier 103 between mutually the interface of boundary in the high-temperature process stage, almost can merge each other, and make both contact interfaces no longer so fairly obvious.At Fig. 1 F, insulant 105 is implemented back to carve in the step of corrosion, by wet method as utilized HF or BOE (to characterize HF and NH
4the mixed liquor of F solution), with the time, control the mode of etching degree, peel off all oxide layers in epitaxial loayer 101b surface and each groove upper portion side wall, but the oxide layer that retains polysilicon shield grid 104a upper surface, to improve the puncture voltage between shield grid 104a and subsequent control grid 107a.Particularly, need to predetermined etching remove the unwanted part of insulant 105: as a part of insulant 105, the insulant 105 of the first insulating barrier 103 tops on epitaxial loayer 101b end face are filled in active groove 102a and the termination groove 102b overwhelming majority on top separately.This time carved in step, also need synchronous corrosion to remove to be covered in active groove 102a and termination groove 102b first insulating barrier 103 at upper portion side wall place separately, and etching removes the first insulating barrier 103 on epitaxial loayer 101b end face.It is worth emphasizing that, although the major part of the insulant 105 in each groove has all been etched away, a nationality that still needs to retain each shield grid 104a top face is carved for 105 times by insulant and the separator 105a that stays.Attention is in this stage, active groove 102a and termination groove 102b are under-filled separately a shield grid 104a, the sidewall of groove bottom and bottom are still attached with the first insulating barrier 103, meanwhile, the clearance space of hollow has been formed again at active groove 102a and termination groove 102b top separately, and the end face of epitaxial loayer 101b is also out exposed.
In Fig. 1 G, generate second insulating barrier 106, typically for example pass through thermal oxidation method and a silicon dioxide layer of regrowth, now the second insulating barrier 106 covers active groove 102a and termination groove 102b separately on the exposed sidewall in top, the second insulating barrier 106 is also covered on epitaxial loayer 101b whole exposed end face or upper surface simultaneously, in fact, the second insulating barrier 106 that active groove 102a and termination groove 102b adhere on the sidewall on top is separately by the real grid oxic horizon in structure cell unit that is vertical furrow groove MOSFET device, this will continue to introduce below.
In Fig. 1 H, according to the present invention's spirit, deposits conductive material 107 for the second time, for example pass through LPCVD method, growing polycrystalline silicon layer, this polysilicon essence can be in-situ doped, or growth is not implemented after the polysilicon of doping in advance, then realizes polysilicon doping by Implantation or thermal diffusion method.Electric conducting material 107 covers the top of the second insulating barrier 106 on epitaxial loayer 101b end face, electric conducting material 107 is also filled among active groove 102a and termination groove 102b top separately simultaneously, and the clearance space that in Fig. 1 F, active groove 102a and termination groove 102b top separately form is originally filled up by the electric conducting material 107 of polysilicon again.Subsequently as shown in Figure 1 I, afterwards by plasma dry etching method, etching conductive material 107, electric conducting material is carved into certain degree 107 times, make the end face of the electric conducting material 107 of reservation in groove in the substantially flush position of the upper surface with the second insulating barrier 106, also return and be carved into the position that the top surface with epitaxial loayer 101b is close, as shown in Figure 1 I.Return and carve after electric conducting material 107, finally retain active groove 102a and the termination groove 102b electric conducting material 107 on top separately, as control gate (Control gate) 107a.
In Fig. 1 J, need to utilize a photoresist layer 208 as etch mask, the photoresist layer 208 of spin coating is covered in the top of whole this second insulating barrier 106 on epitaxial loayer 101b end face, and photoresist layer 208 also covers the over top of each control gate 107a simultaneously.Then utilize conventional photoetching technique, after exposure imaging, form several openings 208a in photoresist 208, opening 208a overlaps on the control gate 107a in termination groove 102b, according to the present invention's spirit, preferably, the width value of opening 208a on termination groove 102b Width is no more than the width value (also can say the width value that is upwards no more than control gate 107a the party) of termination groove 102b self.The photoresist layer 208 of now usining with opening 208a defines through hole 107b as etching screen, for the ease of observing and understanding, can be in conjunction with the step of 1K-1 to Fig. 1 K-3 that publishes picture, wherein in Fig. 1 K-1, do not demonstrate photoresist 208, in addition, Fig. 1 K-2 to Fig. 1 K-3 is the sectional elevation figure along dotted line AA in Fig. 1 K-1.
The concrete steps that etching defines through hole 107b are: by the dry etching of plasma, etch away the control gate 107a region of coming out in opening 208a below, for example, in Fig. 1 K-1 and Fig. 1 K-2, in the control gate 107a of termination groove 102b, etching has formed through hole 107b.Then do not peel off photoresist layer 208, still using it as etch mask, continue downward etching (here dry method or wet etching all can), until the separator 105a region that through hole 107b bottom exposes is also etched away, as shown in Fig. 1 K-3, but etching ends at the end face that shield grid 104a exposes.Therefore, the through hole 107b forming in the control gate 107a filling on termination groove 102b top runs through control gate 107a and separator 105a downwards successively, exposes the shadow shield grid 104a region that is positioned at through hole below from through hole 107b.In this etch step, select polysilicon and oxide layer to select than high dry etch process as far as possible, both realized the oxide layer that can etch through hole 107b and can not damage through hole 107b sidewall as the second insulating barrier 106.In preferred embodiment, the width value of through hole 107b on termination groove 102b Width is approximately equal to or slightly less than the width value of control gate 107a, is about to the original width W of termination groove 102b
tdeduct the one-tenth-value thickness 1/10 T of the second insulating barrier 106 of twice
o, approximate W
t-2T
o, need insulating barrier 106 thickness that adhere on two relative sidewalls of consideration termination groove 102b top.Thus, just realized nationality in photoresist layer 208 for exposing the patterning opening 208a in a part of control gate 107a region in termination groove 102b, control gate 107a and separator 105a in etching termination groove 102b, forms one or more through hole 107b that expose shield grid 104a regional area downwards.Watch in addition Fig. 1 K-1, along the length direction of termination groove 102b, a plurality of isolated through hole 107b can be set.As Fig. 1 K-3, after completing the etching of through hole 107b and removing the separator 105a of through hole 107b bottom, then etching removes photoresist layer 208.
In Fig. 1 L-1, need on epitaxial loayer 101b end face, prepare a top medium layer 108.For example, directly by the thicker oxide layer of low-pressure chemical vapor phase deposition (LPCVD) method growth one deck, as insulating medium layer (not indicating separately), it has the part that covers former the second insulating barrier 106 tops on epitaxial loayer 101b end face, this part insulating medium layer is also covered the exposed end face of each control gate 107a simultaneously, can think that top medium layer 108 is a total composite bed in fact, its fusion has comprised original the second insulating barrier 106 on epitaxial loayer 101b end face, with original the second prepared a part of insulating medium layer out in insulating barrier 106 tops having merged on epitaxial loayer 101b end face.Finally, the top medium layer 108 of acquisition is covered on epitaxial loayer 101b end face, is also covered on each control gate 107a end face simultaneously.It is worth emphasizing that, it is identical silicon dioxide material that second insulating barrier 106 here and prepared insulating medium layer can be selected in fact, and they can also select to adopt high annealing to improve the compactness of whole oxide layer.In addition, what must illustrate is, aforementioned LPCVD deposition generates in the step of thick oxide layer, the insulating medium layer (oxide) obtaining is not selectivity deposition or growth, actual conditions are tops that generated insulating medium layer is not only just covered in original the second insulating barrier 106 on epitaxial loayer 101b end face, equally, prepared insulating medium layer yet has the part on the sidewall that is attached to through hole 107b, this part insulating medium layer is defined as sidepiece dielectric layer 108a, as shown in Fig. 1 L-1 and Fig. 1 L-2.In other words, prepared an insulating medium layer with the second insulating barrier 106 identical material, it at least has the part that is covered in the second insulating barrier 106 tops on epitaxial loayer 101b end face, and this SI semi-insulation dielectric layer is fused into top medium layer 108 together with original the second insulating barrier 106 on epitaxial loayer 101b end face; Meanwhile, the synchronous another part insulating medium layer generating is also attached on the sidewall that through hole 107b is exposed, and to form sidepiece dielectric layer 108a, Fig. 1 L-2 has shown the result of this step.
Need another aspect of considering to be, in view of the insulating medium layer (oxide) obtaining is not selectivity deposition or growth, when interlock system is for top medium layer 108, sidepiece dielectric layer 108a, some insulating medium layer can be deposited on the bottom of through hole 107b naturally so, being arranged in shield grid 104a from the exposed location out of through hole 107b, is exactly the exposed region place that covers the shield grid 104a end face under through hole 107b in fact.According to the present invention's spirit, need to directly utilize top medium layer 108 as etch mask, and do not utilize extra mask, after adopting anisotropic dry etch step, the end face of shield grid 104a is positioned at this part insulating medium layer that place, region under through hole 107b covers and will be etched and removes, and this region is exactly exposed region out from through hole 107b.
In Fig. 1 M, carry out the step of deposits conductive material 109, electric conducting material 109 is for example prepared by the LPCVD method in-situ doped polysilicon of growing, or does not first remove the deposit spathic silicon that adulterates, and then by the polysilicon of Implantation or method of diffusion preparation doping.Deposits conductive material 109 is steps of deposit spathic silicon for the third time, and final, electric conducting material 109 covers the top of the top medium layer 108 on epitaxial loayer 101b end face, and electric conducting material 109 is also filled in each through hole 107b.Then as shown in Fig. 1 N-1, carry out back the step of carving electric conducting material 109.For example, by the dry etching method of plasma, return etching conductive material 109, to the electric conducting material in through hole 107b is carved into the position substantially flush with the top surface of top medium layer 108 for 109 go back tos, but the electric conducting material 109 of top medium layer 108 top on epitaxial loayer 101b end face will be eliminated.As shown in Fig. 1 N-2, thereby only retain the part electric conducting material 109a in through hole 107b.
For more detailed understanding through hole 107b and near the relative position relation of other each assemblies it, Fig. 1 N-3 has specially intercepted in Fig. 1 N-2 along the profile of the vertical section of dotted line BB.Fig. 1 N-3 is a fragment of termination groove 102b, shown 1/2nd of about termination groove 102b width, wherein on the sidewall of termination groove 102b bottom and bottom, be attached with the first insulating barrier 103, and there is a shield grid 104a termination groove 102b is under-filled, separator 105a is arranged on the end face of shield grid 104a, on the sidewall on termination groove 102b top, be coated with the second insulating barrier 106, the first insulating barriers 103 general much thicker than the second insulating barrier 106.In addition, on termination groove 102b top, be also filled with control gate 107a, and a control gate 107a directly over each shield grid 104a and it relies on their separator 105a between the two and isolation insulated from each other.Top medium layer 108 covers on the top end face of control gate 107a.According to illustrated structure, through hole 107b runs through control gate 107a, separator 105a downwards successively, and on the sidewall of through hole 107b, be coated with sidepiece dielectric layer 108a, so the electric conducting material 109a filling in through hole 107b relies on sidepiece dielectric layer 108a and control gate 107a to be enclosed in through hole 107b region insulation isolation around, but the electric conducting material 109a filling in through hole 107b but interconnects with shield grid 104a and has a relation in electrical contact, in addition, the electric conducting material 109a filling in through hole 107b is also out exposed from top medium layer 108.
In Fig. 1 O, can utilize one to inject mask, screen as Implantation, thereby alloy is implanted at the top of the epitaxial loayer 101b inside termination groove 102b, form a body layer 110, here the alloy that injected or ion are P type, it is the second conduction type with aforementioned the first conductivity type opposite, formed body layer 110 is centered around each active groove 102a top around, interface setting between attention body layer 110 and its below epitaxial loayer 101b is above the bottom surface of control gate 107a, to can form the raceway groove that vertical inversion layer is set up MOSFET unit along the sidewall of active groove 102a or termination groove 102b in body layer 110.And the alloy that continues subsequently to implant at the top of body layer 110 N+ type, forming a near source layer 111 of epitaxial loayer 101b end face, source layer 111 is also centered around each active groove 102a top around, but its depth ratio body layer 110 wants much shallow.Complete after the implantation of body layer 110, source layer 111 and just peelablely to fall injection mask of anticipating out not shown in the figures.In the embodiment of Fig. 1 O, the body layer of implanting 110, source layer 111 are arranged in the active area of termination groove 102b inner side, in the termination environment in termination groove 102b outside, do not form any body layer 110, source layer 111.But in the embodiment not showing in other figure, can save one and inject mask, do not adopt any ion implantation mask, and directly with integral type, cover the mode of injecting (blanket implant), not only at the top of the epitaxial loayer 101b of termination groove 102b inner side, form body layer 110 and formed source layer 111 at the top of the body layer 110 of this position, also body layer 110 has been formed on the top of the epitaxial loayer 101b outside termination groove 102b, formed source layer 111 with the top of body layer 110 at termination groove 102b outer fix place, in other words, active area and termination environment all globality injection body layer and source layer.
In Fig. 1 P, first deposit an insulating passivation layer 112 and cover on the top surface of top medium layer 108, the silex glass BPSG that for example adopts low temperature oxide LTO and/or contain boric acid.Insulating passivation layer 112 also covers the top of the electric conducting material 109a filling in each through hole 107b.After preparing insulating passivation layer 112, extra photoresist layer of spin coating again above insulating passivation layer 190, and photoetching development forms some patterns of openings wherein, utilize this photoresist layer as contact hole etching mask, through after suitable anisotropic dry etch, synchronously form some first set contact hole 112b, the second cover contact hole 112a that run through insulating passivation layer 112.When in Fig. 1 P, etching insulating passivation layer 112 is prepared the second cover contact hole 112a, mainly that preparation extends downwardly into the contact hole among the mesa structure of active area, comprise downwards etching insulating passivation layer 112 successively, top medium layer 108, the source layer 111 of active area, the body layer 110 of active area, formation extends downward the cover of second in body layer 110 contact hole 112a, second overlaps each contact hole in contact hole 112a or is arranged between adjacent two active groove 102a, or be arranged between outermost active groove 102a and near the termination groove 102b it (outermost active groove 102a is the active groove of the most close termination groove 102b in whole active groove 102a).When in Fig. 1 P, etching insulating passivation layer 112 is prepared first set contact hole 112b, be mainly contact hole of corresponding preparation on a through hole 107b, in first set contact hole 112, each contact hole overlaps on a through hole 107b and inner electric conducting material top thereof.Thus, in first set contact hole 102b, for formed each contact hole that runs through insulating passivation layer 112 downwards, its equal respective aligned and the electric conducting material 109a that contacts a through hole 107b who is positioned under it and fill.
In some embodiment that anticipate out not shown in the figures, utilization is autoregistration injection mask with the insulating passivation layer 112 of the second cover contact hole 112a, can also inject to the bottom of each contact hole of the second cover contact hole 112a the heavy doping ion of P+ type, form be located in body layer 110 and be arranged near the body contact zone each contact hole of the second cover contact hole 112a bottom, its doping content is larger than the doping content of body layer 110.
In certain embodiments, first fill in metal material (as tungsten) each contact hole in first set contact hole 112b, the second cover contact hole 112a, metal material in contact hole forms metal plug or metal joint, now, this metal plug is the technique that adopts an independent deposition procedures and then return etching, etching removes the unnecessary unwanted metal material in insulating passivation layer 112 tops, and only retains the metal material in each contact hole.In addition, in this embodiment, also need to deposit separately the top that a metal layer at top 113 covers whole insulating passivation layer 112, metal layer at top 113 be electrically connected/contacts with the metal plug formation in each contact hole in first set contact hole 112b, the second cover contact hole 112a again.The electric conducting material 109a filling in a through hole 107b due to its below of the equal respective aligned of each contact hole in first set contact hole 102b, so the metal plug in a contact hole directly over the electric conducting material 109a filling in each particular via 107b nature and this through hole 107b (belonging to first set contact hole) forms in electrical contact.
In some other optional embodiments, the metal material (metal plug) of filling in each contact hole in first set contact hole 112b, the second cover contact hole 112a synchronize with the metal material (metal layer at top 113) of insulating passivation layer 112 tops and is deposited generation, that is to say, metal plug in each contact hole and metal layer at top 113 are integrated in fact, now their material is identical, and the metal plug in metal layer at top 113 and first set contact hole 112b, the second cover contact hole 112a in each contact hole forms electric connection/contact naturally.
Power MOSFET device for plough groove type, metal layer at top 113 is presented as source electrode, the bottom metal layers not illustrating arranging on base substrate 101a bottom surface is presented as drain electrode, control gate 107a in each active groove 102a is communicated to a grid of not drawing out and picks up the electric conducting material in groove, and not shown in the figures anticipate out another run through insulating passivation layer 112, the contact hole of top medium layer 108 is set up to be aimed at and contacts grid and pick up the electric conducting material in groove, the electric conducting material of metal plug in this contact hole in grid picks up groove be electrically connected to be positioned at insulating passivation layer 112 tops another in the gate metal layer of gate electrode.
In the embodiment of Fig. 2～4, be the step based on Figure 1A～1Q, only change is the implantation formation of body layer 110 or source layer 111 have been done to some opportunity adjust, other step is in full accord and without any difference with Figure 1A～1Q.For example, in the step of Figure 1A～1Q, body layer 110 or source layer 111 are that the electric conducting material 109a in Fig. 1 O has formed through hole 107b just injects afterwards.But in the embodiment of Fig. 2, in Fig. 1 I, to prepare active groove 102a and termination groove 102b separately after the control gate 107a on top, and horse back successively injects the alloy of P type and N-type, form P type body layer 110 or N-type source layer 111, this has replaced the Implantation step of Fig. 1 O step originally.In the embodiments of figure 3, be after Fig. 1 K-3 peels off the step of photoresist layer 208, substep successively injects the alloy of P type and N-type at once, forms P type body layer 110 or N-type source layer 111, and this has replaced the Implantation step of Fig. 1 O step originally.In the embodiment of Fig. 4, after completing the top medium layer 108 and sidepiece dielectric layer 108a step of preparing Fig. 1 L-1, successively substep injects the alloy of P type and N-type, form P type body layer 110 or N-type source layer 111, this has replaced the Implantation step of Fig. 1 O step originally, in the embodiment of Fig. 4, illustrate above, the end face of shield grid 104a is positioned on that a part of regional area under through hole 107b can additionally cover a part of insulating medium layer, in Fig. 4, form so the injection timing of the alloy of body layer 110 or source layer 111, both before a part of insulating medium layer having covered on can the region under the end face that cleans out shield grid 104a is positioned at through hole 107b, also can be after cleaning out this part insulating medium layer, equally, here a part of insulating medium layer referring to forms with top medium layer 108 and sidepiece dielectric layer 108a simultaneously, only this part insulating medium layer is the bottom that is deposited on through hole 107b.
In the embodiment of Fig. 5 A～5C, it is the step based on Figure 1A～1Q, only change is (being Fig. 1 M to Fig. 1 N-1) in the step of the electric conducting material 109 that deposits for the third time in etching, be not only the electric conducting material 109a that has left expection in through hole 107b, synchronous also left this field plate consisting of the residual electric conducting material 109b of a part, other step is in full accord and without any difference with Figure 1A～1Q.As shown in Fig. 5 A～5B, utilize an extra photoresist layer (not illustrating) as etch mask, cover electric conducting material 109, then the electric conducting material 109 on etching top medium layer 108, the part that electric conducting material 109 overlaps on the epitaxial loayer 101a inside termination groove 109a is disposed by complete etching, but the local electric conducting material 109b that electric conducting material 109 overlaps on the epitaxial loayer 101a outside termination groove 109a is retained, the electric conducting material 109 that is equivalent to epitaxial loayer 101a periphery edge vicinity is retained, and this is retained the electric conducting material 109b getting off and also has the part overlapping on termination groove 102b simultaneously.Due to the shielding action of electric conducting material 109b, in through hole 107b, filled conductive material 109a is positioned under electric conducting material 109b, and by electric conducting material, 109b stops, and can not be etched away, so be retained.Thus, in through hole 107b, filled conductive material 109a and electric conducting material 109b are electrically connected in fact each other, are also integrated in their structures.This partially conductive material 109b as this field plate expands and extends to the outside of termination groove 102a in the horizontal direction directly over termination groove 102a, until extend near epitaxial loayer 101b periphery edge.Step than Fig. 1 P～1Q, due to some electric conducting material 109b additionally having more on top medium layer 108 and termination groove 102b, so the insulating passivation layer 112 of follow-up preparation also can be covered this electric conducting material 109b, at Fig. 5 C, prepare in first set contact hole 112b so, in the step of etching insulation passivation 112, form the first set contact hole 112b that runs through insulating passivation layer 112 downwards, each contact hole in first set contact hole 112b is aimed at and is contacted this field plate, thereby follow-up metal plug of filling in first set contact hole 112b, all can be electrically connected to via this field plate the electric conducting material 109a in through hole 107b below field plate.
The partial schematic diagram of substrate or chip has been shown in Fig. 6～7, substrate has the active area 170 of termination groove 102b inner side, termination environment 160 with termination groove 102b outside, the latter is round the former, the active groove 102a of some strips is set in termination groove 102b inner side, termination groove 102b is except having the part paralleling with active groove 102a, termination groove 102b is also connected with the end of active groove 102a perpendicular to the part of active groove 102a, among the control gate 107a on termination groove 102b top, etching has been prepared isolated a plurality of through hole 107b, and termination groove 102b, the active groove 102a separately shield grid 104a of bottom interconnects each other, take this by this conductive path of metal plug in the electric conducting material 109a in through hole 107b and first set contact hole 112b, can realize shield grid 104a is electrically connected in metal layer at top 113, make their equipotentiality.In Fig. 7, electric conducting material 109b (i.e. this field plate) is positioned on top medium layer 108, and there is the part overlapping on termination groove 102b, this field plate is also annular shape, on termination groove 102b, along horizontal direction, to external expansion, extend, extend outwardly into the outside of termination groove 102b, for example can extend to the termination environment in termination groove 102b outside, the outer ledge that can configure in addition this field plate 109b self approaches the periphery edge 150 of chip or substrate or epitaxial loayer 101b, the inside edge that this field plate 109b is relative be positioned at termination groove 102b close active area (or towards chip center) madial wall directly near, this field plate can be used for alleviating the electric field crowding of termination environment.
In some optional but nonessential embodiment, termination groove 102b can not be also closed annular, but is arranged side by side with active groove 102a, is positioned at the both sides of active groove 102a.In some optional embodiment, only when additionally adding field plate 109b on substrate, just need the extra termination groove 102b that sets closed annular, the words that for example this field plate 109b on epitaxial loayer has not existed, definition termination groove 102b, for annular is not just necessary condition, needs only and offer through hole 107b in termination groove 102b or active groove 102a.If attempt to cancel termination groove 102b, only retain active groove 102a, only need in the control gate 107a on active groove 102a top, offer through hole, the content disclosing above according to the present invention, be readily appreciated that, in the control gate 107a that is desirably in active groove 102a top, offer through hole, its processing step is just the same with the step of offering through hole in the control gate 107a on termination groove 102b top, so it will not go into details, when offering through hole 107b in active groove 102a, only need the shield grid 104a of active groove 102a bottom to export to and metal layer at top 113 short circuits as source electrode.Certainly, at other embodiment, if need to this field plate 109b, can prepare the termination groove 102b of active groove 102a periphery.
According to the present invention's spirit, can realize and reduce light shield level, and simplified processing process, both reduced difficulty of processing and reduced processing cost, and can realize high-breakdown-voltage, low on-resistance and improve rate of finished products, device can have the stronger market competitiveness.The present invention has also abandoned the mode of the expensive process such as traditional employing HDP and CMP, and the hole of offering on shield grid does not need expensive chemical gaseous phase depositing process to realize metallization, has effectively reduced the reliability that technology difficulty while have strengthened long term device greatly.
Above, by explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, foregoing invention has proposed existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (27)
1. with a preparation method for the groove-type power device of splitting bar, it is characterized in that, comprise the following steps:
The top of steps A, the epitaxial loayer on base substrate etches a termination groove and a plurality of active groove;
Step B, generation one first insulating barrier, be covered in termination groove and active groove sidewall and bottom separately, is covered on the end face of epitaxial loayer simultaneously;
Step C, at termination groove, active groove under-filled electric conducting material separately, as shield grid;
Step D, etching remove termination groove, active groove the first insulating barrier on upper portion side wall place and epitaxial loayer end face separately, and above each shield grid, prepare a separator;
Step e, generate the second insulating barrier, cover termination groove and active groove separately on the exposed sidewall in top, be covered on the end face of epitaxial loayer simultaneously;
Step F, at termination groove, active groove top filled conductive material separately, as control gate;
Step G, in termination groove etching control gate and separator, define one or more through holes that expose shield grid;
The top medium layer of the second insulating barrier on epitaxial loayer end face has been merged in step H, formation one, is covered on epitaxial loayer end face and each control gate, synchronously forms the sidewall that a sidepiece dielectric layer is attached to through hole;
Step I, filled conductive material are to through hole;
Step J, formation one insulating passivation layer are covered on top medium layer and through hole;
Step K, etching insulating passivation layer at least form first set contact hole wherein, fill subsequently metal plug to first set contact hole and on top medium layer, depositing a metal layer at top, the metal plug arranging in first set contact hole is electrically connected electric conducting material and the metal layer at top in through hole.
2. the method for claim 1, is characterized in that, in step C, comprises the following steps:
Deposits conductive material, covers the top of the first insulating barrier on epitaxial loayer end face for the first time, and is filled in termination groove and active groove;
Return and carve electric conducting material, retain termination groove, the active groove electric conducting material of bottom separately, as shield grid.
3. the method for claim 1, is characterized in that, in step D, comprises the following steps:
Deposition insulant, is covered in the top of the first insulating barrier on epitaxial loayer end face, and is filled in termination groove and active groove top separately;
Return to carve and to remove insulant, and return to carve to remove and be covered in termination groove, active groove the first insulating barrier on upper portion side wall place and epitaxial loayer end face separately, a nationality that retains each shield grid top is returned the separator of carving and staying by insulant.
4. the method for claim 1, is characterized in that, in step F, comprises the following steps:
Deposits conductive material, covers the top of the second insulating barrier on epitaxial loayer end face for the second time, and is filled in the top of termination groove and active groove;
Return and carve electric conducting material, retain termination groove, the active groove electric conducting material on top separately, as control gate.
5. the method for claim 1, is characterized in that, in step G, comprises the following steps:
On the second insulating barrier top on epitaxial loayer end face and the top of each control gate, form a photoresist layer;
Nationality is controlled the opening of gate region for inner minute in photoresist layer for exposing termination groove, control gate and the separator in etching termination groove, forms one or more through holes that expose shield grid downwards.
6. the method for claim 1, is characterized in that, in step H, comprises the following steps:
Above the second insulating barrier on epitaxial loayer end face, prepare the insulating medium layer with the identical material of the second insulating barrier, original the second insulating barrier on this SI semi-insulation dielectric layer and epitaxial loayer end face merges and forms in a top medium layer, and this top medium layer is covered on epitaxial loayer end face and each control gate;
The synchronous another part insulating medium layer forming is also attached on the sidewall that through hole is exposed to form sidepiece dielectric layer.
7. method as claimed in claim 6, is characterized in that, after step H, comprises the following steps:
Directly utilize top medium layer as etch mask, dry etching removes in the step that generates top medium layer and sidepiece dielectric layer and is synchronously covered in the insulating medium layer at the exposed region place of the shield grid below through hole.
8. the method for claim 1, is characterized in that, in step I, comprises the following steps:
Deposits conductive material, covers the top of the top medium layer on epitaxial loayer end face and is filled in through hole for the third time;
Return and carve electric conducting material, retain the electric conducting material in through hole.
9. the method for claim 1, is characterized in that, in step F, G, H, I after any one step, but before step J, further comprising the steps of:
At least the top of the epitaxial loayer inside termination groove is implanted alloy and is formed a body layer, is centered around each active groove top around; And
Near one source pole layer implanting alloy formation epitaxial loayer end face at the top of body layer.
10. method as claimed in claim 9, it is characterized in that, when step K etching insulating passivation layer, also comprise downwards etching insulating passivation layer, top medium layer, source layer and body layer successively, form and extend in body layer and second overlapping contact hole between adjacent active groove or between active groove and termination groove; And
Also in the second cover contact hole, fill metal plug subsequently, the metal plug in formed metal layer at top and the second cover contact hole forms in electrical contact.
11. the method for claim 1, it is characterized in that, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at electric conducting material in described through hole, thereby the metal plug of filling in first set contact hole is electrically connected the electric conducting material in through hole.
12. methods as claimed in claim 4, is characterized in that, in step I, comprise the following steps:
When returning the electric conducting material depositing for the third time quarter, also retain a part of electric conducting material overlap on termination groove as a field plate, wherein, this part electric conducting material termination groove outside expansion in the horizontal direction that forms this field plate is extended, until extend near epitaxial loayer periphery edge.
13. methods as claimed in claim 12, it is characterized in that, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at this field plate, thereby the metal plug of filling in first set contact hole is electrically connected to the electric conducting material in the through hole of field plate below via field plate.
14. 1 kinds of groove-type power devices with splitting bar, is characterized in that, comprising:
One base substrate and be positioned at the epitaxial loayer on base substrate;
Be formed on a termination groove and a plurality of active groove in epitaxial loayer;
Be filled in respectively active groove, termination groove separately bottom shield grid and be filled in their control gates on top separately, between a control gate of each shield grid and its top, be provided with a separator insulation;
At least be formed on termination groove inner side epitaxial loayer top and be centered around each active groove top body layer around, and the one source pole layer that is formed on body layer top;
Run through successively downwards on one or more sidewalls of control gate, separator in termination groove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole;
A top medium layer that is positioned on epitaxial loayer end face and each control gate is covered and be positioned at the insulating passivation layer on top medium layer;
Downwards run through successively insulating passivation layer, top medium layer and source layer and extend to body layer in and second overlapping contact hole between adjacent active groove or between active groove and termination groove, and running through insulating passivation layer downwards and aim at the first set contact hole of the interior electric conducting material of described through hole;
Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer;
The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.
15. 1 kinds of groove-type power devices with splitting bar, is characterized in that, comprising:
One base substrate and be positioned at the epitaxial loayer on base substrate;
Be formed on a termination groove and a plurality of active groove in epitaxial loayer;
Be filled in respectively active groove, termination groove separately bottom shield grid and be filled in their control gates on top separately, between a control gate nationality of each shield grid and its top, be provided with a separator;
At least be formed on termination groove inner side epitaxial loayer top and be centered around each active groove top body layer around, and the one source pole layer that is formed on body layer top;
Run through successively downwards on one or more sidewalls of control gate, separator in termination groove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole;
A top medium layer that is positioned on epitaxial loayer end face and each control gate is covered;
Be positioned on top medium layer and overlap on the field plate on termination groove, field plate outwards extends to the outside of termination groove in the horizontal direction;
When being arranged on top medium layer, also envelope the insulating passivation layer of described field plate;
Downwards run through successively insulating passivation layer, top medium layer and source layer and extend to body layer in and second overlapping contact hole between adjacent active groove or between active groove and termination groove, and running through insulating passivation layer downwards and aim at the first set contact hole of described field plate;
Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer;
The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.
16. 1 kinds of preparation methods with the groove-type power device of splitting bar, is characterized in that, comprise the following steps:
The top of steps A, the epitaxial loayer on base substrate etches a plurality of grooves;
Step B, generation one first insulating barrier, be covered in each trenched side-wall and bottom, and be covered on the end face of epitaxial loayer;
Step C, at the under-filled electric conducting material of groove, as shield grid;
Step D, etching remove the first insulating barrier on groove upper portion side wall place and epitaxial loayer end face, and above each shield grid, prepare a separator;
Step e, generate the second insulating barrier, on the exposed sidewall in covering groove top, be covered on the end face of epitaxial loayer simultaneously;
Step F, at groove top filled conductive material, as control gate;
Step G, in part groove etching control gate and separator, define one or more through holes that expose shield grid;
The top medium layer of the second insulating barrier on epitaxial loayer end face has been merged in step H, formation one, is covered on epitaxial loayer end face and each control gate, synchronously forms the sidewall that a sidepiece dielectric layer is attached to through hole;
Step I, filled conductive material are to through hole;
Step J, formation one insulating passivation layer are covered on top medium layer and through hole;
Step K, etching insulating passivation layer at least form first set contact hole wherein, fill subsequently metal plug to first set contact hole and on top medium layer, depositing a metal layer at top, the metal plug arranging in first set contact hole is electrically connected electric conducting material and the metal layer at top in through hole.
17. methods as claimed in claim 16, is characterized in that, in step C, comprise the following steps:
Deposits conductive material, covers the top of the first insulating barrier on epitaxial loayer end face, and is filled in groove for the first time;
Return and carve electric conducting material, retain the electric conducting material of groove bottom, as shield grid.
18. methods as claimed in claim 16, is characterized in that, in step D, comprise the following steps:
Deposition insulant, is covered in the top of the first insulating barrier on epitaxial loayer end face, and is filled in the top in groove;
Return and remove insulant quarter, and remove the first insulating barrier being covered on groove upper portion side wall place and epitaxial loayer end face time quarter, a nationality that retains each shield grid top is returned the separator of carving and staying by insulant.
19. methods as claimed in claim 16, is characterized in that, in step F, comprise the following steps:
Deposits conductive material, covers the top of the second insulating barrier on epitaxial loayer end face for the second time, and is filled in the top of groove;
Return and carve electric conducting material, retain the electric conducting material on groove top, as control gate.
20. methods as claimed in claim 16, is characterized in that, in step G, comprise the following steps:
On the second insulating barrier top on epitaxial loayer end face and the top of each control gate, form a photoresist layer;
Nationality is for exposing the opening in a part of control gate region in pregroove in photoresist layer, and control gate and the separator in this pregroove of etching, forms one or more through holes that expose shield grid downwards.
21. methods as claimed in claim 16, is characterized in that, in step H, comprise the following steps:
Above the second insulating barrier on epitaxial loayer end face, prepare the insulating medium layer with the identical material of the second insulating barrier, original the second insulating barrier on this SI semi-insulation dielectric layer and epitaxial loayer end face merges and forms in a top medium layer, and this top medium layer is covered on epitaxial loayer end face and each control gate;
The synchronous another part insulating medium layer forming is also attached on the sidewall that through hole is exposed to form sidepiece dielectric layer.
22. methods as claimed in claim 21, is characterized in that, after step H, comprise the following steps:
Directly utilize top medium layer as etch mask, dry etching removes in the step that generates top medium layer and sidepiece dielectric layer and is synchronously covered in the insulating medium layer at the exposed region place of the shield grid below through hole.
23. methods as claimed in claim 16, is characterized in that, in step I, comprise the following steps:
Deposits conductive material, covers the top of the top medium layer on epitaxial loayer end face and is filled in through hole for the third time;
Return and carve electric conducting material, retain the electric conducting material in through hole.
24. methods as claimed in claim 16, is characterized in that, in step F, G, H, I after any one step, but before step J, further comprising the steps of:
At least the top of the epitaxial loayer inside outermost groove is implanted alloy and is formed a body layer, is centered around each groove top around; And
Near one source pole layer implanting alloy formation epitaxial loayer end face at the top of body layer.
25. methods as claimed in claim 24, it is characterized in that, when step K etching insulating passivation layer, also comprise downwards etching insulating passivation layer, top medium layer, source layer and body layer successively, form the second cover contact hole extending in body layer and between adjacent trenches; And
Also in the second cover contact hole, fill metal plug subsequently, the metal plug in formed metal layer at top and the second cover contact hole forms in electrical contact.
26. methods as claimed in claim 16, it is characterized in that, in the step of step K etching insulation passivation, form the first set contact hole that runs through insulating passivation layer downwards and aim at electric conducting material in described through hole, thereby the metal plug of filling in first set contact hole is electrically connected the electric conducting material in through hole.
27. 1 kinds of groove-type power devices with splitting bar, is characterized in that, comprising:
One base substrate and be positioned at the epitaxial loayer on base substrate;
Be formed on a plurality of grooves in epitaxial loayer;
Be filled in the shield grid and the control gate that is filled in groove top of groove bottom, between each shield grid and a control gate of its top, be provided with a separator insulation;
At least be formed on outermost groove inner side epitaxial loayer top and be centered around each groove top body layer around, and the one source pole layer that is formed on body layer top;
Run through successively downwards on one or more sidewalls of control gate, separator in a part of pregroove and be attached with the through hole of sidepiece dielectric layer, and be filled in the electric conducting material in through hole;
A top medium layer that is positioned on epitaxial loayer end face and each control gate is covered and be positioned at the insulating passivation layer on top medium layer;
Run through successively insulating passivation layer, top medium layer and source layer downwards and extend to the second cover contact hole in body layer and between adjacent trenches, and run through the first set contact hole of electric conducting material in insulating passivation layer aligned through holes downwards;
Be filled in the metal plug in first set, the second cover contact hole and be arranged at the metal layer at top on insulating passivation layer;
The shield grid of interconnection takes this to be electrically connected at described metal layer at top by the conductive path of the metal plug in the electric conducting material in through hole and first set contact hole to each other.
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