CN103855017B - The method of forming a trench type double polysilicon gate structure having two lateral mos isolated - Google Patents

The method of forming a trench type double polysilicon gate structure having two lateral mos isolated Download PDF

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CN103855017B
CN103855017B CN201210509270.6A CN201210509270A CN103855017B CN 103855017 B CN103855017 B CN 103855017B CN 201210509270 A CN201210509270 A CN 201210509270A CN 103855017 B CN103855017 B CN 103855017B
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layer
polysilicon
step
etching
nitride film
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CN103855017A (en
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李陆萍
张博
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上海华虹宏力半导体制造有限公司
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Abstract

本发明公开了一种形成沟槽型双层栅MOS结构两层多晶硅横向隔离的方法,包括:1)生长第一氮化膜;2)沟槽刻蚀;3)生长介质层;4)生长第一层多晶硅;5)第一层多晶硅第一步反刻蚀;6)第一层多晶硅光刻及第二步反刻蚀,并去除第一层多晶硅上方的沟槽侧壁介质层;7)淀积第二氮化膜,刻蚀,露出第一层多晶硅;8)生长热氧化层;9)去除沟槽侧壁的第二氮化膜和硅基板表面的第一、二氮化膜;10)栅极氧化层生长;11)淀积第二层多晶硅,刻蚀;12)多晶硅光刻;13)形成基极和源极;14)形成隔离介质层;15)形成接触孔、金属、钝化层。 The present invention discloses a method of forming a trench MOS gate type double layer polysilicon structure having two lateral isolation, comprising: 1) growing a first nitride film; 2) a trench etch; 3) growth medium layer; 4) Growth a first polysilicon layer; 5) a first layer of the first step anti-etching the polysilicon; 6) a first polysilicon layer and the trench sidewalls photolithography second step anti-etching the dielectric layer, and removing the polysilicon over the first layer; 7 ) depositing a second nitride film is etched to expose the first polysilicon layer; 8) growing a thermal oxide layer; 9) the first and second nitride film of the second nitride film and the silicon substrate surface is removed to the trench sidewalls ; 10) growth of gate oxide layer; 11) depositing a second polysilicon layer, etching; 12) of polysilicon lithography; 13) forming a base and a source; 14) forming an isolation dielectric layer; 15) forming a contact hole, a metal , a passivation layer. 本发明的工作区域得到扩张,且降低工艺成本及控制难度,提高器件工作性能。 The present invention obtained working area expansion, and difficult to control and reduce process costs, improve the performance of the device.

Description

形成沟槽型双层栅MOS结构两层多晶硅横向隔离的方法 The method of forming a trench type double polysilicon gate MOS structure having two lateral isolation of

技术领域 FIELD

[0001]本发明涉及一种沟槽型金属氧化物半导体场效应晶体管(Trench M0SFET)中的多晶硅横向隔离的方法,特别是涉及一种形成沟槽型双层栅MOS结构两层多晶硅横向隔离的方法。 [0001] The present invention relates to a trench metal oxide semiconductor field effect transistor (Trench M0SFET) lateral isolation of the polysilicon, in particular to a trench is formed a double polysilicon gate MOS structure having two lateral isolation of method.

背景技术 Background technique

[0002]在功率器件中,沟槽型双层栅功率MOS器件具有击穿电压高、导通电阻低、转换效率高、开关速度快的特性。 [0002] In the power device, a double gate trench power MOS device having high breakdown voltage, low on-resistance, high conversion efficiency, fast switching speed characteristics. 通常,源极多晶硅(第一层多晶硅)电极作为屏蔽电极与源极短接或者通单独引出,第二层多晶硅电极作为栅极。 Typically, source poly (first polysilicon layer) electrode as a shield electrode is shorted to the source or by a separate lead, the second polysilicon layer as a gate electrode. 因而在一个沟槽内,会存在源极多晶硅引出端区域与栅极多晶硅横向接触的区域。 Accordingly, in one trench, there will be a source region and a polysilicon gate polysilicon leading ends of the lateral contact areas. 这两层多晶硅电极之间的氧化层厚度需要严格控制,否则会形成漏电或较低的击穿电压。 The thickness of the oxide layer between the two layers of polysilicon electrodes must be strictly controlled, otherwise it will form a drain breakdown voltage or lower.

[0003]目前的HDP生长的双层栅之间介质层的工艺方法,其流程如下: [0003] process for a double dielectric layer between the gate current HDP growth process is as follows:

[0004] I)沟槽腐蚀; [0004] I) a trench etching;

[0005] 2)介质层淀积; [0005] 2) dielectric layer is deposited;

[0006] 3)源极多晶硅(第一层多晶硅)栅淀积; [0006] 3) a polysilicon source (first polysilicon layer) is deposited a gate;

[0007] 4)源极多晶硅(第一层多晶硅)栅第一步反刻蚀; [0007] 4) a polysilicon source (first polysilicon layer) gate the first step anti-etching;

[0008] 5)源极多晶硅(第一层多晶硅)栅光刻、源极多晶硅(第一层多晶硅)栅第二步反刻蚀; [0008] 5) a source polysilicon (first polysilicon layer) gate photolithography, the polysilicon source electrode (first polysilicon layer) gate anti-etching the second step;

[0009] 6)高密度等离子体(HDP)氧化膜淀积; [0009] 6) a high-density plasma (HDP) oxide film deposition;

[0010] 7)HDP CMP(化学机械研磨)至剩余3000埃; [0010] 7) HDP CMP (chemical mechanical polishing) to the rest of 3000 Angstroms;

[0011] 8)P-Cover(P0LY⑶VER)光刻后湿法腐蚀形成双层多晶硅横向隔离区域,同时在cel I (M0SFET的原胞)区沟槽内的第一层多晶硅上剩余2500埃HDP氧化膜; [0011] 8) P-Cover rear (P0LY⑶VER) photolithography wet etching to form a double polysilicon lateral isolation region, while in the cel I (M0SFET original cell) a first region of the trench polysilicon layer on the remaining HDP oxide 2500 Å membrane;

[0012] 9)栅氧化层生长、第二层多晶硅淀积、第二层多晶硅反刻蚀; [0012] 9) a gate oxide layer is grown, a second polysilicon layer is deposited, a second polysilicon layer anti-etching;

[0013] 10)金属下介质层生长; [0013] 10) the lower metal layer growth medium;

[0014] 11)接触孔介质层刻蚀、接触孔硅刻蚀; [0014] 11) dielectric layer contact hole etching, silicon etching contact holes;

[0015] 12)源极金属生长与刻蚀。 [0015] 12) growth and etching the source metal.

[0016] 其中,现有工艺中的第一层多晶硅两步反刻蚀之后的cell(M0SFET的原胞)区断面示意图,如图1所示;第一层多晶硅两步反刻蚀之后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图,如图2所示;HDP氧化膜生长后cell区断面示意图,如图3所示;HDP氧化膜生长后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图,如图4所示;HDP氧化膜湿法刻蚀后cell区断面示意图,如图5所示;HDP氧化膜湿法刻蚀后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图,如图6所示。 [0016] wherein, after the polysilicon Cell-step prior art anti-etch the first layer (M0SFET original cell) schematic sectional area, as shown in FIG. 1; a first polysilicon layer after a first-step etching trans a polysilicon layer lead schematic sectional area along the groove direction and the cell region, as shown in FIG. 2; the cell area schematic sectional HDP oxide film growth, as shown in FIG. 3; the first layer was grown HDP oxide film and a polysilicon region extraction cell schematic cross sectional area along the groove direction, shown in Figure 4; cell region HDP oxide film after wet etching cross-sectional schematic view, FIG. 5; first HDP oxide layer after wet etching the polysilicon film and the lead-out area cell cross-sectional area along the groove direction is a schematic diagram, as shown in FIG.

[0017]上述工艺方法,利用源极多晶硅(第一层多晶硅)反刻之后生长的HDP(高密度等离子体)氧化膜,加一层光刻版在HDP湿法反刻时横向覆盖住部分氧化膜使其不被刻蚀,最终在源极多晶硅引出端边上留下约20000埃的HDP氧化膜作为两层多晶硅之间的横向隔离介质层。 [0017] The above process, using a source poly (first polysilicon layer) HDP (High Density Plasma) oxide film growth after the anti-engraved, add a layer of the lithographic printing plate covering the lateral portions of the wet HDP oxide moment when trans film so as not to be etched, eventually leading end edge of the source polysilicon leaving HDP oxide film of about 20,000 angstroms as lateral isolation dielectric layer between the two layers of polysilicon. 但该方法存在如下几个问题: But there is some problem with this approach:

[0018]首先,完全依赖于HDP工艺,而在现在改良的热氧方法生长的双层栅之间介质层的工艺中无法实现; [0018] First, completely dependent on the HDP process, the process can not be achieved in double the gate dielectric layer between the oxygen present improved thermal growth of the method;

[0019]其次,已有双层栅功率MOS器件存在因为HDP氧化膜刻蚀速率的起伏波动以及湿法刻蚀各向同性的特性,使得横向隔离区域长度需要很大(湿法纵向刻蚀量需要约12000埃,故横向一般留有20000埃左右的距离),才可以保证两层多晶硅之间横向不会穿通,这样大大减少了工作区域面积,影响器件参数。 [0019] Secondly, existing double gate MOS power device because the presence of fluctuations HDP oxide film and the isotropic etch rate characteristics of the wet etching, so that the lateral isolation region requires a large length (longitudinal wet etch amount requires about 12,000 angstroms, it is generally left lateral distance of around 20,000 angstroms), can not ensure lateral through between the two layers of polysilicon, this greatly reduces the working area of ​​the impact device parameters.

发明内容 SUMMARY

[0020]本发明要解决的技术问题是提供一种形成沟槽型双层栅MOS结构两层多晶硅横向隔离的方法。 [0020] The present invention is to solve the technical problem is to provide a method for trench-type double gate MOS structure having two lateral polysilicon spacer is formed. 利用该方法,可解决热氧介质层双层栅工艺中两层多晶硅的横向隔离问题。 With this method, the dielectric layer can solve the thermal oxidation process of a double gate polysilicon layers laterally isolate the problem.

[0021]为解决上述技术问题,本发明的形成沟槽型双层栅MOS结构两层多晶硅横向隔离的方法,包括步骤: [0021] In order to solve the above problems, the present invention is formed trench gate MOS structure having two double polysilicon lateral isolation method, comprising the steps of:

[0022] I)在硅基板上,生长作为保护层的第一氮化膜; [0022] I) on the silicon substrate, growing a first nitride film as the protective layer;

[0023] 2)在娃基板上,进行Trench(沟槽)刻蚀; [0023] 2) on the substrate baby, for Trench (trench) etching;

[0024] 3)沟槽内生长介质层; [0024] 3) the growth of the dielectric layer within the trench;

[0025] 4)在介质层上,生长第一层多晶硅(源极多晶硅); [0025] 4) on the dielectric layer, growing a first layer of polycrystalline silicon (polysilicon source);

[0026] 5)对第一层多晶硅进行第一步反刻蚀; [0026] 5) a first layer of polysilicon of the first step anti-etching;

[0027] 6)对第一层多晶硅进行光刻及第二步反刻蚀,并去除第一层多晶硅上方的沟槽侧壁介质层; [0027] 6) a first layer of polysilicon and a second step anti-etching photolithography, and removing the first layer of polysilicon trench sidewall over the dielectric layer;

[0028] 7)在沟槽的底部和侧壁以及硅基板表面淀积第二氮化膜后,刻蚀去除沟槽底部的第二氮化膜,露出第一层多晶硅; [0028] 7) in the side wall and the bottom surface of the trench of the silicon substrate and depositing a second nitride film, the nitride film is removed by etching the second bottom of the trench, the exposed first polysilicon layer;

[0029] 8)在第一层多晶硅上,生长热氧化层; [0029] 8) on a first polysilicon layer, growing a thermal oxide layer;

[0030] 9)去除沟槽侧壁的第二氮化膜和硅基板表面的第一、二氮化膜; [0030] 9) the first and second nitride film of the second nitride film and the silicon substrate surface is removed to the trench sidewalls;

[0031] 10)栅极氧化层生长; [0031] 10) growth of gate oxide layer;

[0032] 11)在沟槽内淀积第二层多晶硅(栅极多晶硅),并刻蚀至硅表面; [0032] 11) depositing a second polysilicon layer (gate polysilicon) within the trench and etched to the silicon surface;

[0033] 12)多晶硅(Poly Cover层)光刻,定义靠近热氧化层端的第二层多晶硅处的待填充隔离介质层区域,并将该区域内的第二层多晶硅全部刻蚀掉,形成待填充隔离介质层区; [0033] 12) of polysilicon (Poly Cover layer) lithography, isolation dielectric layer regions to be filled at the second polysilicon layer is defined near the end of the thermally oxidized layer, the second polysilicon layer and etching away all of the region, to be formed filling isolation dielectric layer region;

[0034] 13)形成基极(BODY)和源极(Source); [0034] 13) forming a base (the BODY) and the source (the Source);

[0035] 14)在涂硼磷硅玻璃的同时,在待填充隔离介质层区内,硼磷硅玻璃也会自然流入,从而形成横向隔离介质层; [0035] 14) while borophosphosilicate glass coating in the area to be filled isolation dielectric layer, borophosphosilicate glass will naturally flow into, thereby forming a lateral isolation dielectric layer;

[0036] 15)形成接触孔、金属、钝化层。 [0036] 15) forming a contact hole, a metal, a passivation layer.

[0037]所述步骤I)中,生长第一氮化膜的方法包括:低压化学气相沉积或等离子体增强式化学气相沉积;第一氮化膜的材质包括:氮化硅;第一氮化膜的厚度为500〜3000埃。 [0037] The step I), the method of growing the first nitride film comprising: a low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; first nitride film material comprising: silicon; a first nitride the film thickness was 500~3000 Å.

[0038]所述步骤3)中,介质层为氧化膜,包括:氧化娃,厚度为500〜3000埃;介质层的生长方式包括:热氧或低压化学气相沉积方式。 In [0038] step 3), the dielectric layer is an oxide film, comprising: a baby oxide, having a thickness of 500~3000 Å; growth pattern the dielectric layer comprising: a low pressure oxygen or thermal chemical vapor deposition method.

[0039]所述步骤4)中,生长第一层多晶硅的方法包括:低压化学气相沉积;第一层多晶硅的厚度为足以填满沟槽内部。 [0039] step 4), the method of growing a first polysilicon layer comprising: a low pressure chemical vapor deposition; thickness of the first polysilicon layer sufficient to fill the inside of the trench.

[0040] 所述步骤5)中,第一步反刻蚀时,直至刻蚀至硅表面。 [0040] step 5), the first step when the anti-etching until the etched to the silicon surface.

[0041]所述步骤6)的对第一层多晶硅进行光刻及第二步反刻蚀中,对第一层多晶硅进行光刻,保护住需要接出源极多晶硅的位置,剩余的第一层多晶硅位置进行第二步多晶硅反刻蚀,直至刻蚀至硅表面以下所需深度。 [0041] step 6) a first layer of a first and a second step anti-lithographic etching polysilicon, the polysilicon layer of the first photolithography, protect the lives of the need to take the position of the source polysilicon, remaining Step polysilicon layer polysilicon anti-etching position, until the silicon is etched to a desired depth below the surface.

[0042]所述步骤7)中,第二氮化膜淀积的方法包括:低压化学气相沉积或等离子体增强式化学气相沉积;第二氮化膜的材质包括:氮化硅;第二氮化膜的厚度为500〜3000埃;刻蚀的方法为干法刻蚀。 In [0042] step 7), the second nitride film deposition method comprising: a low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; second nitride film material comprising: a silicon nitride; a second nitrogen the thickness of the film is 500~3000 Å; etching method is dry etching.

[0043]所述步骤8)中,生长热氧化层的方法为通过热氧方式生长;其中,热氧方式中的工艺温度为高于950°C;热氧化层的厚度为500〜3000埃。 In [0043] step 8), the method of growing a thermal oxide layer is grown by thermal oxidation mode; wherein the thermal process temperature is higher than the oxygen mode is 950 ° C; thickness of the thermal oxide layer is 500~3000 Å.

[0044]所述步骤9)中,去除的方式包括:湿法刻蚀。 In [0044] step 9), removal methods include: wet etching.

[0045]所述步骤12)中,待填充隔离介质层区域的宽度为1000〜10000埃。 In [0045] The step 12), the width of the area to be filled isolation dielectric layer is 1000~10000 Å.

[0046] 所述步骤14)中,硼磷硅玻璃的厚度为5000〜10000埃。 In [0046] The step 14), the thickness of borophosphosilicate glass 5000~10000 Å. 本步骤中,填入的硼磷硅玻璃不仅要将待填充区域填满,还要在表面上存在一定厚度用于作为CT的隔离介质层。 In this step, borophosphosilicate glass filled not only to fill the area to be filled, but also the presence of a certain thickness on the surface of a CT isolation dielectric layer.

[0047]本发明针对目前改良的热氧方法生长的双层栅之间介质层的工艺提出一种方法,在栅极多晶硅电极刻蚀至硅表面之后再多加一层光刻版,定义出源极多晶硅引出端区域边一块特定长度区域,利用干法完全刻蚀掉该区域栅极多晶硅。 [0047] The present invention provides a method for the bilayer process of the gate dielectric layer between the oxygen present improved thermal growth method, etching of the gate polysilicon electrode layer of the lithographic printing plate and then more after the silicon surface to define the source a polysilicon electrode lead-out side end region specific length region, by dry etched away region of the gate polysilicon. 后续该区域在接触孔刻蚀之前由ILD层硼磷硅玻璃填满。 Follow-up in the region filled with the BPSG ILD layer prior to etching the contact hole. 利用硼磷硅玻璃作为隔离介质,应用于热氧介质层双层栅工艺中实现了两层多晶硅的横向隔离。 Use of borophosphosilicate glass as the separation medium, heat is applied to the gate oxide bilayer dielectric layer in the process to achieve the lateral isolation layers of polysilicon.

[0048]由于本发明利用硼磷硅玻璃作为隔离介质,应用于热氧介质层双层栅工艺中实现了两层多晶硅的横向隔离,较之HDP氧化膜介质层双层栅工艺,不仅省去HDP氧化膜淀积、化学机械研磨等工艺,工作区域也得到很大扩张,且在降低工艺成本及控制难度的基础上,还有效提尚器件工作性能。 [0048] Since the present invention utilizes a borophosphosilicate glass as the separation medium, heat is applied to the gate oxide bilayer dielectric layer in the process to achieve the lateral isolation layers of polycrystalline silicon oxide film HDP dielectric layer than the double gate process, not only to save HDP oxide film deposition, chemical mechanical polishing process, the operating region has also been greatly expanded, and on the basis of cost and process control to reduce the difficulty, yet also effectively improve device performance.

附图说明 BRIEF DESCRIPTION

[0049]下面结合附图与具体实施方式对本发明作进一步详细的说明: [0049] The accompanying drawings in conjunction with the following specific embodiments will be further detailed description of the present invention:

[0050]图1是现有工艺中的第一层多晶硅两步反刻蚀之后的ce 11 (MOSFET的原胞)区断面示意图; [0050] FIG. 1 is a sectional view of a conventional process in the first layer ce 11 (MOSFET original cell) regions after a two-step anti polysilicon etch;

[0051]图2是现有工艺中的第一层多晶硅两步反刻蚀之后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图; [0051] FIG 2 is a first layer of a first prior art polysilicon layer and the lead-out area in the cell area schematic cross-sectional direction of the groove after the two-step anti-etching the polysilicon;

[0052]图3是现有工艺中的HDP氧化膜生长后cell区断面示意图; [0052] FIG. 3 is a sectional schematic view of the cell region HDP oxide film grown in the conventional process;

[0053]图4是现有工艺中的HDP氧化膜生长后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图; [0053] FIG. 4 is a schematic view of the HDP oxide film is grown in the conventional process first polysilicon layer and the lead-out area of ​​a cross-sectional area along the groove direction of the cell;

[0054]图5是现有工艺中的HDP氧化膜湿法刻蚀后cell区断面示意图; [0054] FIG. 5 is a sectional schematic view of the cell region HDP oxide film conventional wet etching process;

[0055]图6是现有工艺中的HDP氧化膜湿法刻蚀后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图; [0055] FIG. 6 is a first polysilicon layer and the lead-out area in the cell area schematic cross-sectional direction after the trench oxide film HDP conventional wet etching process;

[0056]图7是本发明的沟槽刻蚀前生长一层氮化层作为阻挡层的cell区断面图; [0056] FIG. 7 is a front trench etch the present invention is growing a nitride layer as the cell sectional view of the barrier layer region;

[0057]图8是本发明的第一层多晶硅两步反刻蚀及去除侧壁氧化层后的cell区断面图; [0057] FIG. 8 is a sectional view of a two-step first layer polysilicon cell region after the back etching and removing sidewall oxide layer of the present invention;

[0058]图9是本发明的第一层多晶硅第一步反刻蚀及去除侧壁氧化层后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图; [0058] FIG. 9 is a schematic diagram of the present invention, the first step of the first polysilicon layer was removed and the anti-etching the first sidewall oxide layer polysilicon cell lead-out area and the cross-sectional area along the groove direction;

[0059]图10是本发明的生长一层氮化膜后的cell区断面图; [0059] FIG. 10 is a sectional view of the cell growth zone after the nitride film layer of the present invention;

[0060]图11是本发明的刻蚀形成侧壁氮化膜保护层的cell区断面图; [0060] FIG. 11 is a sectional view of the present invention cell area is etched sidewall nitride film is formed a protective layer;

[0061]图12是本发明的在第一层多晶硅上生长热氧介质层后的cell区断面图; [0061] FIG. 12 is a sectional view of the cell region growing a thermal oxide on the polysilicon layer of the first dielectric layer of the present invention;

[0062]图13是本发明的去除沟槽侧壁及硅基板表面的氮化膜后的cell区断面图。 [0062] FIG. 13 is a sectional view of the cell region after removing the nitride film sidewalls and the trench of the silicon substrate surface according to the present invention.

[0063]图14是本发明的热氧化层及栅极氧化层生长之后的cell区断面示意图; [0063] FIG. 14 is a sectional schematic view of a thermal oxide layer and the gate oxide layer grown after the cell area of ​​the present invention;

[0064]图15是本发明的热氧化层及栅极氧化层生长之后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图; [0064] FIG. 15 is a schematic diagram after the thermal oxide layer and the gate oxide layer grown according to the present invention a first cross-sectional area and the lead-out layer polysilicon cell region along the groove direction;

[0065]图16是本发明的第二次多晶硅生长后的cell区断面示意图; [0065] FIG. 16 is a sectional schematic view of the second cell after growth of the polysilicon region of the invention;

[0066]图17是本发明的第二次多晶硅生长后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图; [0066] FIG. 17 is a schematic diagram of the present invention, after the second polysilicon layer is first grown and a polysilicon lead-out area along the groove direction of the cell cross-sectional area;

[0067]图18是本发明的Poly Cover层光刻定义位于靠近热氧化层端的第二层多晶硅处的待填充隔离介质层区域后,将该区域的栅极多晶硅全部刻蚀的第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图; [0067] FIG. 18 is a Poly Cover layer according to the present invention positioned lithographically-defined isolation dielectric layer after filling the region to be close to the second layer of polycrystalline silicon layer at the end of the thermal oxidation, the entire first layer of gate polysilicon etching polysilicon region lead-out area and the cell area schematic sectional view along the groove direction;

[0068]图19是本发明的填入硼磷硅玻璃后第一层多晶硅引出区域与cell区沿沟槽方向的断面示意图。 [0068] FIG. 19 is a schematic sectional view of the present invention is filled after the first borophosphosilicate glass layer polysilicon cell area and lead-out area along the groove direction.

[0069]图中附图标记说明如下: [0069] The reference numerals in FIG follows:

[0070] I为硅基板,2为沟槽,3为第一氮化膜,4为介质层,5为第一层多晶硅,6为第二氮化膜,7为热氧化层,8为栅极氧化层,9为第二层多晶硅。 [0070] I is a silicon substrate, a trench 2, 3 is a first nitride film, a dielectric layer 4, a first layer of polycrystalline silicon 5, 6 for the second nitride film, a thermal oxide layer 7, a gate 8 gate oxide layer, a second layer 9 of polysilicon.

具体实施方式 Detailed ways

[0071]本发明的形成沟槽型双层栅MOS结构两层多晶硅横向隔离的方法,其步骤如下: [0071] forming a trench of the invention is a double polysilicon gate MOS structure having two lateral isolation method comprises the following steps:

[0072] I)在硅基板I上,通过低压化学气相沉积或等离子体增强式化学气相沉积方法,生长厚度为500〜3000埃的第一氮化膜(如氮化硅)2(如图7所示); [0072] I) on a silicon substrate I, by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition method, growing the first nitride film with a thickness of 500~3000 Å (e.g., silicon nitride) 2 (FIG. 7 shown);

[0073]本步骤中的第一氮化膜2可作为后续工艺中沟槽顶部的保护层; [0073] In this step, the first nitride film 2 as a protective layer on top of the trench in a subsequent process;

[0074] 2)在硅基板I上,进行沟槽2刻蚀; [0074] 2) on a silicon substrate I, 2 for a trench etch;

[0075] 3)在沟槽2的侧壁和底部,通过热氧或低压化学气相沉积方式,生长厚度为500〜3000埃的介质层(如氧化硅)4; [0075] 3) on the sidewalls and bottom of trenches 2 by thermal oxidation or LPCVD embodiment, a thickness of 500~3000 Å grown dielectric layer (e.g., silicon oxide) 4;

[0076] 4)在介质层4上,通过低压化学气相沉积,生长第一层多晶硅5(源极多晶硅),第一层多晶硅5的厚度为足以填满沟槽内部; [0076] 4) on the dielectric layer 4, by low pressure chemical vapor deposition, growth of the first polysilicon layer 5 (poly source), the thickness of the first polysilicon layer 5 is sufficient to fill the inside of the trench;

[0077] 5)对第一层多晶硅5进行第一步反刻蚀,直至刻蚀至硅表面; [0077] 5) the first polysilicon layer 5 is the first step anti-etching until the etched silicon surface to;

[0078] 6)对第一层多晶硅5进行光刻及第二步反刻蚀,并通过湿法刻蚀,去除第一层多晶硅5上方的沟槽侧壁介质层4(如图8-9所示); [0078] 6) of a first polysilicon layer 5 and a second step anti-lithographic etching by wet etching, removing the sidewalls of the trench dielectric layer over the first layer of polysilicon 4 5 (FIG. 8-9 shown);

[0079]其中,对第一层多晶硅5进行光刻,保护住需要接出源极多晶硅的位置,剩余的第一层多晶硅5位置进行第二步多晶硅反刻蚀,直至刻蚀至硅表面以下所需深度(特定深度)。 [0079] wherein the first polysilicon layer 5 photolithography, protect the lives of the need to take the position of the source polysilicon, the remaining first polysilicon layer 5 position of the second step anti-etching the polysilicon until the silicon surface is etched to the following a desired depth (depth specific).

[0080] 7)通过低压化学气相沉积或等离子体增强式化学气相沉积,在沟槽2的底部和侧壁以及硅基板I表面(第一氮化膜3表面)淀积厚度为500〜3000埃的第二氮化膜(如氮化硅)6后(如图10所示),干法刻蚀去除沟槽2底部的第二氮化膜6,露出第一层多晶硅5(如图11所示); [0080] 7) deposition or plasma enhanced chemical vapor deposition by low pressure chemical vapor, and the trench sidewalls and bottom surface of the silicon substrate 2 I (3 surface of the first nitride film) is deposited in a thickness of 500~3000 Å second nitride film of the second nitride film (e.g., silicon nitride) after 6 (FIG. 10), removing the dry etching of the bottom of the trench 6 2 exposed first polysilicon layer 5 (FIG. 11 shown);

[0081 ] 8)在第一层多晶硅5上,通过热氧方式(温度高于950°C),生长厚度为500〜3000埃的热氧化层(如氧化硅)7 (如图12所示); [0081] 8) on a first polysilicon layer 5, by way of thermal oxidation (temperatures above 950 ° C), growth of the thickness of 500~3000 Å thermal oxide layer (e.g., silicon oxide) 7 (12) ;

[0082] 9)湿法刻蚀,去除沟槽侧壁的第二氮化膜6,以及硅基板I表面的第一氮化膜3、和第二氮化膜6,留下沟槽2底部的第一层多晶硅5上存在的热氧化层7(如图13所示); [0082] 9) wet etching, 6, and a silicon substrate I 3, the second nitride film and the first nitride film surface of the second trench sidewall nitride film 6 is removed, leaving the bottom of the trench 2 a first layer of thermal oxide present on the polysilicon layer 57 (FIG. 13);

[0083] 10)按照现有工艺,利用热氧化,生长栅极氧化层8(如图14-15所示); [0083] 10) According to the prior process, by thermal oxidation, a gate oxide layer 8 is grown (FIG. 14-15);

[0084] 11)按照现有工艺(如低压化学气相沉积),在沟槽2内淀积第二层多晶硅(栅极多晶硅)9,并刻蚀至硅表面(如图16-17所示); [0084] 11) in accordance with the conventional process (e.g., low pressure chemical vapor deposition), 2 is deposited within the trench of the second layer of polysilicon (gate polysilicon) 9, and etched to the silicon surface (FIG. 16-17) ;

[0085] 12)多晶硅(Poly Cover层)光刻,定义位于靠近热氧化层端的第二层多晶硅处的待填充隔离介质层区域,并将该区域内的第二层多晶硅全部刻蚀掉,形成待填充隔离介质层区,即定义第一层多晶硅引出端旁的存在于第二层多晶硅处的特定长度区域(如1000〜10000埃),并将该区域内的第二层多晶硅全部刻蚀掉,形成待填充隔离介质层区(如图18所示); Region to be filled isolation dielectric layer [0085] 12) of polysilicon (Poly Cover layer) lithography, is located close to the definition of a polysilicon layer is thermally oxidized at the end of the second layer, the second polysilicon layer and etching away all of the region, is formed isolation dielectric layer regions to be filled, i.e. polysilicon layer defining a first end of the lead is present next to a specific length of the region (e.g. 1000~10000 Å) at a second polysilicon layer, the second polysilicon layer and etching away all of the region forming an isolation dielectric layer regions to be filled (Figure 18);

[0086] 13)按照现有工艺,通过离子注入,形成基极(BODY)和源极(Source); [0086] 13) in accordance with prior art, by ion implantation, forming a base (the BODY) and the source (the Source);

[0087] 14)在涂硼磷硅玻璃的同时,在待填充隔离介质层区内,硼磷硅玻璃也会自然流入,从而形成横向隔离介质层,即当涂厚度为5000〜10000埃的硼磷硅玻璃作为接触孔的隔离介质层,在步骤12)形成的待填充隔离介质层区内,该硼磷硅玻璃厚度足以填满该区域,形成接触孔的隔离介质(ILD)层的同时也形成双层多晶硅的横向隔离区(如图19所示); [0087] 14) while borophosphosilicate glass coating in the area to be filled isolation dielectric layer, borophosphosilicate glass will naturally flow into, thereby forming a lateral isolation dielectric layer, i.e. a thickness of Dang boron 5000~10000 Å phosphosilicate glass as a contact hole barrier dielectric layer filling the isolation dielectric layer region to be in step 12) is formed, the borophosphosilicate glass thickness sufficient to fill the region, the contact hole is formed in the isolation dielectric (ILD) layer also to form a double polysilicon lateral isolation region (19);

[0088] 15)按照现有工艺,形成接触孔、金属和钝化层,即利用掩膜板刻蚀形成接触孔,淀积金属层并刻蚀形成接触电极,淀积并刻蚀形成钝化层。 [0088] 15) According to the prior process, a contact hole is formed, the metal and passivation layers, i.e., an etching mask is formed using a contact hole, a metal layer is deposited and etched to form a contact electrode, is deposited and etched to form a passivation Floor.

[0089]本发明通过在第二层多晶娃淀积与反刻蚀后,Poly Cover层光刻,定义源极多晶硅引出端旁特定长度区域,将该区域的栅极多晶硅全部刻蚀,然后利用后续接触孔工艺前涂布的硼磷娃玻璃填充Poly Cover层定义的区域,形成横向隔离,即本发明在刻蚀出来的一个沟槽一直保持到接触孔形成之前,利用ILD层的硼磷硅玻璃填入,由此形成源极多晶硅引出端与栅极多晶硅的横向隔离区域,同时,该后续同现有工艺。 [0089] By the present invention, after the deposition of the second layer polycrystalline baby and anti-etching, Poly Cover layer lithography, defining source polysilicon lead-out area next to the end of a particular length, the gate polysilicon etch the entire area, and using the process prior to coating a subsequent contact hole region of borophosphosilicate glass filled baby Poly Cover layer defined, lateral isolation is formed, i.e., the present invention is out of a trench etching is maintained until the hole is formed prior to contact by the ILD layer of borophospho silica glass filled, thereby forming a polysilicon source and leading ends of the gate polysilicon lateral isolation region at the same time, with the subsequent conventional processes.

[0090]按照上述方法进行,本发明的工作区域得到很大扩张,并且能降低工艺成本和控制难度,提高器件工作性能。 [0090] in accordance with the method described above, the work area is greatly expanded according to the present invention, and can be difficult to control and reduce process costs, improve the performance of the device.

Claims (11)

1.一种形成沟槽型双层栅MOS结构两层多晶硅横向隔离的方法,其特征在于,包括步骤: 1)在硅基板上,生长作为保护层的第一氮化膜; 2)在硅基板上,进行沟槽刻蚀; 3)沟槽内生长介质层; 4)在介质层上,生长第一层多晶硅; 5)对第一层多晶硅进行第一步反刻蚀,直至刻蚀至硅表面; 6)对第一层多晶硅进行光刻及第二步反刻蚀,并去除第一层多晶硅上方的沟槽侧壁介质层; 其中,对第一层多晶硅进行光刻,保护住需要接出源极多晶硅的位置,剩余的第一层多晶硅位置进行第二步多晶硅反刻蚀,直至刻蚀至硅表面以下所需深度; 7)在沟槽的底部和侧壁以及硅基板表面淀积第二氮化膜后,刻蚀去除沟槽底部的第二氮化膜,露出第一层多晶硅; 8)在第一层多晶硅上,生长热氧化层; 9)去除沟槽侧壁的第二氮化膜和硅基板表面的第一、二氮化膜; 10)栅极氧 A method for trench-type double gate MOS structure having two lateral polysilicon spacer is formed, characterized by comprising the steps of: 1) a silicon substrate, growing a first nitride film as the protective layer; 2) silicon on a substrate, a trench etching; 3) growth of the dielectric layer within the trench; 4) on the dielectric layer, growing a first polysilicon layer; 5) on the first polysilicon layer is the first step anti-etching until the etched to silicon surface; 6) of the first polysilicon layer and a second step anti-etching photolithography, and removing the sidewalls of the trench dielectric layer over the first polysilicon layer; wherein the first layer polysilicon lithography, living need protection a source polysilicon contact position, the remaining first polysilicon layer polysilicon position by a second step anti-etching until the silicon surface is etched to the desired depth; 7) on the bottom surface of the lake and the silicon substrate and sidewalls of the trench the product of the second nitride film, the nitride film is removed by etching the second bottom of the trench, the exposed first polysilicon layer; 8) on the first layer of polycrystalline silicon, thermal oxide layer growth; 9) removing the first trench sidewalls two nitride film and the first and second nitride film of the silicon substrate surface; 10) gate oxide 层生长; 11)在沟槽内淀积第二层多晶硅,并刻蚀至硅表面; 12)多晶硅光刻,定义靠近热氧化层端的第二层多晶硅处的待填充隔离介质层区域,并将该区域内的第二层多晶硅全部刻蚀掉,形成待填充隔离介质层区; 13)形成基极和源极; 14)在涂硼磷硅玻璃的同时,在待填充隔离介质层区内,硼磷硅玻璃会流入,形成隔离介质层; 15)形成接触孔、金属、钝化层。 Layer is grown; 11) depositing a second polysilicon layer within the trench and etched to the silicon surface; 12) of polysilicon lithography, isolation dielectric layer regions to be filled at the second polysilicon layer is defined near the end of the thermally oxidized layer, and the second polysilicon layer is etched away all of the region, an isolation dielectric layer forming region to be filled; 13) forming a base and a source; 14) while the coating is borophosphosilicate glass, isolation dielectric layer in the area to be filled, borophosphosilicate glass will flow, forming an isolation dielectric layer; 15) forming a contact hole, a metal, a passivation layer.
2.如权利要求1所述的方法,其特征在于:所述步骤I)中,生长第一氮化膜的方法包括:低压化学气相沉积或等离子体增强式化学气相沉积;第一氮化膜的材质包括:氮化硅;第一氮化膜的厚度为500〜3000埃。 First nitride film; low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition: 2. A method as claimed in claim 1, wherein: said step I), the method of growing the first nitride film comprises material comprising: a silicon nitride; thickness of the first nitride film is 500~3000 Å.
3.如权利要求1所述的方法,其特征在于:所述步骤3)中,介质层为氧化膜,包括:氧化硅,厚度为500〜3000埃;介质层的生长方式包括:热氧或低压化学气相沉积方式。 3. The method according to claim 1, wherein: in the step 3), the dielectric layer is an oxide film comprising: silicon oxide, having a thickness of 500~3000 Å; growth pattern the dielectric layer comprises: an oxygen or heat a low pressure chemical vapor deposition method.
4.如权利要求1所述的方法,其特征在于:所述步骤4)中,生长第一层多晶硅的方法包括:低压化学气相沉积;第一层多晶硅的厚度为足以填满沟槽内部。 4. The method according to claim 1, wherein: said step 4), the method of growing a first polysilicon layer comprising: a low pressure chemical vapor deposition; thickness of the first polysilicon layer sufficient to fill the inside of the trench.
5.如权利要求1所述的方法,其特征在于:所述步骤5)中,第一步反刻蚀时,直至刻蚀至硅表面。 5. The method according to claim 1, wherein: said step 5), when the first step anti-etching until the etched to the silicon surface.
6.如权利要求1所述的方法,其特征在于:所述步骤6)的对第一层多晶硅进行光刻及第二步反刻蚀中,对第一层多晶硅进行光刻,保护住需要接出源极多晶硅的位置,剩余的第一层多晶硅位置进行第二步多晶硅反刻蚀,直至刻蚀至硅表面以下所需深度。 6. The method according to claim 1, wherein: said step 6) of the first layer and a second step anti-lithographic etching polysilicon, the first layer polysilicon lithography, living need protection a source polysilicon contact position, the remaining first polysilicon layer polysilicon position by a second step anti-etching until the silicon is etched to a desired depth below the surface.
7.如权利要求1所述的方法,其特征在于:所述步骤7)中,第二氮化膜淀积的方法包括:低压化学气相沉积或等离子体增强式化学气相沉积;第二氮化膜的材质包括:氮化硅;第二氮化膜的厚度为500〜3000埃;刻蚀的方法为干法刻蚀。 7. The method according to claim 1, wherein: in the step 7), the second nitride film deposition method comprising: a low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; second nitride film material comprising: silicon nitride; thickness of the second nitride film is 500~3000 Å; etching method is dry etching.
8.如权利要求1所述的方法,其特征在于:所述步骤8)中,生长热氧化层的方法为通过热氧方式生长;其中,热氧方式中的工艺温度为高于950°C;热氧化层的厚度为500〜3000埃。 8. The method according to claim 1, wherein: in the step 8), the method of growing a thermal oxide layer is grown by thermal oxidation mode; wherein the thermal process temperature is higher than the oxygen mode is 950 ° C ; thickness of the thermal oxide layer is 500~3000 Å.
9.如权利要求1所述的方法,其特征在于:所述步骤9)中,去除的方式包括:湿法刻蚀。 9. The method according to claim 1, wherein: in the step 9), removal methods include: wet etching.
10.如权利要求1所述的方法,其特征在于:所述步骤12)中,待填充隔离介质层区域的宽度为1000〜10000埃。 10. The method according to claim 1, wherein: in the step 12), the width to be filled isolation dielectric layer region is 1000~10000 Å.
11.如权利要求1所述的方法,其特征在于:所述步骤14)中,硼磷硅玻璃的厚度为5000〜10000埃。 11. The method according to claim 1, wherein: in the step 14), the thickness of borophosphosilicate glass 5000~10000 Å.
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