CN103903969B - The preparation method of floating boom - Google Patents
The preparation method of floating boom Download PDFInfo
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- CN103903969B CN103903969B CN201210576099.0A CN201210576099A CN103903969B CN 103903969 B CN103903969 B CN 103903969B CN 201210576099 A CN201210576099 A CN 201210576099A CN 103903969 B CN103903969 B CN 103903969B
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- 238000007667 floating Methods 0.000 title claims abstract description 65
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000001039 wet etching Methods 0.000 claims abstract description 27
- 238000001312 dry etching Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 230000008878 coupling Effects 0.000 claims abstract description 11
- 238000010168 coupling process Methods 0.000 claims abstract description 11
- 238000005859 coupling reaction Methods 0.000 claims abstract description 11
- 238000002513 implantation Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 12
- 238000006396 nitration reaction Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 25
- 230000008569 process Effects 0.000 description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 238000000151 deposition Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 238000011049 filling Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000001808 coupling effect Effects 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 241000562516 Thisbe Species 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
The invention discloses a kind of preparation method of floating boom. The method comprises: S1, in Semiconductor substrate, form fleet plough groove isolation structure, and the upper surface of fleet plough groove isolation structure is above Semiconductor substrate upper surface the first height H 1; S2 is formed with source region in Semiconductor substrate by Implantation; S3 forms tunnel oxide in Semiconductor substrate; S4 deposits floating boom material layer in tunnel oxide; S5, planarization floating boom material layer exposes the upper surface of fleet plough groove isolation structure; And S6, etching is removed part fleet plough groove isolation structure, forms floating boom; Step S6 comprises: adopt wet etching to remove the fleet plough groove isolation structure of the second height H 2, make between floating boom and the control gate of follow-up formation coupling efficiency higher; Then adopt dry etching to remove the fleet plough groove isolation structure of third high degree H3, form floating boom. Apply technical scheme of the present invention, make the coupling efficiency between floating boom and the control gate of follow-up formation higher, and avoided the risk of short circuit between active area and control gate.
Description
Technical field
The present invention relates to IC-components manufacturing technology field, in particular to a kind of preparation method of floating boom.
Background technology
In recent years, the application that high density flash memory is gone up has in a lot of fields received very large concern, because the dwindling of memory cell sizeCan significantly lower manufacturing cost.
At present, the floating boom of IC-components is formed with several different methods. Wherein, a kind of typical floating boom preparation method is as follows: 1)Providing Semiconductor substrate, for example silicon wafer, silicon-on-insulator or epitaxial silicon chip; 2) use high-density plasma process deposits padSilicon oxide layer and silicon nitride layer, etching forms trench area; Filling groove district on silicon nitride layer surface; 3) use chemical machineThe planarization of tool glossing, by the silicon oxide layer of high-density plasma process deposits, forms trench area isolation structure and exposes nitrogenSiClx layer; 4) optionally remove silicon nitride layer by wet-etching technology, form from bottom, trench area and extend to pad oxide skin(coating)Above fleet plough groove isolation structure; 5) remove the oxygen that passes through high-density plasma process deposits in pad oxide skin(coating) and trench areaA part for SiClx layer; 6) use photoresist as mask, form source-drain electrode and the ditch in Semiconductor substrate by ImplantationRoad district; 7) form tunnel oxide; 8) deposit spathic silicon material; 9) deposit cover oxide material; 10) planarization polysiliconMaterial, the top of exposing fleet plough groove isolation structure; 11) use HF impregnation technology to remove the high-density plasma that passes through in trench areaA part for the silicon oxide layer of body technology deposition, forms floating boom.
In above-mentioned steps 11) in remove the silicon oxide layer that pass through high-density plasma process deposits in trench area a part lead toNormal what adopt is wet etching, and this is because wet etching is isotropic etching, the ONO layer that forms afterwards (silica-Silicon-nitride and silicon oxide layer) parcel floating boom area larger, make the coupling efficiency between floating boom and the control gate of follow-up formation higher. ButThat it exists following technical problem: 1), if the process of wet etching is not controlled well, will be etched directly into active area, causeShort circuit between active area and the control gate of follow-up formation; 2), after wet etching, the coupling effect between floating boom and floating boom is larger, shadowRing performance of semiconductor device. If but adopt dry etching (anisotropic etching), although do not have source region and follow-up formationControl gate between the risk of short circuit, but the coupling effect between floating boom and floating boom can increase and the control of floating boom and follow-up formationCoupling efficiency between grid processed is also less; And the noticeable electrical thickness reduction that also has dry etching can make ONO layer. InstituteWith current above-mentioned steps 11 urgently to be resolved hurrily) in etching exist above-mentioned technical problem.
Summary of the invention
The present invention aims to provide a kind of preparation method of floating boom, removes to solve in prior art part silicon oxide layer in trench areaCoupling efficiency between the active area existing in journey and control gate between the risk of short circuit or floating boom and the control gate of follow-up formation is lessTechnical problem.
To achieve these goals, according to an aspect of the present invention, provide a kind of preparation method of floating boom. This preparation methodComprise the following steps: S1, form fleet plough groove isolation structure, and the upper surface of fleet plough groove isolation structure exceeds in Semiconductor substrateIn Semiconductor substrate upper surface the first height H 1; S2 is formed with source region in Semiconductor substrate by Implantation; S3, halfIn conductive substrate, form tunnel oxide; S4, in tunnel oxide, deposition forms floating boom material layer; S5, planarization is floatingGate material layer is exposed the upper surface of fleet plough groove isolation structure; And S6, etching is removed part fleet plough groove isolation structure, forms floating boom;Step S6 comprises: adopt wet etching to remove the fleet plough groove isolation structure of the second height H 2, make the control of floating boom and follow-up formationBetween grid processed, coupling efficiency is higher; Then adopt dry etching to remove the fleet plough groove isolation structure of third high degree H3, form floating boom, itsIn, H2+H3≤H1.
Further, the first height H 1 is 600 ~ 700 dusts.
Further, the second height H 2 is 250 ~ 400 dusts.
Further, the wet etching in step S6 comprises that the etching solution that employing contains hydrofluoric acid carries out etching.
Further, the dry etching in step S6 comprises and carries out etching using carbon tetrafluoride as presoma.
Further, step S1 comprises: in Semiconductor substrate, deposition forms pad oxide skin(coating) and nitration case; Etching forms grooveDistrict, and deposition forms silicon oxide layer filling groove district to nitration case; Planarization silicon oxide layer is to nitration case; Etching is removed nitrogenChange layer and pad oxide, obtain fleet plough groove isolation structure.
Further, the material of Semiconductor substrate is silicon wafer, silicon-on-insulator or epitaxial silicon chip.
Further, silicon oxide layer forms by high-density plasma process deposits.
Further, after step S6, further comprise: on floating boom, form dielectric layer, dielectric layer is silica-silicon nitride-oxygenSiClx layer.
Further, the thickness of dielectric layer is 140 ± 3 dusts.
Apply technical scheme of the present invention, in the time that etching is removed part fleet plough groove isolation structure, first adopt wet etching to remove theThe fleet plough groove isolation structure of one degree of depth, then adopts dry etching to remove the described fleet plough groove isolation structure of second degree of depth, forms floatingGrid. So just overcome the shortcoming with dry etching or private wet etching separately simultaneously, also had both its both advantage, this isBecause first adopt wet etching, and wet etching is isotropic etching, make ONO layer (silica-silicon-nitride and silicon oxideLayer) parcel floating boom area larger, thereby make the coupling efficiency between floating boom and the control gate of follow-up formation higher; Then adopt dryMethod etching, has avoided the risk of short circuit between active area and control gate.
Brief description of the drawings
The Figure of description that forms the application's a part is used to provide a further understanding of the present invention, schematic reality of the present inventionExecute example and explanation thereof for explaining the present invention, do not form inappropriate limitation of the present invention. In the accompanying drawings:
Fig. 1 shows the structural representation of the semiconductor devices forming to S5 according to the step S1 of the embodiment of the present invention;
Fig. 2 shows according to the structural representation of the semiconductor devices forming after the wet etching of the embodiment of the present invention; And
Fig. 3 shows according to the FGS floating gate structure schematic diagram forming after the dry etching of the embodiment of the present invention.
Detailed description of the invention
It should be noted that, in the situation that not conflicting, the feature in embodiment and embodiment in the application can combine mutually.Describe below with reference to the accompanying drawings and in conjunction with the embodiments the present invention in detail.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " above" etc., be used for describing as the spatial relation of a device shown in the figure or feature and other devices or feature. Should manageSeparate, space relative terms is intended to comprise the difference in using or operating except the described in the drawings orientation of deviceOrientation. For example, if the device in accompanying drawing is squeezed, be described as " above other devices or structure " or " at other devices orOn structure " device after will be positioned as " other devices or structure below " or " other devices or construct under ". Thereby,Exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation. This device also can otherDifferent modes location (90-degree rotation or in other orientation), and make corresponding to the space relative descriptors that used hereExplain.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention. But, these exemplary embodimentsCan be implemented by multiple different form, and should not be interpreted as being only limited to the embodiments set forth herein. Be to be understood that, provide these embodiment be for make of the present invention disclose thorough and complete, and by the structure of these exemplary embodimentsThink fully to convey to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expanded the thickness in layer and region, andAnd use identical Reference numeral to represent identical device, thereby will omit description of them.
A kind of typical embodiment according to the present invention, provides a kind of preparation method of floating boom. As shown in Figures 1 to 3, the methodComprise the following steps: S1, in Semiconductor substrate 10, form fleet plough groove isolation structure 20, and fleet plough groove isolation structure 20 is upperSurface is above Semiconductor substrate 10 upper surface the first height H 1; S2, is formed with in Semiconductor substrate 10 by ImplantationSource region; S3 forms tunnel oxide 30 in Semiconductor substrate 10; S4, in tunnel oxide 30, deposition forms floatingGate material layer; S5, planarization floating boom material layer exposes the upper surface of fleet plough groove isolation structure 20; And S6, etching is removed partFleet plough groove isolation structure 20, forms floating boom 40; Step S6 comprises: adopt wet etching to remove the shallow trench isolation of the second height H 2From structure 20, make between floating boom 40 and the control gate of follow-up formation coupling efficiency higher; Then adopt dry etching to remove third highThe fleet plough groove isolation structure 20 of degree H3, forms floating boom 40, wherein, and H2+H3≤H1.
Apply technical scheme of the present invention, in the time that etching is removed part fleet plough groove isolation structure 20, first adopt wet etching to removeThe fleet plough groove isolation structure 20 of the first height H 1, then adopts dry etching to remove the described shallow trench isolation junction of the second height H 2Structure 20, forms floating boom 40. So overcome the shortcoming with dry etching or private wet etching separately simultaneously, also had both its twoPerson's advantage, this is because first adopt wet etching, and wet etching is isotropic etching, makes ONO layer (silica-silicon-nitride and silicon oxide layer) parcel floating boom 40 area larger, thereby make the coupling between floating boom 40 and the control gate of follow-up formationRate is higher; Then adopt dry etching, avoided the risk of short circuit between active area and control gate.
The one typical embodiment according to the present invention, the first height H 1 is 600 ~ 700 dusts, the making of this device that is highly applicable to becoming more meticulous.
Technical scheme of the present invention is suitable in 65nm technology, because it is very little to make window in 65nm technology, the error in a wafer of the thickness after floating boom cmp is very large, if adopt fixing numerical value to do when etching, can bring twoProblem: if floating boom is heavy too thin, the minimum point of trench area part can be also lower than active area after etching, the consequence of bringing like thisBe that electric leakage possibility is very large, the ability of write-in program reduces a lot; If floating boom is too thick conversely speaking,, the interference meeting between floating boomStrengthen. So doing before wet etching and will first doing an assessment to floating boom thickness, then adjust to carve according to actual floating boom thickness and wetMethod etch depth, to form high-quality semiconductor devices. Preferably, the second height H 2 is that 250 ~ 400 dusts are (according to floatingGrid height adjustment, each etching (step) is 50 dusts, enough ensures the coupling efficiency between floating boom 40 and the control gate of follow-up formationHigher, and ensure H2+H3≤.
Preferably, the wet etching in step S6 comprises that the etching solution that employing contains hydrofluoric acid carries out etching, while reaction by controlBetween control the degree of depth under etching.
Preferably, the dry etching in step S6 carries out etching using carbon tetrafluoride as presoma, etching 300-350 dust.
Preferably, after step S6, further comprise: on floating boom, form dielectric layer, dielectric layer is silica-silicon nitride-oxidationSilicon (ONO) layer. Same ONO physical thickness, with the electrical thickness of ONO layer forming after wet etching be 140 ~ 150 dusts,Than add dry etching thickness (120-130 dust) thick 13.80% out by wet method. Through assessment, in order to ensure final productsPerformance, we need to be the physical thickness of ONO add the thickness of 10 left and right dusts during than wet etching again, thus preferably,The electrical thickness that ensures dielectric layer is 140 ± 3 dusts.
A kind of typical embodiment according to the present invention, step S1 comprises: in Semiconductor substrate 10, deposition forms pad oxideLayer and nitration case; Etching forms trench area, and deposition forms silicon oxide layer filling groove district to nitration case; Planarization oxidationSilicon layer is to nitration case; Etching is removed nitration case and pad oxide, obtains fleet plough groove isolation structure 20. Adopt in this way and to formThe part of fleet plough groove isolation structure 20 more than Semiconductor substrate 10 upper surfaces is up-narrow and down-wide, removes like this at follow-up dry etchingWhen second degree of depth, as shown in Figure 3, have fraction remnants 31, can make the coupling effect meeting between floating boom 40 and floating boom 40Reduce, improve the performance of semiconductor devices.
The typical embodiment of one according to the present invention, the formation of floating boom 40 specifically comprises the steps:
1) provide Semiconductor substrate 10, such as silicon wafer, silicon-on-insulator or epitaxial silicon chip etc.; Form and cover Semiconductor substrate 10Pad oxide. This pad oxide can be the oxide of at high temperature producing by boiler tube, can also use chemical vapour deposition (CVD) workSkill or other applicable technique form. Pad form on oxide silicon nitride layer (the present thickness of silicon nitride layer is 1300 dusts becauseFloating boom height is determined by silicon nitride layer thickness, so high silicon nitride can bring high floating boom, and high floating boom brings better controlGrid processed, to the coupling effect of floating boom, improve device performance. So now meeting on the basis of shallow trench isolation layer filling capacity,Silicon nitride layer can be set to the thickness of 1400-1450 dust), this silicon nitride layer can utilize dichlorosilane and NH3As forerunnerThe chemical vapor deposition method of body forms, and other appropriate method that also can apply in addition plasma activated chemical vapour deposition form.
2) use photoetching and etching technics to form trench area, wherein, etching technics can be wet etching, can be also that dry method is carvedErosion. Then use high-density plasma process deposits to form silicon oxide layer, filling groove district on silicon nitride layer surface.In a preferred embodiment, this silicon oxide layer is in ar gas environment, to utilize silane and oxygen as presoma, uses high density etc.Gas ions (HDP) deposition forms.
3) use CMP process planarization by the silicon oxide layer of high-density plasma process deposits, form trench areaIsolation structure, and this trench area isolation structure exceeds substrate top surface first height, is equivalent to the height of floating boom 40. In this stepCMP process also can adopt other suitable flatening process to replace, such as anti-etching, reflux or its combination etc.In specific embodiment, this first can be highly 600 ~ 700 dusts, and certainly, according to actual needs, this highly can basisThe different height of different designs of semiconductor devices.
4) optionally remove silicon nitride layer by wet-etching technology, in specific embodiment, can use the wet of phosphoric acid classMethod etching technics optionally place to go silicon nitride layer (because silicon nitride layer remove in, the hydrofluoric acid of dilution is to silica alsoHave certain etch capabilities, we find that suitably lengthening the time of making can increase floating boom width, and the coupling of grid to floating boom tightens controlClose ability). Also can use other etch process herein, for example reactive ion etching (RIE).
5) remove a part that pads the silicon oxide layer that passes through high-density plasma process deposits in oxide skin(coating) and trench area. ItsMiddle pad oxide skin(coating) can use the wet method selective etch of hydrofluoric acid class, can certainly adopt reactive ion etching (RIE).
6) use photoresist as mask, form the active area in Semiconductor substrate 10 by Implantation.
7) form tunnel oxide. Tunnel oxide can use the chemical gaseous phase deposition method shape of tetraethyl orthosilicate as presomaBecome, also can use the technique of other applicable silica deposition to form, for example, using dichlorosilane and oxygen as presomaChemical vapor deposition method forms.
8) deposit spathic silicon material (floating boom material layer);
9) deposit cover oxide material, this lid oxide material can be that dichlorosilane and oxygen are heavy as the chemical gaseous phase of presomaLong-pending technique forms. Lid oxide material is for protecting polycrystalline silicon material at CMP process, and he can prevent polysiliconLayers of material, can also protect large stretch of polysilicon region and reduce polysilicon depression.
10) planarization polycrystalline silicon material, the top of exposing fleet plough groove isolation structure 20.
11) adopt wet etching to remove the fleet plough groove isolation structure 20 of first degree of depth, make the control gate of floating boom 40 and follow-up formationBetween coupling efficiency higher; Then adopt dry etching to remove the described fleet plough groove isolation structure 20 of second degree of depth, form floating boom 40.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for those skilled in the art, the present invention can have various modifications and variations. Within the spirit and principles in the present invention all, any amendment of doing, etc.With replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a preparation method for floating boom, comprises the following steps:
S1, at Semiconductor substrate (10) upper formation fleet plough groove isolation structure (20), and described fleet plough groove isolation structure (20)Upper surface above described Semiconductor substrate (10) upper surface the first height H 1;
S2 is formed with source region by Implantation in described Semiconductor substrate (10);
S3, in the upper tunnel oxide (30) that forms of described Semiconductor substrate (10);
S4, forms floating boom material layer in the upper deposition of described tunnel oxide (30);
S5, floating boom material layer exposes the upper surface of described fleet plough groove isolation structure (20) described in planarization; And
S6, etching is removed the described fleet plough groove isolation structure of part (20), forms floating boom (40); It is characterized in that, described inStep S6 comprises:
Adopt wet etching to remove the described fleet plough groove isolation structure (20) of the second height H 2, make described floating boom (40)And between the control gate of follow-up formation, coupling efficiency is higher;
Then adopt dry etching to remove the described fleet plough groove isolation structure (20) of third high degree H3, form described floating boom(40), wherein, H2+H3≤H1.
2. preparation method according to claim 1, is characterized in that, described the first height H 1 is 600～700 dusts.
3. preparation method according to claim 1, is characterized in that, described the second height H 2 is 250～400 dusts.
4. preparation method according to claim 1, is characterized in that, the described wet etching in described step S6 comprises employingThe etching solution that contains hydrofluoric acid carries out etching.
5. preparation method according to claim 2, is characterized in that, the described dry etching in described step S6 comprises with fourFluorocarbons carries out etching as presoma.
6. preparation method according to claim 1, is characterized in that, described step S1 comprises:
Form pad oxide skin(coating) and nitration case in the upper deposition of described Semiconductor substrate (10);
Etching forms trench area, and deposition formation silicon oxide layer is filled described trench area to described nitration case;
Described in planarization, silicon oxide layer is to described nitration case;
Etching is removed described nitration case and described pad oxide skin(coating), obtains described fleet plough groove isolation structure (20).
7. preparation method according to claim 6, is characterized in that, the material of described Semiconductor substrate (10) be silicon wafer,Silicon-on-insulator or epitaxial silicon chip.
8. preparation method according to claim 6, is characterized in that, described silicon oxide layer is by high-density plasma techniqueDeposition forms.
9. preparation method according to claim 2, is characterized in that, after described step S6, further comprises: described floatingOn grid, form dielectric layer, described dielectric layer is silica-silicon-nitride and silicon oxide layer.
10. preparation method according to claim 9, is characterized in that, the thickness of described dielectric layer is 140 ± 3 dusts.
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| CN105789035B (en) * | 2014-12-24 | 2019-03-26 | 上海格易电子有限公司 | A kind of floating gate and preparation method thereof |
| CN105826326B (en) * | 2016-03-22 | 2018-11-09 | 上海华力微电子有限公司 | A kind of lithographic method for the trench oxide improving deep-submicron flush memory device coupling efficiency |
| CN112038344A (en) * | 2019-06-04 | 2020-12-04 | 联华电子股份有限公司 | Method for manufacturing floating gate memory element |
| CN113611654B (en) * | 2020-11-03 | 2022-04-19 | 联芯集成电路制造(厦门)有限公司 | Manufacturing method for reducing height difference of shallow trench isolation |
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