CN112038344A

CN112038344A - Method for manufacturing floating gate memory element

Info

Publication number: CN112038344A
Application number: CN201910480200.4A
Authority: CN
Inventors: 易亮; 任驰; 李志国
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2019-06-04
Filing date: 2019-06-04
Publication date: 2020-12-04

Abstract

The invention discloses a method for manufacturing a floating gate memory element, which comprises the following steps: a plurality of isolation structures are formed in the substrate, and a plurality of sidewalls of at least two adjacent isolation structures are partially exposed. A gate dielectric layer is formed on the substrate between two adjacent isolation structures. At least one floating gate is formed on the gate dielectric layer. A spacer is formed on at least one sidewall of at least two adjacent isolation structures and covers a portion of the floating gate. The floating gate is etched back using the spacer as an etching mask.

Description

Method for manufacturing floating gate memory element

Technical Field

The present invention relates to a method for manufacturing a memory device, and more particularly, to a method for manufacturing a floating gate memory device (floating gate memory device).

Background

In a modern society in which information is highly developed, a microprocessor system (microprocessor system) capable of rapidly processing data and arranging digital information has become an important element of information electronic products such as application chip systems, mobile phones, personal digital assistants, notebook computers, digital cameras, and the like. The memory used to store digital data and provide access to data by the microprocessor system is one of the most important components of the microprocessor system. Flash memory (flash memory) is a memory device that is electronically operated to allow a microprocessor system to store data in a non-volatile manner and to access data quickly and efficiently. The method has the advantages of no data loss during power failure, high transmission speed, low power consumption and long storage life, and is widely applied to various microprocessor systems at present.

A typical flash memory, such as a floating gate memory device, is composed of a floating gate (floating gate) and a Metal-Oxide Semiconductor (MOS) transistor. The floating gate is located in a gate dielectric layer of the MOS transistor and is isolated from the semiconductor substrate, the drain, the source and the control gate. When writing data to a floating gate memory device, appropriate biasing of the control gate, source, drain and semiconductor substrate is required to induce hot electrons (hot electrons) to flow through the gate dielectric layer into the floating gate. Depending on the amount and electrical properties of the charge injected into the floating gate, different data states may be associated.

For example, when a floating gate is injected with negative electrons, the corresponding digital data state is labeled "1"; conversely, when the negative electrons injected into the floating gate are removed, the corresponding digital data state is labeled "0". When erasing data from a floating gate memory device, appropriate biasing of the control gate, source, drain and semiconductor substrate is required to force electrons originally stored in the floating gate to flow through the gate dielectric layer to other electrodes by F-N tunneling (Fowler-Nordheim tunneling). By such injection or removal of negative electrons, the floating gate memory element has a characteristic of repeated reading and writing.

However, in the gate dielectric layer of the flash memory, structural Defects (Defects) of materials, such as atomic dislocations (dislocations), are easily generated during the manufacturing process, which causes a leakage phenomenon during the write/erase operation. Although increasing the thickness of the gate dielectric can improve the leakage problem, increasing the thickness of the gate dielectric not only significantly increases the operating power consumption of the floating gate memory bit, but also decreases the speed and efficiency of the erase operation.

Therefore, it is desirable to provide a method for fabricating a memory device to improve the speed and efficiency of the floating gate memory bit writing and erasing operations, and to solve the problems encountered in the prior art.

Disclosure of Invention

One embodiment of the present invention relates to a method for manufacturing a floating gate memory device, comprising the following steps: a plurality of isolation structures are formed in the substrate, and a plurality of sidewalls of at least two adjacent isolation structures are partially exposed. A gate dielectric layer is formed on the substrate between two adjacent isolation structures. At least one floating gate is formed on the gate dielectric layer. A spacer is formed on at least one sidewall of at least two adjacent isolation structures and covers a portion of the floating gate. The floating gate is etched back (etch back) using the spacer as an etching mask.

In view of the above, embodiments of the present invention provide a method for manufacturing a floating gate memory device. In the manufacturing process of forming the floating gate, a self-aligned etch-back manufacturing process is used for forming a protruding part and a recessed part in the floating gate, and the protruding part and the recessed part are used for increasing the overlapping surface area and the voltage coupling ratio of the floating gate and the control gate. Meanwhile, a plurality of conductive angles are formed at the position of the floating grid adjacent to the erasing grid and the character line so as to increase the electric field during the erasing operation and promote the F-N tunneling of electrons. The speed and efficiency of the write and erase operations of the floating gate memory device can be improved without adding additional photomasks.

Drawings

In order to make the aforementioned embodiments of the present invention comprehensible, other objects, features and advantages thereof, several preferred embodiments accompanied with figures are described in detail as follows:

fig. 1A to 1J are cross-sectional views of a part of a manufacturing process for manufacturing a floating gate memory device 100 according to an embodiment of the present disclosure;

FIG. 2 is a cross-sectional view of a portion of a floating gate fabrication process according to another embodiment of the present disclosure;

FIG. 3A is a top view of a floating gate memory cell structure according to one embodiment of the present description;

FIG. 3B is a cross-sectional view of the structure taken along line 3B-3B' of FIG. 3A;

FIG. 3C is a cross-sectional view of the structure taken along line 3C-3C' of FIG. 3A; and

FIG. 3D is a simplified perspective view of a portion of the structure shown in the circled position K of FIG. 3A.

Description of the symbols

100: floating gate memory element 101: base material

101 a: surface 102 of substrate: pad oxide layer

104: patterned hard mask layers 105, 125: etching process

106: opening 107: isolation structure

107 a: sidewall of isolation structure

107b, 107 b': upper surface of the isolation structure

108: gate dielectric layer 109: floating gate

109 a: top surface 109 b: concave part

109 c: projection 109 d: bottom surface

111: the clearance wall 112: patterned photoresist layer

113: dielectric layer 114: control gate layer

115: character line 116: erase gate

117: dielectric isolation layer 118A: source electrode

118B: drain electrode 120: lead angle

121. 122: planarization processes 123, 124: etch-back manufacturing process

H1: first height H2: second height

Θ, Θ': angles 3B-3B ', 3C-3C': tangent line

K: position of circle selection

Detailed Description

The present specification provides a method for fabricating a floating gate memory device, which can improve the speed and efficiency of bit erase operation of the floating gate memory device without increasing the gate dielectric thickness. In order to make the aforementioned embodiments and other objects, features and advantages of the present invention comprehensible, several methods of fabricating a metal-oxide-semiconductor image sensor are described in detail below, with reference to the accompanying drawings.

It should be noted, however, that the specific embodiments and methods are not to be considered as limiting the invention. The invention may be embodied with other features, elements, methods, and parameters. The preferred embodiments are provided only to illustrate the technical features of the present invention, and not to limit the claims of the present invention. Those skilled in the art will recognize that equivalent modifications and variations can be made in light of the following description without departing from the spirit of the invention. Like elements in different embodiments and drawings will be denoted by like reference numerals.

Referring to fig. 1A to 1J, fig. 1A to 1J are sectional views of a part of a manufacturing process for manufacturing a floating gate memory device 100 according to an embodiment of the present disclosure. The fabrication of the floating gate memory device 100 includes the following steps: first, a substrate 101 is provided, and a pad oxide layer (pad oxide)102 is formed on a surface 101a of the substrate 101. In some embodiments of the present description, the substrate 101 may be a silicon-containing substrate, such as a silicon wafer, a silicon-on-insulator (SOI) or other semiconductor substrate. The pad oxide layer 102 may be a Silicon Dioxide (SiO) layer formed on the surface 101a of the substrate 101 by a thermal oxidation process, a chemical oxidation process, or a deposition process₂) And (3) a layer.

Next, a plurality of Isolation structures 107, such as Shallow Trench Isolation (STI), are formed in the substrate 101. The formation of the isolation structure 107 includes the steps of: first, a patterned hard mask layer 104 is formed on the pad oxide layer 102; an etch process 105 is then performed using the patterned hard mask layer 104 as an etch mask to form a plurality of openings 106 through the pad oxide layer 102 and extending into the substrate 101 (as shown in fig. 1A). In some embodiments of the present description, the patterned hard mask layer 104 may be a silicon nitride (SiN) layer.

Then, the opening 106 is filled with a dielectric material, and the patterned hard mask layer 104 is used as a stop layer to perform a Planarization process 121, such as a Chemical-Mechanical polishing (CMP) process, to remove the dielectric material above the patterned hard mask layer 104 for forming a plurality of isolation structures 107 (as shown in fig. 1B) in the substrate 101. In some embodiments of the present disclosure, the dielectric material forming the isolation structure 107 may be silicon oxide (SiO), for example_x) Silicon carbide (SiC), Silicon Oxynitride (SiON), or other suitable material.

Thereafter, the patterned hard mask layer 104 and the pad oxide layer 102 are removed, exposing a portion of the sidewall 107a of each isolation structure 107 extending upward beyond the surface 101a of the substrate 101. In some embodiments of the present disclosure, after removing the patterned hard mask layer 104 and the pad oxide layer 102, the exposed portion of the sidewall 107a of the isolation structure 107 has a first height H1 (as shown in fig. 1C) from the surface 101a of the substrate 101 to the upper surface 107b of the isolation structure 107. In the present embodiment, first height H1 is between 100 angstroms (angstrom,

) To 500 angstroms.

Next, a gate dielectric layer 108 and a floating gate 109 on the gate dielectric layer 108 are formed on the surface 101a of the substrate 101 between the isolation structures 107. In some embodiments of the present description, the formation of the gate dielectric layer 108 and the floating gate 109 may include the following steps: first, a gate dielectric layer 108 is formed on the surface 101a of the substrate 101 between the isolation structures 107 by a deposition process, such as a Chemical Vapor Deposition (CVD) process; forming a semiconductor material layer 119 covering the gate dielectric layer 108 and the isolation structure 107 by another deposition process; a dielectric cap layer 110 is formed over the semiconductor material layer 119 by another deposition process (as shown in fig. 1D).

In some embodiments of the present description, the gate dielectric layer 108 may be a dielectric material layer composed of, for example, silicon oxide, silicon carbide, silicon oxynitride, or other suitable materials. The material forming the semiconductor material layer 119 may include polysilicon, germanium (Ge), Silicon-germanium (SiGe), or other suitable semiconductor materials. The dielectric cap layer 110 may be a silicon dioxide layer.

Subsequently, a planarization process 122, such as a chemical mechanical polishing process, is performed with the isolation structures 107 as a stop layer to remove the dielectric cap layer 110 and a portion of the semiconductor material layer 119 located above the isolation structures 107, so that the remaining semiconductor material layer 119 forms a plurality of floating gates 109 between two adjacent isolation structures 107 and stacked on the gate dielectric layer 108 (as shown in fig. 1E).

Then, an etch-back process 123 is performed on the floating gate 109 to expose a portion of the sidewall 107a of each isolation structure 107. In some embodiments of the present disclosure, after the etch-back process 123, the exposed portion of the sidewall 107a of the isolation structure 107 has a second height H2 (as shown in fig. 1F) from the top surface 109a of the floating gate 109 to the upper surface 107b of the isolation structure 107. In the present embodiment, the second height H2 is between 50 a and 250 a; preferably between 100 and 200 angstroms.

Thereafter, a spacer (spacer)111 is formed on a portion of the sidewall 107a exposed outside the isolation structure 107, such that the spacer 111 covers a portion of the top surface 109a of the floating gate 109 and exposes another portion of the top surface 109a (as shown in fig. 1G). In some embodiments of the present description, the spacers 111 comprise silicon nitride.

Next, using the spacer 111 as a mask, the floating gate 109 is etched back again by the etching-back process 124, so that the remaining floating gate 109 has a recess 109b and a protrusion 109 c. In one embodiment of the present disclosure, the recess 109b has a bottom surface 109d connected to the protrusion 109 c. The protrusion 109c is located below the spacer 111 and includes a portion of the top surface 109a covered by the spacer 111. The bottom surface 109d of the recess 109b and the top surface 109a of the protrusion 109c have a height difference S substantially between 50 a and 150 a. And the sidewall of protrusion 109c and the bottom surface 109d of recess 109b enclose an angle theta. In the present embodiment, the angle Θ formed by the sidewall of the protrusion 109c and the bottom surface 109d of the recess 109b can be 90 ° (as shown in fig. 1H). However, due to the limitation of the condition of the etch-back process 124, the angle Θ' formed by the sidewall of the protrusion 109c and the bottom surface 109d of the recess 109b may be a non-right angle. For example, in another embodiment of the present description, the angle Θ' may be between 90 ° and 165 ° (as depicted in fig. 2).

After removing the spacer 111, the floating gate 109 is covered by the patterned photoresist layer 112, and the isolation structure 107 is subjected to an etching process 125 to remove a portion of the isolation structure 107, such that the top surface 107 b' of the isolation structure 107 after etching is substantially lower than the top surface 109a of the protrusion 109c of the floating gate 109 (as shown in fig. 1I).

After removing the patterned photoresist layer 112, a dielectric layer 113 and a control gate layer 114 are sequentially formed on the isolation structure 107 and the floating gate 109 by a plurality of deposition processes, such as a chemical vapor deposition process and a patterning process (not shown), and partially cover the upper surface 107 b' of the isolation structure 107, the sidewalls and the top surface 109a of the protrusion 109c of the floating gate 109, and the bottom surface 109d of the recess 109 b. The control gate 114 and the floating gate 109 are electrically isolated by a dielectric layer 113 (as shown in fig. 1J). In some embodiments of the present disclosure, the dielectric layer 113 may be a multi-layer composite structure. For example, in the present embodiment, the dielectric layer 113 may include a triple-Oxide-Nitride-Oxide (ONO) structure.

Subsequently, a series of post-fabrication processes (not shown) are performed to form the floating gate memory device 100. Referring to fig. 3A to 3D, fig. 3A is a top view of a floating gate memory device 100 according to an embodiment of the present disclosure; FIG. 3B is a cross-sectional view of the structure taken along line 3B-3B' of FIG. 3A; FIG. 3C is a cross-sectional view of the structure taken along line 3C-3C' of FIG. 3A. Fig. 3D is a simplified perspective view of a portion of the structure depicted in the circled position K of fig. 3A.

The floating gate memory device 100 further includes a source 118A, a drain 118B, a word line 115, and an erase gate 116. The source 118A and the drain 118B are located in the substrate 101, adjacent to the floating gate 109, and electrically isolated from the floating gate 109 by the gate dielectric layer 108. The word line 115 and erase gate 116 are located over the gate dielectric 108, adjacent to the floating gate 109 and control gate 114, and are electrically isolated from the floating gate 109 and control gate 114, respectively, by a dielectric isolation layer 117. In some embodiments of the present description, the material constituting the dielectric isolation layer 117 may be the same as the material of the dielectric layer 113. For example, in the present embodiment, the dielectric isolation layer 117 may also be a three-layer composite structure including silicon oxide-silicon nitride-silicon oxide.

When writing data to the floating gate memory device 100, an appropriate set of biases can be applied to the control gate 114, the source 118A, the drain 118B, and the substrate 101 to induce hot electrons to flow through the gate dielectric layer 108 into the floating gate 109. When erasing data from the floating gate memory device 100, another set of appropriate bias voltages is applied to the control gate 114, the source 118A, the drain 118B and the substrate 101 to force electrons originally stored in the floating gate 109 to flow through the gate dielectric layer 108 into the drain 118B or through the dielectric isolation layer 117 into the erase gate 116 by F-N tunneling.

As shown in fig. 3D, since the protrusion 109a and the recess 109 of the floating gate 109 can increase the overlapping surface area of the floating gate 109 and the control gate 114, the capacitance therebetween is increased; the voltage Coupling Ratio (Coupling Ratio) between the control gate 114 and the floating gate 109 can be increased during the write operation, thereby improving the write efficiency. In addition, the arrangement of the protruding portion 109a and the recessed portion 109 of the floating gate 109 can also form a plurality of conductive corners 120 at the position where the floating gate 109 is adjacent to the erase gate 116 and the word line 115. During erasing operation, a larger electric field is formed at the conductive corner 120 adjacent to the word line 115 to promote tunneling of electrons, thereby achieving the purpose of improving erasing efficiency.

In light of the foregoing, embodiments of the present disclosure provide a method for fabricating a floating gate memory device 100. In the fabrication process for forming the floating gate 109, a self-aligned etch-back process 123 and 124 (as shown in fig. 1F to 1G) are used to form a protrusion 109a and a recess 109 in the floating gate 109, so as to increase the overlapping surface area and the voltage coupling ratio of the floating gate 109 and the control gate 114. Meanwhile, a plurality of conductive corners 120 are formed at the positions of the floating gate 109 adjacent to the erase gate 116 and the word line 115 to increase the electric field during the erase operation and promote the F-N tunneling of electrons. The speed and efficiency of the write and erase operations of the floating gate memory device 100 can be improved without adding additional photomasks.

Although the present invention has been described in connection with the preferred embodiments, it is not intended to be limited thereto, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for manufacturing a floating gate memory element comprises the following steps:

forming a plurality of isolation structures in the substrate, and partially exposing a plurality of sidewalls of at least two adjacent ones of the isolation structures;

forming a gate dielectric layer on the substrate between at least two adjacent ones of the isolation structures;

forming at least one floating gate on the gate dielectric layer;

forming a spacer (spacer) on at least one of the sidewalls and covering a portion of the floating gate; and

the spacer is used as an etching mask to perform a first etch back process on the floating gate.

2. The method of claim 1, wherein the step of forming the isolation structures comprises:

forming a pad oxide layer (pad oxide) on the substrate;

forming a patterned hard mask layer on the pad oxide layer;

performing an etching process using the patterned hard mask layer as an etching mask to form a plurality of openings through the pad oxide layer and extending into the substrate; and

the openings are filled with a dielectric material.

3. The method of claim 2, wherein forming the gate dielectric layer comprises removing the patterned mask layer and the pad oxide layer to expose a portion of each of the sidewalls, wherein the exposed portion of each of the sidewalls has a first height from the surface of the substrate to the top surface of the isolation structures, the first height being between 100 angstroms

To 500 angstroms.

4. The method of claim 2, wherein the patterned hard mask layer comprises silicon nitride; the pad oxide layer includes silicon oxide.

5. The method of manufacturing a floating gate memory device according to claim 1, wherein the step of forming the floating gate comprises:

forming a semiconductor layer to cover the gate dielectric layer and the isolation structure; and

the semiconductor layer is planarized with the isolation structure as a stop layer.

6. The method of claim 5, further comprising a second etch-back process for removing a portion of the floating gates to expose a portion of each of the sidewalls before forming the spacers, wherein the exposed portion of each of the sidewalls has a second height from a top surface of the floating gates to an upper surface of the isolation structures, the second height being between 50 angstroms and 250 angstroms.

7. The method of claim 6, wherein said spacer silicon is formed on said top surface and comprises silicon nitride.

8. The method of claim 7, wherein after the first etch-back process, the floating gate has a recess and a protrusion; the recess having a bottom surface; the protrusion is located below the spacer and includes a portion of the top surface.

9. The method of claim 8, wherein the protrusion is at a right angle or a non-right angle to the bottom surface.

10. The method of claim 8, wherein the top surface and the bottom surface have a height difference of between 50A and 150A.