CN103021957A - Method for increasing floating grid coupling coefficient of control grid in flash memory - Google Patents
Method for increasing floating grid coupling coefficient of control grid in flash memory Download PDFInfo
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- CN103021957A CN103021957A CN 201210576924 CN201210576924A CN103021957A CN 103021957 A CN103021957 A CN 103021957A CN 201210576924 CN201210576924 CN 201210576924 CN 201210576924 A CN201210576924 A CN 201210576924A CN 103021957 A CN103021957 A CN 103021957A
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- sidewall spacers
- gate layer
- coupling coefficient
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Abstract
The invention provides a method for increasing floating grid coupling coefficient of a control grid in a flash memory. The method includes: forming shallow ditch separations higher than an active area surface on two sides of the active area of a silicon wafer, and forming a grid oxide layer and a floating grid layer sequentially on the active area surface; forming an additive layer on the floating grid layer surface and the shallow ditch separation surface; forming side wall separators for etching the additive layer on the side walls of the shallow ditch separations; utilizing the side wall separators to etch the floating grid layer so as to form grooves in the floating grid layer; and removing the side wall separators.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of the raising and control grid in the flash memory to the method for floating boom coupling coefficient.
Background technology
Flash memory is convenient with it, and storage density is high, and the advantages such as good reliability become the focus of studying in the non-volatility memorizer.Since first flash memory products came out from the 1980s, along with development and the demand of each electronic product to storing of technology, flash memory was widely used in mobile phone, and notebook is in the movement such as palmtop PC and USB flash disk and the communication apparatus.
Fig. 1 schematically shows the flash memory grid dividing structure according to prior art.
As shown in Figure 1, the flash memory grid dividing structure according to prior art comprises gate oxide level 2, floating gate layer 3, control gate oxide level 4 and the control grid layer 5 that is arranged in successively on the silicon chip active area 1.
In Fig. 1, floating boom and control gate all are planar structures, because the oxide skin(coating) between floating boom and control gate 4 is general thicker than the oxide skin(coating) 2 of floating boom, so control gate is generally less than 50% to the coupling coefficient of floating boom, like this when wiping and programming, need to add higher voltage on the control gate, enough voltage is realized operation to floating boom to be coupled.
Therefore, hope can provide a kind of can the Effective Raise flash memory in the control grid to the method for floating boom coupling coefficient, thereby can reduce when wiping with programming operation required voltage on the control gate.
Summary of the invention
Technical problem to be solved by this invention is for having defects in the prior art, providing a kind of and can control grid to the method for floating boom coupling coefficient in the Effective Raise flash memory.
In order to realize above-mentioned technical purpose, according to a first aspect of the invention, provide a kind of the raising to control grid in the flash memory to the method for floating boom coupling coefficient, it comprises: floating gate layer forms step, be used for forming in the active area both sides of silicon chip the shallow trench isolation that is higher than surfaces of active regions from, and on surfaces of active regions, form successively gate oxide level and floating gate layer; Extra play forms step, is used on the floating gate layer surface and shallow trench insulation surfaces formation extra play; Sidewall spacers forms step, is used for the etching extra play, thus shallow trench isolation from sidewall form sidewall spacers; The floating gate layer etch step is used for utilizing sidewall spacers that floating gate layer is carried out etching, thereby forms groove in floating gate layer; Sidewall spacers is removed step, is used for removing sidewall spacers.
Preferably, extra play is the oxide skin(coating) that forms by CVD deposition (chemical vapour deposition (CVD)).
Preferably, carry out sidewall spacers by dry etching and form step.
Preferably, remove in the step at sidewall spacers, after removing sidewall spacers, can also adopt isotropic etching that the groove in the floating gate layer is carried out the bight sphering and process.
In according to the raising flash memory of first aspect present invention, control in the method for grid to the floating boom coupling coefficient, because increased the real surface of floating gate layer by the groove in the floating gate layer long-pending, namely increased the coupling capacitance between control gate and floating boom, so improved the control grid to the floating boom coupling coefficient, and whole step can be integrated in the manufacturing process of stacking gate flash memory, can not increase new mask.
According to a second aspect of the invention, provide a kind of the raising to control grid in the flash memory to the method for floating boom coupling coefficient, it comprises: floating gate layer forms step, be used for forming in the active area both sides of silicon chip the shallow trench isolation that is higher than surfaces of active regions from, and on surfaces of active regions, form successively gate oxide level and floating gate layer; Extra play forms step, is used on the floating gate layer surface and shallow trench insulation surfaces formation extra play; Sidewall spacers forms step, is used for the etching extra play, thus shallow trench isolation from sidewall form sidewall spacers; Silicon epitaxy step, the recess that is used between sidewall spacers is filled silicon; Sidewall spacers is removed step, is used for removing sidewall spacers, thereby forms the silicon protuberance at floating gate layer.
Preferably, extra play is the oxide skin(coating) that forms by the CVD deposition.
Preferably, carry out silicon epitaxy step by selective epitaxial.
Preferably, remove in the step at sidewall spacers, after removing sidewall spacers, can also adopt isotropic etching that the silicon protuberance is carried out the bight sphering and process.
Like this, in according to the raising flash memory of second aspect present invention, control in the method for grid to the floating boom coupling coefficient, because increased the real surface of floating gate layer by the silicon protuberance on the floating gate layer long-pending, namely increased the coupling capacitance between control gate and floating boom, so improved the control grid to the floating boom coupling coefficient, and whole step can be integrated in the manufacturing process of stacking gate flash memory, can not increase new mask.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the flash memory grid dividing structure according to prior art.
Fig. 2 schematically shows according to the floating gate layer formation step of control grid in the raising flash memory of first embodiment of the invention and the second embodiment to the method for floating boom coupling coefficient.
Fig. 3 schematically shows according to control grid in first embodiment of the invention and the raising flash memory the second embodiment the extra play of the method for floating boom coupling coefficient is formed step.
Fig. 4 schematically shows according to control grid in first embodiment of the invention and the raising flash memory the second embodiment the sidewall spacers of the method for floating boom coupling coefficient is formed step.
Fig. 5 schematically shows according to control grid in the raising flash memory of first embodiment of the invention the floating gate layer etch step of the method for floating boom coupling coefficient.
Fig. 6 schematically shows according to control grid in the raising flash memory of first embodiment of the invention the sidewall spacers of the method for floating boom coupling coefficient is removed step.
Fig. 7 schematically shows according to control grid in the raising flash memory of second embodiment of the invention the silicon epitaxy step of the method for floating boom coupling coefficient.
Fig. 8 schematically shows according to control grid in the raising flash memory of second embodiment of the invention the sidewall spacers of the method for floating boom coupling coefficient is removed step.
Need to prove, accompanying drawing is used for explanation the present invention, and unrestricted the present invention.Note, the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
The＜the first embodiment 〉
Fig. 2 to Fig. 6 schematically shows according to control grid in the raising flash memory of first embodiment of the invention the method for floating boom coupling coefficient.
Specifically,, comprise according to the method for control grid in the raising flash memory of first embodiment of the invention to the floating boom coupling coefficient to shown in Figure 6 such as Fig. 2:
Floating gate layer forms step, be used for forming in active area 1 both sides of silicon chip the shallow trench isolation that is higher than surfaces of active regions from, and on active area 1 surface, form successively gate oxide level 2 and floating gate layer 3, as shown in Figure 2;
Extra play forms step, is used on floating gate layer 3 surfaces and shallow trench insulation surfaces formation extra play 6; For example, extra play 6 is the oxide skin(coating)s that form by the CVD deposition, as shown in Figure 3;
Sidewall spacers forms step, is used for etching extra play 6, thus shallow trench isolation from sidewall form sidewall spacers 61 and 62; For example, carry out sidewall spacers by dry etching and form step, as shown in Figure 4;
The floating gate layer etch step is used for utilizing sidewall spacers 61 and 62 pairs of floating gate layers 3 to carry out etching, thereby forms groove 31 in floating gate layer 3, as shown in Figure 5;
Sidewall spacers is removed step, is used for removing sidewall spacers 61 and 62, as shown in Figure 6; Preferably, after removing sidewall spacers 61 and 62, can also adopt isotropic etching that the groove 31 in the floating gate layer 3 is carried out the bight sphering and process.
After this, can carry out the formation of follow-up normal control gate oxide level and control grid layer.
Like this, in according to the raising flash memory of first embodiment of the invention, control in the method for grid to the floating boom coupling coefficient, because increased the real surface of floating gate layer by the groove in the floating gate layer long-pending, namely increased the coupling capacitance between control gate and floating boom, so improved the control grid to the floating boom coupling coefficient, and whole step can be integrated in the manufacturing process of stacking gate flash memory, can not increase new mask.
The＜the second embodiment 〉
Fig. 2 to Fig. 4 and Fig. 7 to Fig. 8 schematically show according to control grid in the raising flash memory of second embodiment of the invention the method for floating boom coupling coefficient.
Specifically, extremely shown in Figure 8 such as Fig. 2 to Fig. 4 and Fig. 7, comprise according to the method for control grid in the raising flash memory of second embodiment of the invention to the floating boom coupling coefficient:
Floating gate layer forms step, be used for forming in active area 1 both sides of silicon chip the shallow trench isolation that is higher than surfaces of active regions from, and on active area 1 surface, form successively gate oxide level 2 and floating gate layer 3, as shown in Figure 2;
Extra play forms step, is used on floating gate layer 3 surfaces and shallow trench insulation surfaces formation extra play 6, as shown in Figure 3; For example, extra play 6 is the oxide skin(coating)s that form by the CVD deposition;
Sidewall spacers forms step, is used for etching extra play 6, thus shallow trench isolation from sidewall form sidewall spacers 61 and 62; For example, carry out sidewall spacers by dry etching and form step, as shown in Figure 4;
Silicon epitaxy step, the recess that is used between sidewall spacers 61 and 62 is filled silicon; For example, can carry out silicon epitaxy step by selective epitaxial;
Sidewall spacers is removed step, is used for removing sidewall spacers 61 and 62, thereby forms silicon protuberance 32 at floating gate layer 3, as shown in Figure 6; Preferably, after removing sidewall spacers 61 and 62, can also adopt isotropic etching that silicon protuberance 32 is carried out the bight sphering and process.
After this, can carry out the formation of follow-up normal control gate oxide level and control grid layer.
Like this, in according to the raising flash memory of second embodiment of the invention, control in the method for grid to the floating boom coupling coefficient, because increased the real surface of floating gate layer by the silicon protuberance on the floating gate layer long-pending, namely increased the coupling capacitance between control gate and floating boom, so improved the control grid to the floating boom coupling coefficient, and whole step can be integrated in the manufacturing process of stacking gate flash memory, can not increase new mask.
In addition, need to prove, unless stated otherwise or point out, otherwise the term in the specification " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing specification, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that, although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. one kind is improved in the flash memory control grid to the method for floating boom coupling coefficient, it is characterized in that comprising:
Floating gate layer forms step, be used for forming in the active area both sides of silicon chip the shallow trench isolation that is higher than surfaces of active regions from, and on surfaces of active regions, form successively gate oxide level and floating gate layer;
Extra play forms step, is used on the floating gate layer surface and shallow trench insulation surfaces formation extra play;
Sidewall spacers forms step, is used for the etching extra play, thus shallow trench isolation from sidewall form sidewall spacers;
The floating gate layer etch step is used for utilizing sidewall spacers that floating gate layer is carried out etching, thereby forms groove in floating gate layer;
Sidewall spacers is removed step, is used for removing sidewall spacers.
2. the control grid is characterized in that the method for floating boom coupling coefficient in the raising flash memory according to claim 1, and extra play is the oxide skin(coating) that forms by the CVD deposition.
3. the control grid is characterized in that the method for floating boom coupling coefficient in the raising flash memory according to claim 1 and 2, carries out sidewall spacers by dry etching and forms step.
4. control grid in the raising flash memory according to claim 1 and 2 to the method for floating boom coupling coefficient, it is characterized in that, remove in the step at sidewall spacers, after removing sidewall spacers, utilize isotropic etching that the groove in the floating gate layer is carried out the bight sphering and process.
5. one kind is improved in the flash memory control grid to the method for floating boom coupling coefficient, it is characterized in that comprising:
Floating gate layer forms step, be used for forming in the active area both sides of silicon chip the shallow trench isolation that is higher than surfaces of active regions from, and on surfaces of active regions, form successively gate oxide level and floating gate layer;
Extra play forms step, is used on the floating gate layer surface and shallow trench insulation surfaces formation extra play;
Sidewall spacers forms step, is used for the etching extra play, thus shallow trench isolation from sidewall form sidewall spacers;
Silicon epitaxy step, the recess that is used between sidewall spacers is filled silicon;
Sidewall spacers is removed step, is used for removing sidewall spacers, thereby forms the silicon protuberance at floating gate layer.
6. the control grid is characterized in that the method for floating boom coupling coefficient in the raising flash memory according to claim 5, and extra play is the oxide skin(coating) that forms by the CVD deposition.
7. the control grid is characterized in that the method for floating boom coupling coefficient according to claim 6 or in the 7 described raising flash memories, carries out silicon epitaxy step by selective epitaxial.
According to claim 6 or in the 7 described raising flash memories control grid to the method for floating boom coupling coefficient, it is characterized in that, remove in the step at sidewall spacers, after removing sidewall spacers, utilize isotropic etching that the silicon protuberance is carried out the bight sphering and process.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104637816A (en) * | 2013-11-11 | 2015-05-20 | 中芯国际集成电路制造(上海)有限公司 | Flash memory unit and production method thereof |
| CN112038344A (en) * | 2019-06-04 | 2020-12-04 | 联华电子股份有限公司 | Method for manufacturing floating gate memory element |
-
2012
- 2012-12-26 CN CN 201210576924 patent/CN103021957A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104637816A (en) * | 2013-11-11 | 2015-05-20 | 中芯国际集成电路制造(上海)有限公司 | Flash memory unit and production method thereof |
| CN104637816B (en) * | 2013-11-11 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | Flash memory cell and preparation method thereof |
| CN112038344A (en) * | 2019-06-04 | 2020-12-04 | 联华电子股份有限公司 | Method for manufacturing floating gate memory element |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140506 |
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Effective date of registration: 20140506 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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