CN103903969A - Floating gate preparation method - Google Patents
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- 238000007667 floating Methods 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000001039 wet etching Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000001312 dry etching Methods 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 15
- 230000008878 coupling Effects 0.000 claims abstract description 13
- 238000010168 coupling process Methods 0.000 claims abstract description 13
- 238000005859 coupling reaction Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000006396 nitration reaction Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 14
- 238000000151 deposition Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000002210 silicon-based material Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000011049 filling Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 230000001808 coupling effect Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 3
- 239000000428 dust Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000005470 impregnation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000003016 phosphoric acids Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Power Engineering (AREA)
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- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a floating gate preparation method. The method comprises steps: S1, a shallow trench isolation structure whose upper surface is higher than the first height H1 of the upper surface of a semiconductor substrate is formed on a semiconductor substrate; S2, an active region is formed on the semiconductor substrate through ion implantation; S3, a tunnel oxide layer is formed on the semiconductor substrate; S4, a floating gate material layer is deposited on the tunnel oxide layer; S5, the floating gate material layer is flattened to enable the upper surface of the shallow trench isolation structure to be exposed; and S6, part of the shallow trench isolation structure is removed by etching to form the floating gate. S6 further comprises steps of adopting wet etching to remove the shallow trench isolation structure with a second height H2 to enable coupling efficiency between the floating gates and control gates formed subsequently to be high, and adopting dry etching to remove the shallow trench isolation structure with a third height H3 to form the floating gates. When the technical scheme of the invention is applied, the coupling efficiency between the floating gate and control gates formed subsequently is high, and the risk of short circuit between the active region and the control gates can be avoided.
Description
Technical field
The present invention relates to integrated circuit (IC)-components manufacturing technology field, in particular to a kind of preparation method of floating boom.
Background technology
In recent years, the application that high density flash memory is gone up has in a lot of fields received very large concern, because manufacturing cost can be significantly lowered in dwindling of memory cell size.
At present, the floating boom of integrated circuit (IC)-components is formed with several different methods.Wherein, a kind of typical floating boom preparation method is as follows: 1) providing Semiconductor substrate, for example silicon wafer, silicon-on-insulator or epitaxial silicon chip; 2) use high-density plasma process deposits pad silicon oxide layer and silicon nitride layer, etching forms trench area; Filling groove district on silicon nitride layer surface; 3) use CMP (Chemical Mechanical Polishing) process planarization by the silicon oxide layer of high-density plasma process deposits, form trench area isolation structure and expose silicon nitride layer; 4) optionally remove silicon nitride layer by wet-etching technology, form from bottom, trench area and extend to fleet plough groove isolation structure more than pad oxide skin(coating); 5) remove a part that pads the silicon oxide layer that passes through high-density plasma process deposits in oxide skin(coating) and trench area; 6) use photoresist as mask, form source-drain electrode and the channel region in Semiconductor substrate by Implantation; 7) form tunnel oxide; 8) deposit spathic silicon material; 9) deposit cover oxide material; 10) planarization polycrystalline silicon material, the top of exposing fleet plough groove isolation structure; 11) use HF impregnation technology to remove a part for the silicon oxide layer that passes through high-density plasma process deposits in trench area, form floating boom.
In above-mentioned steps 11) in what remove that the part of the silicon oxide layer that passes through high-density plasma process deposits in trench area adopts conventionally is wet etching, this is because wet etching is isotropic etching, the area of ONO layer (silica-silicon-nitride and silicon oxide layer) the parcel floating boom forming is afterwards larger, makes the coupling efficiency between floating boom and the control gate of follow-up formation higher.But there is following technical problem in it: 1), if the process of wet etching is not controlled well, will be etched directly into active area, cause short circuit between active area and the control gate of follow-up formation; 2), after wet etching, the coupling effect between floating boom and floating boom is larger, affects performance of semiconductor device.If but adopt dry etching (anisotropic etching), although do not have the risk of short circuit between source region and the control gate of follow-up formation, the coupling effect between floating boom and floating boom can increase and floating boom and the control gate of follow-up formation between coupling efficiency also less; And the noticeable electrical thickness reduction that also has dry etching can make ONO layer.So current above-mentioned steps urgently to be resolved hurrily 11) in etching exist above-mentioned technical problem.
Summary of the invention
The present invention aims to provide a kind of preparation method of floating boom, to solve the less technical problem of coupling efficiency between risk or floating boom and the control gate of follow-up formation of short circuit between the active area that exists in part silicon oxide layer removal process in trench area in prior art and control gate.
To achieve these goals, according to an aspect of the present invention, provide a kind of preparation method of floating boom.This preparation method comprises the following steps: S1, in Semiconductor substrate, form fleet plough groove isolation structure, and the upper surface of fleet plough groove isolation structure is above Semiconductor substrate upper surface the first height H 1; S2 is formed with source region in Semiconductor substrate by Implantation; S3 forms tunnel oxide in Semiconductor substrate; S4, in tunnel oxide, deposition forms floating boom material layer; S5, planarization floating boom material layer exposes the upper surface of fleet plough groove isolation structure; And S6, etching is removed part fleet plough groove isolation structure, forms floating boom; Step S6 comprises: adopt wet etching to remove the fleet plough groove isolation structure of the second height H 2, make between floating boom and the control gate of follow-up formation coupling efficiency higher; Then adopt dry etching to remove the fleet plough groove isolation structure of third high degree H3, form floating boom, wherein, H2+H3≤H1.
Further, the first height H 1 is 600 ~ 700 dusts.
Further, the second height H 2 is 250 ~ 400 dusts.
Further, the wet etching in step S6 comprises that the etching solution that employing contains hydrofluoric acid carries out etching.
Further, the dry etching in step S6 comprises and carries out etching using carbon tetrafluoride as presoma.
Further, step S1 comprises: in Semiconductor substrate, deposition forms pad oxide skin(coating) and nitration case; Etching forms trench area, and deposition forms silicon oxide layer filling groove district to nitration case; Planarization silicon oxide layer is to nitration case; Etching is removed nitration case and pad oxide, obtains fleet plough groove isolation structure.
Further, the material of Semiconductor substrate is silicon wafer, silicon-on-insulator or epitaxial silicon chip.
Further, silicon oxide layer forms by high-density plasma process deposits.
Further, after step S6, further comprise: on floating boom, form dielectric layer, dielectric layer is silica-silicon-nitride and silicon oxide layer.
Further, the thickness of dielectric layer is 140 ± 3 dusts.
Apply technical scheme of the present invention, in the time that etching is removed part fleet plough groove isolation structure, first adopt wet etching to remove the fleet plough groove isolation structure of first degree of depth, then adopt dry etching to remove the described fleet plough groove isolation structure of second degree of depth, form floating boom.So just overcome the shortcoming with dry etching or private wet etching separately simultaneously, also have both its both advantage, this is because first adopt wet etching, and wet etching is isotropic etching, make the area of ONO layer (silica-silicon-nitride and silicon oxide layer) parcel floating boom larger, thereby make the coupling efficiency between floating boom and the control gate of follow-up formation higher; Then adopt dry etching, avoided the risk of short circuit between active area and control gate.
Accompanying drawing explanation
The Figure of description that forms the application's a part is used to provide a further understanding of the present invention, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 shows the structural representation of the semiconductor device forming to S5 according to the step S1 of the embodiment of the present invention;
Fig. 2 shows according to the structural representation of the semiconductor device forming after the wet etching of the embodiment of the present invention; And
Fig. 3 shows according to the floating gate structure schematic diagram forming after the dry etching of the embodiment of the present invention.
Embodiment
It should be noted that, in the situation that not conflicting, the feature in embodiment and embodiment in the application can combine mutually.Describe below with reference to the accompanying drawings and in conjunction with the embodiments the present invention in detail.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " above " etc., be used for describing as the spatial relation of a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in using or operating except the described in the drawings orientation of device.For example, if the device in accompanying drawing is squeezed, be described as " other devices or structure above " or " other devices or structure on " device after will be positioned as " other devices or construct below " or " other devices or construct under ".Thereby exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or in other orientation), and the space relative descriptors that used is here made to respective explanations.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, provide these embodiment be for make of the present invention disclose thorough and complete, and the design of these exemplary embodiments is fully conveyed to those of ordinary skills, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and used identical Reference numeral to represent identical device, thereby will omit description of them.
A kind of typical execution mode according to the present invention, provides a kind of preparation method of floating boom.As shown in Figures 1 to 3, the method comprises the following steps: S1, in Semiconductor substrate 10, form fleet plough groove isolation structure 20, and the upper surface of fleet plough groove isolation structure 20 is above Semiconductor substrate 10 upper surface the first height H 1; S2 is formed with source region by Implantation in Semiconductor substrate 10; S3 forms tunnel oxide 30 in Semiconductor substrate 10; S4, in tunnel oxide 30, deposition forms floating boom material layer; S5, planarization floating boom material layer exposes the upper surface of fleet plough groove isolation structure 20; And S6, etching is removed part fleet plough groove isolation structure 20, forms floating boom 40; Step S6 comprises: adopt wet etching to remove the fleet plough groove isolation structure 20 of the second height H 2, make between floating boom 40 and the control gate of follow-up formation coupling efficiency higher; Then adopt dry etching to remove the fleet plough groove isolation structure 20 of third high degree H3, form floating boom 40, wherein, H2+H3≤H1.
Apply technical scheme of the present invention, in the time that etching is removed part fleet plough groove isolation structure 20, first adopt wet etching to remove the fleet plough groove isolation structure 20 of the first height H 1, then adopt dry etching to remove the described fleet plough groove isolation structure 20 of the second height H 2, form floating boom 40.So just overcome the shortcoming with dry etching or private wet etching separately simultaneously, also have both its both advantage, this is because first adopt wet etching, and wet etching is isotropic etching, make the area of ONO layer (silica-silicon-nitride and silicon oxide layer) parcel floating boom 40 larger, thereby make the coupling efficiency between floating boom 40 and the control gate of follow-up formation higher; Then adopt dry etching, avoided the risk of short circuit between active area and control gate.
The one typical embodiment according to the present invention, the first height H 1 is 600 ~ 700 dusts, the making of this device that is highly applicable to becoming more meticulous.
Technical scheme of the present invention is suitable in 65nm technology, because it is very little to make window in 65nm technology, thickness after floating boom cmp error in a wafer is very large, if adopt fixing numerical value to do when etching, can bring two problems: if floating boom is heavy too thin, after etching, the minimum point of trench area part can be also lower than active area, and the consequence of bringing is like this that electric leakage possibility is very large, and the ability of write-in program reduces a lot; If floating boom is too thick conversely speaking,, the interference between floating boom can strengthen.So doing before wet etching and will first doing an assessment to floating boom thickness, then adjust and carve the wet etching degree of depth according to actual floating boom thickness, to form high-quality semiconductor device.Preferably, the second height H 2 be 250 ~ 400 dusts (according to floating boom Height Adjustment, each etching (step) is 50 dusts, enough guarantees that the coupling efficiency between floating boom 40 and the control gate of follow-up formation is higher, and guarantee H2+H3≤.
Preferably, the wet etching in step S6 comprises that the etching solution that employing contains hydrofluoric acid carries out etching, controls the degree of depth under etching by controlling the reaction time.
Preferably, the dry etching in step S6 carries out etching using carbon tetrafluoride as presoma, etching 300-350 dust.
Preferably, after step S6, further comprise: on floating boom, form dielectric layer, dielectric layer is silica-silicon-nitride and silicon oxide (ONO) layer.Same ONO physical thickness, with the electrical thickness of ONO layer forming after wet etching be 140 ~ 150 dusts, than add dry etching thickness (120-130 dust) thick 13.80% out by wet method.Through assessment, in order to guarantee the performance of final products, we need to be the physical thickness of ONO add the thickness of 10 left and right dusts during than wet etching again, so preferably, guarantee that the electrical thickness of dielectric layer is 140 ± 3 dusts.
A kind of typical execution mode according to the present invention, step S1 comprises: in Semiconductor substrate 10, deposition forms pad oxide skin(coating) and nitration case; Etching forms trench area, and deposition forms silicon oxide layer filling groove district to nitration case; Planarization silicon oxide layer is to nitration case; Etching is removed nitration case and pad oxide, obtains fleet plough groove isolation structure 20.Adopt the part of the fleet plough groove isolation structure 20 forming in this way more than Semiconductor substrate 10 upper surfaces up-narrow and down-wide, like this in the time that follow-up dry etching is removed second degree of depth, as shown in Figure 3, have fraction remnants 31, can make the coupling effect between floating boom 40 and floating boom 40 reduce, improve the performance of semiconductor device.
The typical execution mode of one according to the present invention, the formation of floating boom 40 specifically comprises the steps:
1) provide Semiconductor substrate 10, such as silicon wafer, silicon-on-insulator or epitaxial silicon chip etc.; Form the pad oxide that covers Semiconductor substrate 10.This pad oxide can be the oxide of at high temperature producing by boiler tube, can also use chemical vapor deposition method or other applicable technique to form.(the present thickness of silicon nitride layer is 1300 dusts on pad oxide, to form silicon nitride layer, because floating boom height is determined by silicon nitride layer thickness, so high silicon nitride can bring high floating boom, and high floating boom brings the coupling effect of better control gate to floating boom, improve device performance.So now meeting on the basis of shallow trench isolation layer filling capacity, silicon nitride layer can be set to the thickness of 1400-1450 dust), this silicon nitride layer can utilize dichlorosilane and NH
3chemical vapor deposition method as presoma forms, and other appropriate method that also can apply in addition plasma activated chemical vapour deposition form.
2) use photoetching and etching technics to form trench area, wherein, etching technics can be wet etching, can be also dry etching.Then use high-density plasma process deposits to form silicon oxide layer, filling groove district on silicon nitride layer surface.In a preferred embodiment, this silicon oxide layer is in ar gas environment, to utilize silane and oxygen as presoma, uses high-density plasma (HDP) deposition to form.
3) use CMP (Chemical Mechanical Polishing) process planarization by the silicon oxide layer of high-density plasma process deposits, form trench area isolation structure, and this trench area isolation structure exceeds substrate top surface the first height, be equivalent to the height of floating boom 40.CMP (Chemical Mechanical Polishing) process in this step also can adopt other suitable flatening process to replace, such as anti-etching, reflux or its combination etc.In specific embodiment, this first can be highly 600 ~ 700 dusts, certainly, according to actual needs, the height that these highly can be different according to the different designs of semiconductor device.
4) optionally remove silicon nitride layer by wet-etching technology, in specific embodiment, the wet-etching technology that can use phosphoric acid class optionally place to go silicon nitride layer (because when silicon nitride layer is removed, the hydrofluoric acid of dilution also has certain etch capabilities to silica, we find that suitably lengthening the time of making can increase floating boom width, and the coupling ability of grid to floating boom tightens control).Also can use other etch process herein, for example reactive ion etching (RIE).
5) remove a part that pads the silicon oxide layer that passes through high-density plasma process deposits in oxide skin(coating) and trench area.Wherein pad the wet method selective etch that oxide skin(coating) can use hydrofluoric acid class, can certainly adopt reactive ion etching (RIE).
6) use photoresist as mask, form the active area in Semiconductor substrate 10 by Implantation.
7) form tunnel oxide.Tunnel oxide can use tetraethyl orthosilicate to form as the chemical gaseous phase deposition method of presoma, also can use the technique of other applicable silica deposition to form, and for example, forms as the chemical vapor deposition method of presoma using dichlorosilane and oxygen.
8) deposit spathic silicon material (floating boom material layer);
9) deposit cover oxide material, this lid oxide material can be that dichlorosilane and oxygen form as the chemical vapor deposition method of presoma.Lid oxide material is for protecting polycrystalline silicon material in CMP (Chemical Mechanical Polishing) process, and he can prevent polycrystalline silicon material layering, can also protect large stretch of polysilicon region and reduce polysilicon depression.
10) planarization polycrystalline silicon material, the top of exposing fleet plough groove isolation structure 20.
11) adopt wet etching to remove the fleet plough groove isolation structure 20 of first degree of depth, make between floating boom 40 and the control gate of follow-up formation coupling efficiency higher; Then adopt dry etching to remove the described fleet plough groove isolation structure 20 of second degree of depth, form floating boom 40.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a preparation method for floating boom, comprises the following steps:
S1, at Semiconductor substrate (10) upper formation fleet plough groove isolation structure (20), and the upper surface of described fleet plough groove isolation structure (20) is above described Semiconductor substrate (10) upper surface the first height H 1;
S2 is formed with source region by Implantation in described Semiconductor substrate (10);
S3, in the upper tunnel oxide (30) that forms of described Semiconductor substrate (10);
S4, forms floating boom material layer in the upper deposition of described tunnel oxide (30);
S5, floating boom material layer exposes the upper surface of described fleet plough groove isolation structure (20) described in planarization; And
S6, etching is removed the described fleet plough groove isolation structure of part (20), forms described floating boom (40); It is characterized in that, described step S6 comprises:
Adopt wet etching to remove the described fleet plough groove isolation structure (20) of the second height H 2, make between described floating boom (40) and the control gate of follow-up formation coupling efficiency higher;
Then adopt dry etching to remove the described fleet plough groove isolation structure (20) of third high degree H3, form described floating boom (40), wherein, H2+H3≤H1.
2. preparation method according to claim 1, is characterized in that, described the first height H 1 is 600 ~ 700 dusts.
3. preparation method according to claim 1, is characterized in that, described the second height H 2 is 250 ~ 400 dusts.
4. preparation method according to claim 1, is characterized in that, the described wet etching in described step S6 comprises that the etching solution that employing contains hydrofluoric acid carries out etching.
5. preparation method according to claim 2, is characterized in that, the described dry etching in described step S6 comprises and carries out etching using carbon tetrafluoride as presoma.
6. preparation method according to claim 1, is characterized in that, described step S1 comprises:
Form pad oxide skin(coating) and nitration case in the upper deposition of described Semiconductor substrate (10);
Etching forms trench area, and deposition formation silicon oxide layer is filled described trench area to described nitration case;
Described in planarization, silicon oxide layer is to described nitration case;
Etching is removed described nitration case and described pad oxide, obtains described fleet plough groove isolation structure (20).
7. preparation method according to claim 6, is characterized in that, the material of described Semiconductor substrate (10) is silicon wafer, silicon-on-insulator or epitaxial silicon chip.
8. preparation method according to claim 6, is characterized in that, described silicon oxide layer forms by high-density plasma process deposits.
9. preparation method according to claim 2, is characterized in that, further comprises: on described floating boom, form dielectric layer, described dielectric layer is silica-silicon-nitride and silicon oxide layer after described step S6.
10. preparation method according to claim 9, is characterized in that, the thickness of described dielectric layer is 140 ± 3 dusts.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105789035A (en) * | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Floating gate and manufacturing method therefor |
| CN105826326A (en) * | 2016-03-22 | 2016-08-03 | 上海华力微电子有限公司 | Cell recess oxide etching method of improving deep-submicron flash memory device coupling rate |
| CN112038344A (en) * | 2019-06-04 | 2020-12-04 | 联华电子股份有限公司 | Method for manufacturing floating gate memory element |
| CN113611654A (en) * | 2020-11-03 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Manufacturing method for reducing height difference of shallow trench isolation |
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| CN105789035A (en) * | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Floating gate and manufacturing method therefor |
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| CN105826326B (en) * | 2016-03-22 | 2018-11-09 | 上海华力微电子有限公司 | A kind of lithographic method for the trench oxide improving deep-submicron flush memory device coupling efficiency |
| CN112038344A (en) * | 2019-06-04 | 2020-12-04 | 联华电子股份有限公司 | Method for manufacturing floating gate memory element |
| CN113611654A (en) * | 2020-11-03 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Manufacturing method for reducing height difference of shallow trench isolation |
| CN113611654B (en) * | 2020-11-03 | 2022-04-19 | 联芯集成电路制造(厦门)有限公司 | Manufacturing method for reducing height difference of shallow trench isolation |
| US11387150B2 (en) | 2020-11-03 | 2022-07-12 | United Semiconductor (Xiamen) Co., Ltd. | Fabricating method of decreasing height difference of STI |
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