JP2005203801A - Improved method for programming electron on floating gate of nonvolatile memory cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for improving the programming efficiency of a nonvolatile memory cell which has a floating gate for storing electrons. <P>SOLUTION: The method for programming the cell includes a step for forming an inversion layer in a second part of a channel. An electron flow is generated in a drain region which adjoins the inversion layer, and the electron flow reaches a pinch-off point passing through the inversion layer. The electrons are accelerated through a depletion layer by a magnetic line of force from the floating gate with little dispersion or without the dispersion. Thereby, the electrons are accelerated through an insulator making the floating gate separate from a substrate, and the electrons are injected into the floating gate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present application relates to a self-aligned method of forming a semiconductor memory array of floating gate memory cells. The invention also relates to a semiconductor memory array of floating gate memory cells of the type described above.

  This application is a continuation-in-part of copending application No. 10 / 358,623 filed on Feb. 4, 2003, which is a US Provisional Patent Application No. 60/370 filed Apr. 5, 2002. 888, “High Coupling Non-Volatile Trench Memory Cell”; US Provisional Patent Application No. 60 / 393,696, filed July 2, 2002, “Non-Volatile Trench Memory Cell and Method of Making Same”; US Provisional Patent Application No. 60 / 398,146, filed Jul. 23, 2000, claims the benefit of “Non-Volatile Memory Trench Cell With Buried Floating Gate”, all of which are incorporated herein by reference.

  Nonvolatile semiconductor memory cells that use a floating gate to store charge thereon, and memory arrays of such nonvolatile memory cells formed on a semiconductor substrate are well known in the art. Usually, such a floating gate memory cell is a split gate type or a stacked gate type.

  One of the problems facing the manufacturability of semiconductor floating gate memory cells has been the alignment of various components such as the source, drain, control gate, and floating gate. The need for precise alignment has become more important as design rules for semiconductor processing integration have been relaxed and the smallest lithographic features have become smaller. The alignment of each part also determines the production output of semiconductor products.

  Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more processes involving one or more materials so that the features are automatically aligned with each other in a stepwise processing process. Accordingly, the present invention uses this self-aligned technique to realize the manufacture of a floating gate memory cell type semiconductor memory array.

  In order to maximize the number of memory cells on a single wafer, there is always a need to reduce the size of the memory cell array. It is well known that the size of the memory cell array can be reduced by forming memory cells in pairs, sharing one source region for each pair, and sharing a common drain region between adjacent pairs of cells. . However, a large area in the array is usually devoted to bit line connections to the drain region. Bit line areas are often occupied by contact holes between memory cell pairs and contacts to word line spacing, which vary greatly due to lithographic generation, contact alignment, and contact integrity. Furthermore, a very large space is reserved for the word line transistors, and the size of the word line transistors is set by lithographic generation and junction scaling.

  Conventionally, the floating gate has been formed with a sharp edge facing the control gate to enhance the Fowler-Nordheim tunnel, which is used to remove electrons from the floating gate during an erase operation. Sharp edges are typically formed by non-uniform oxidation or partial etching on the top surface of the floating gate poly. However, as the size of the floating gate decreases, it becomes difficult to form this sharp edge in this manner.

  There is also a need to improve the programming efficiency of memory cell arrays. FIG. 10A shows a partial cross-sectional view of a prior art flash memory cell 200 (disclosed in US Pat. No. 5,029,130, the entire disclosure of which is incorporated herein by reference). During programming, region 210 is maintained at or near ground voltage. The region 220 is supplied with a high voltage of about +10 volts. A depletion region 250 is then formed around region 220. Further, due to the high capacitive coupling between region 220 and floating gate 230, floating gate 230 "sees" a voltage of about +7 volts. A voltage slightly positive than the threshold voltage, for example, about +1.5 volts, is applied to the control gate 240. Since the voltage of the control gate 240 is lower than the voltage of the floating gate 230, magnetic lines of force are generated from the floating gate 230 to the substrate 260, and then the magnetic lines of force reach the control gate 240. When a positive voltage is applied to the control gate 240, the portion of the channel region below the control gate 240 is “turned on”, ie, the inversion layer 280 is formed. Electrons flow from the first region 210 near the surface of the substrate 260 of the inversion layer 280 until the pinch-off point 295 is reached. At this point 295, the electrons are accelerated by the lines of magnetic force. However, in order to “inject” electrons into the floating gate 230, electrons from the first region 210 collide (scatter) with either impurities or lattice defects in the substrate 260, resulting in a vertical momentum. Must be generated. Furthermore, only electrons having a vertical velocity that can overcome the energy barrier between the oxide and silicon will be injected into the floating gate 230. As a result, only a very small proportion (about 1/1000) of electrons from the electron current in the inversion layer 280 can have sufficient energy to be injected into the floating gate 230. Thus, in this programming mechanism, scattering is an essential element of the programming mechanism.

  FIG. 10B shows an example of another prior art programming mechanism incorporating an EPROM cell 300. Similar to the description of the flash cell 200 shown in FIG. 10A, the first region 210 is maintained at a ground voltage or a substantially ground voltage during programming. The region 220 is supplied with a high voltage of about +12 volts. Next, a depletion region 250 is formed around the second region 220. A high voltage on the order of +12 volts is also applied to the control gate 240, so that the floating gate 230 "sees" +7 volts. Since the voltage of the floating gate 230 is lower than the voltage of the depletion region 250, lines of magnetic force are generated from the depletion region 250 to the floating gate 230. Furthermore, when the floating gate “sees” about +7 volts, the portion of the channel region below the floating gate 230 is “turned on”, ie, the inversion layer 280 is formed. The electrons flow out of the first region 210 near the surface of the substrate 260 in the inversion layer 280 until the pinch-off point 295 is reached. At this point 295, the electrons are accelerated by the lines of magnetic force. However, the electrons are actually rebounded from the surface of the substrate 260 by the magnetic field lines. As a result, the electrons move “downward”. In order to “inject” electrons into the floating gate 230, the electrons from the first region 210 must collide with either impurities or lattice defects in the substrate 260 to generate a vertical momentum component. Only an electron with an initial vertical velocity that can overcome the repulsive magnetic field in the substrate, 2) the energy barrier at the silicon-oxide interface, and 3) the repulsive magnetic field in the oxide, and then the vertical upward velocity. Will be injected into the floating gate 230. As a result, since the electrons are actually moving “downward” at the beginning, a proportion of electrons smaller than the proportion of electrons in the flash cell 200 (one hundred thousandth of the electron current in the inversion layer 280 or Only 1 in million) will have enough energy to be injected into the floating gate 230. Therefore, in this programming mechanism as well, scattering is an indispensable component of the programming mechanism.

  Accordingly, one object of the present invention is to create a method for improving the programming efficiency of a non-volatile memory cell having a floating gate for storing electrons.

  It is known that memory cell elements are formed on non-planar portions of a substrate. For example, US Pat. No. 5,780,341 (Ogura) discloses a number of memory device configurations in which stepped channels are formed on the substrate surface. The purpose of the stepped channel is to inject hot electrons more efficiently into the floating gate, but the memory device design described above requires the size and formation of the memory cell elements as well as efficient and reliable operation. It is still insufficient in that it is difficult to optimize the required operating parameters.

  There is a need for a non-volatile floating gate memory cell array that has greatly reduced cell size while enhancing programming efficiency.

US patent application Ser. No. 10 / 358,623 US Provisional Patent Application No. 60 / 370,888 US Provisional Patent Application No. 60 / 393,696 US Provisional Patent Application No. 60 / 398,146 US Pat. No. 5,029,130 US Pat. No. 5,780,341 US Pat. No. 5,572,054

  In the present invention, the programming efficiency is achieved by using memory cells in a substrate of a first conductivity type semiconductor material and having first and second regions spaced apart in the second conductivity type substrate. It is caused by doing. A non-coplanar channel region is formed between the first and second regions in the substrate. In the non-coplanar channel region, there are two parts, a first part and a second part. The conductive control gate has a portion adjacent to and insulated from the first portion of the channel region to provide an inversion layer there. The floating gate is provided to create a depletion region adjacent to the second portion of the channel region and insulated from it by an insulator, and having a magnetic field line toward the floating gate when a positive voltage is connected to the floating gate. Has a part. The first region is adjacent to the inversion layer and the method of programming the device includes creating the inversion layer. An electron flow is generated in the first region and the electrons traverse this inversion layer. The electrons are then accelerated by magnetic field lines in the depletion region, with little or no scattering, and the electrons are accelerated through the insulator and injected into the floating gate.

  The method of the present invention is shown in FIGS. 1A to 1F, 2A to 2Q (showing the processing steps for fabricating the memory cell array of the present invention), and FIGS. 3A to 3Q (for fabricating the peripheral region of the semiconductor structure). Shows processing steps). The method begins with a semiconductor substrate 10, which is preferably P-type and is well known in the art. The layer thicknesses described below will vary depending on the design rules and processing technology generations. What is described here is for 0.10 micron processing. However, as will be appreciated by those skilled in the art, the present invention is not limited to any particular processing technology generation, nor is it limited to any particular value of any of the processing parameters described below.

Formation of Isolation Regions FIGS. 1A-1F illustrate the well-known STI method of forming isolation regions on a substrate. FIG. 1A shows a top view of a semiconductor substrate 10 (or semiconductor well), preferably P-type, well known in the art. Layers 12 and 14 of first and second materials are formed (eg, grown or deposited) on the substrate. For example, the first layer 12 is silicon dioxide (hereinafter referred to as oxide), which is about 50 mm thick by a well-known technique such as oxidation or oxide deposition (eg, chemical vapor deposition or CVD) on the substrate 10. To 150cm. Nitrogen doped oxides or other insulating dielectrics may be used. The second layer 14 is made of, for example, silicon nitride (hereinafter referred to as nitride), and is formed on the oxide layer 12 with a thickness of about 1000 to 5000 mm, preferably by CVD or PECVD. FIG. 1B shows a cross-sectional view of the resulting structure.

  Once the first and second layers 12/14 are formed, a suitable photoresist material 16 is applied over the nitride layer 14 and a certain area (in the Y or column direction) as shown in FIG. 1C. A masking step is performed to selectively remove the photoresist material from the stripe 18). Where the photoresist material 16 has been removed, the exposed nitride layer 14 and oxide layer 12 are removed using standard etching techniques (eg, anisotropic nitride and oxide / dielectric etch processes) Etching is removed in the form of stripes 18 to form trenches 20 in the structure. The distance W between adjacent stripes 18 can be as small as the minimum lithographic shaping of the processing used. A silicon etch process is then used to dig the trench 20 into the silicon substrate 10, as shown in FIG. 1D (eg, from about 500 to a few microns deep). Where the photoresist 16 is not removed, the nitride layer 14 and the oxide layer 12 are maintained. The processed structure shown in FIG. 1D has a structure in which the active region 22 and the isolation region 24 intersect at this point.

  The structure is further processed and the remaining photoresist 16 is removed. Thereafter, an insulating material such as silicon dioxide is formed in the trench 20 by depositing a thick oxide layer, followed by a chemical mechanical polishing or CMP etch (using the nitride layer 14 as an etch stop). As shown in 1E, oxide layers other than the oxide block 26 in the trench 20 are removed. Thereafter, the remaining nitride and oxide layers 14/12 are removed using a nitride / oxide etch process, resulting in an STI oxide block extending along isolation region 24, as shown in FIG. 1F. 26 is left.

  The STI isolation method is a suitable method for forming the isolation region 24. However, well-known LOCOS isolation methods (eg, recess LOCOS, polybuffered LOCOS, etc.) may be used instead, in which case the trench 20 does not extend into the substrate and the insulating material is on the substrate surface. It is formed in the stripe region 18. 1A to 1F show the memory cell array region of the substrate, and a column of memory cells is formed in the active region 22 separated by the isolation region 24. It should be noted that the substrate 10 also includes at least one peripheral region 28 in which a control circuit to be used for operating the memory cells formed in the memory cell array region is formed. Preferably, isolation blocks 26 are also formed in the peripheral region 28 during the same STI or LOCOS process described above.

Formation of Memory Cell The structure shown in FIG. 1F is further processed as follows. 2A to 2Q show sectional views of the structure of the active region 22 (along the line 2A-2A in FIGS. 1C and 1F) viewed from a direction orthogonal to the cross section of FIG. 1F, and FIGS. A sectional view of the structure of the peripheral region 28 is shown, and the next step in the processing of the present invention is performed simultaneously in both regions.

First, an insulating layer 30 (preferably an oxide or nitride doped oxide) is formed on the substrate 10 as shown in FIGS. 2A and 3A. The active region portion of the substrate 10 is doped at this point to allow the cell array portion of the memory device to be controlled more independently with respect to the peripheral region 28. Such doping is often referred to as V _t implantation or cell well injection, which is well known in the art. During this implantation, the peripheral region is protected with a photoresist layer deposited over the entire structure and removed only from the memory cell array region of the substrate.

  Next, a thick layer of hard mask material 32, such as nitride, is formed on oxide layer 30 (eg, up to a thickness of 3500 mm). Applying a photoresist (masking) material over the nitride layer 32 and then performing a masking process to remove the photoresist material from the selected parallel stripe regions, thereby providing a plurality of parallel first layers in the nitride layer 32. Two trenches 34 are formed. Using anisotropic nitride etching to remove the exposed portion of the nitride layer 32 in this stripe region leaves a second trench 34 that extends downward into the oxide layer 30 and exposes the oxide layer 30. After removing the photoresist, an exposed portion of the oxide layer 30 is removed using anisotropic oxide etching, and the second trench 34 is extended down to the substrate 10. The second trench 34 is then extended down into the substrate 10 in each active region 22 using a silicon anisotropic etching process (e.g., to a depth of about one feature, e.g., 0.15 um technology). (From about 500 mm to several microns). Alternatively, the photoresist may be removed after the trench 34 is formed into the substrate 10. The active / peripheral region 22/28 after processing is shown in FIGS. 2B / 3B.

  Next, a layer of insulating material 36 is formed along the exposed silicon in second trench 34 (desirably using thermal or CVD oxidation), which is the bottom and lower sidewalls of second trench 34. (For example, from 60 to 150 mm thick). Next, a thick polysilicon layer 38 (hereinafter poly) is formed covering the structure and filling the second trench 34. The poly layer 38 is doped (eg, n +) by ion implantation or in situ doped poly treatment. The active / peripheral region 22/28 after processing is shown in FIGS. 2C / 3C.

  Using a poly etch process (e.g., a CMP process using the nitride layer 32 as an etch stop), the poly layer is removed except for the block 40 of polysilicon 38, and that portion remains in the second trench. Left behind. A controlled poly etch is then used to reduce the height of the polyblock 40, with the top surface of the polyblock 40 being above the surface of the substrate and separated as shown in FIGS. 2D / 3D. It is below the upper surface of the STI block 26 in the region 24.

  Next, as shown in FIG. 2E, poly etching is optionally performed again to form an inclined portion 42 on the upper surface of the poly block 40 (adjacent to the side wall of the second trench). Next, thermal oxidation is performed to shape or make the tip of the inclined portion 42 stand out, and the exposed surface of the polyblock 40 is oxidized (the oxide layer 46 is formed thereon) as shown in FIG. 2F. Next, an oxide spacer 48 is formed along the side wall of the second trench 34. The formation of the spacer is well known in the art and involves depositing material over the contours of the structure, followed by an anisotropic etch process, thereby removing the material from the horizontal plane of the structure. On the other hand, the material remains largely intact on the longitudinally oriented surface of the structure (having a rounded top surface). Spacers 48 are formed by depositing an oxide (eg, 300 to 1000 inches thick) on the structure followed by an anisotropic oxide etch. The central portion of the oxide layer 46 of each second trench 34 is also removed by the oxide etching. The peripheral area 28 remains unaffected. The active / peripheral region 22/28 after processing is shown in FIGS. 2G / 3G.

  Next, an anisotropic poly etch is performed in combination with some oxide etch (an etch to adjust the height of the STI oxide along the trench 34), and the polyblock not protected by the oxide spacer 48 When the central portion of 40 is removed, a pair of opposing polo blocks 40a remain in each of the second trenches 34, as shown in FIG. 2H. Next, the insulating layer 50 is formed along the exposed side surface of the polyblock 40a inside the second trench 34 using deposition of an insulating layer and anisotropic etch back processing. The insulating material can be any insulating material (eg, ONO, ie oxide / nitride / oxide, or other high dielectric material). Desirably, the insulating material is oxide and the oxide deposition / etch process also increases the thickness of the oxide spacer 48, resulting in the bottom of each second trench 34 as shown in FIGS. 2I / 3I. The exposed portion of the oxide layer 36 is removed so that the substrate is exposed.

  Suitable ion implantation depends on whether the substrate is P-type or N-type, but includes arsenic, phosphorus, boron, and / or antimony (and possibly annealing), and this ion implantation is performed across the surface of the structure, A first (source) region 52 is formed at the bottom of the second trench 34 in the exposed substrate portion. The source region 52 is self-aligned with the second trench 34 and has a second conductivity type (eg, N-type) that is different from the first conductivity type (eg, P-type) of the substrate. The ions do not affect the nitride layer 32 at all. The active / peripheral region 22/28 after processing is shown in FIGS. 2J / 3J.

Using a poly deposition process and subsequent poly CMP etch (using nitride layer 32 as an etch stop), second trench 34 is filled with polyblock 54 as shown in FIG. 2K. Nitride etching is then performed to remove nitride 32 and expose the upper edge of polyblock 40a. A tunnel oxide layer 56 is then formed on the exposed upper edge of the polyblock 40a by one or both of thermal oxidation and oxide deposition. This oxide formation step forms an oxide layer 58 on the exposed upper surface of the polyblock 54 and possibly increases the thickness of the oxide layer 30 on the substrate 10. At this point, an optional V _t implant may be performed in the peripheral region 28 by masking the active region 22. The active / peripheral region 22/28 after processing is shown in FIGS. 2L / 3L.

  The oxide layer 30 acts as a gate oxide for both the memory cells in the active region and the control circuitry in the peripheral region. For each device, the maximum operating voltage is determined by the thickness of the gate oxide. Thus, if it is desired that some of the control circuits operate at a different voltage than the memory cells or other devices of the control circuit, the thickness of the gate oxide 32 is changed at this point during processing. By way of example and not limitation, a photoresist 60 is formed on the structure, and then a masking step is performed to selectively remove the photoresist portion in the peripheral region to expose portions of the oxide layer 30. The exposed portion of the oxide layer 30 is thinned (eg, using controlled etching) or desired thickness (eg, with oxide etching and oxide deposition), as shown in FIGS. 2M / 3M. The oxide layer 30a is replaced.

  After removal of the photoresist 60, a poly deposition process is used to form a poly layer 62 (eg, about 500 to 300 inches thick) on the structure. A photoresist deposition and masking step is then followed to form a block of photoresist 64 on the poly layer in the peripheral region 28, as shown in FIGS. 2N / 3N. An anisotropic poly etch is then used to remove the polyblock 66 under the photoresist block 64 (in the peripheral region 28) and the polyspacer 68 adjacent to the oxide spacer 48 (in the active region 22) to remove the polylayer. 62 is removed. Using appropriate ion implantation (and annealing), a second (drain) region 70 in the substrate active region and a source / drain region 72/74 in the substrate peripheral region 28 are formed for the devices in the region. The active / peripheral region 22/28 after processing is shown in FIGS. 2O / 3O.

  Then, after the photoresist block 64 is removed, an insulating spacer 76 is formed by insulating material deposition and anisotropic etching (eg, nitride or oxide) so as to strike the poly spacer 68, oxide spacer 48, and poly block 66. Is provided. A metal deposition process is then performed to deposit a metal such as tungsten, cobalt, titanium, nickel, platinum, or molybdenum on the active and peripheral regions 22/28. The structure is then annealed so that hot metal flows and penetrates into the exposed tops of the poly spacers 68 and poly blocks 66 to form a conductive layer of metallized polysilicon 78 (polycide) there. The metal deposited on the remaining structure is removed by a metal etching process. The active / peripheral region 22/28 after processing is shown in FIGS. 2P / 3P.

  Thereafter, an insulating material 80 such as BPSG or oxide is formed over the entire structure. A masking step is performed to define an etched area on the drain region 70/74. Insulative material 80 is selectively etched in the masked areas to create contact holes extending down to drain regions 70/74. The contact hole is then filled with a conductive metal (eg, tungsten) to form a metal contact 82 that is electrically connected to the drain region 70/74. By applying metal masking on the insulating material 80, a drain line contact 84/86 (eg, aluminum, copper, etc.) is added to each of the active and peripheral regions 22/28, and all contacts in each active region 22 are added. 82 (and thus all drain regions 70) are connected together, and a plurality of drain regions 74 in the peripheral region 28 are connected together. The final active region memory cell structure is shown in FIG. 2Q, and the final peripheral region control circuit structure is shown in FIG. 3Q.

  As shown in FIG. 2Q, in the processing of the present invention, a pair of mirror-shaped memory cells in which memory cells are formed on each side of the polyblock 54 is formed. For each memory cell, the first and second regions 52/70 respectively form a source region and a drain region (however, as will be appreciated by those skilled in the art, the source and drain may be switched during operation). The poly block 40a constitutes a floating gate, and the poly spacer 68 constitutes a control gate. A channel region 90 for each memory cell is defined in the surface portion of the substrate and exists between the source and drain 52/70. Each channel region 90 includes two portions joined at substantially right angles, the first (vertical) portion 92 extending along the vertical wall of the filled second trench 34 and the second (horizontal). The (direction) portion 94 extends between the sidewall of the filled second trench 34 and the drain region 70. Each pair of memory cells share a common source region 52 that is disposed below the filled second trench 34 and is in electrical contact with the polyblock 54. Similarly, each drain region 70 is shared between adjacent memory cells in separate mirror sets of memory cells.

  FIG. 4 shows a control gate 68 formed continuously as an interconnect between the bit line 84 and the drain region 70, as well as a control (word) line extending across both the active region and the isolation region 22/24. It is a top view of the structure after the process shown. The above process does not create a source region 52 that extends across the isolation region 24 (this is facilitated by deep implantation or by removing the STI insulating material from the isolation region portion of the second trench 34 prior to ion implantation. Can be done). However, the polyblock 54 (which is in electrical contact with the source region 52) is formed continuously across the isolation region to the adjacent active region, forming source lines, each source line being paired For each row of memory cells, all of the source regions 52 are electrically connected together.

  A floating gate 40a is disposed in the second trench 34, each floating gate facing and from one of the vertical portions 92 of the channel region, one of the source regions 52, and one of the polyblocks 54. Insulated. Each floating gate 40a includes an upper portion that extends above the substrate surface and faces one of the control gates 68 and terminates at an edge 96 that is insulated therefrom, thus providing an oxide layer. Route 56 is provided for the Fowler-Nordheim tunnel. The polyblocks 54 each extend along the floating gate 44a and are insulated (with the oxide layer 50) from them to enhance the voltage coupling therebetween. It is important that the vertical overlap between any control gates and any floating gates is at most partly, so that excessive capacitive coupling between them prevents the operation of the memory cells described below. There is nothing. This means that if there is any vertical overlap between the control gate and the floating gate, the control gate will not extend (horizontally) as long as it completely overlaps (vertically) the floating gate. ing.

Operation of Memory Cell The operation of the memory will now be described. The operation and operation theory of such a memory are also described in US Pat. No. 5,572,054, the disclosure of which includes the operation and operation theory of a nonvolatile memory cell having a floating gate and a control gate, floating This is incorporated herein by reference as a reference for the tunneling effect of the gate-to-control gate and the arrangement of the memory cells formed thereby.

  Initially, a ground potential is applied to both its source 52 and drain 70 to erase a selected memory cell in a given active region 22. A positive high voltage (eg, +7 to +15 volts) is applied to the control gate 68. The electrons of the floating gate 40a are induced by the Fowler-Nordheim tunneling mechanism and travel from the upper end of the floating gate 40a (mainly from the edge 96) through the oxide layer 56 to the control gate 68, so that the floating gate 40a is positive. Will be charged. The tunnel effect is enhanced by the sharp edges 96. Note that each control gate 68 extends across the active and isolation regions as a continuous control (word) line, so that one memory cell in each active region is simultaneously “erased”.

  When programming the selected memory cell, a low voltage (for example, 0.5 to 2.0 V) is applied to the drain region 70. A positive voltage level (approximately +0.2 to 1 volt above the drain node 70) close to the threshold voltage of the MOS structure is applied to its control gate 68. A positive high voltage (eg, about 5 to 10 volts) is applied to the source region 52. Since the floating gate 40 is highly capacitively coupled to the polyblock 54 which is at the same voltage potential as the source region 52, the floating gate 40 "sees" a voltage potential on the order of +4 to +8 volts. As a result, a deep depletion region 250 is formed in the substrate 10. Further, since the voltage of the floating gate 40 is higher than the voltage of the control gate 68, the magnetic field lines are radiated from the floating gate 40 to the control gate 68 as shown in FIG. 10C. Further, since a positive voltage is applied to the control gate 68, an inversion layer 280 is formed on the substrate 10. The inversion layer 280 is connected to the drain region 70. Then, a flow of program electrons (as is well known, a current flows in a direction opposite to the flow of electrons) is generated in the drain region 70. The electrons pass through the inversion layer 280 and reach the pinch-off point 295. The pinch-off point 295 is at or inside the depletion region 250, but at this pinch-off point 295, electrons are accelerated by the magnetic field lines from the floating gate 40. As can be seen from FIG. 10C, magnetic field lines 40 are generated from the floating gate 40 toward the control gate 68, so that electrons are simply accelerated in the same direction as the general direction of the magnetic field lines. Since electrons are accelerated to obtain energy, electrons having sufficient energy are injected into the floating gate 40 across the insulating layer 36. Thus, unlike prior art programming mechanisms, the electrons in the depletion region 250 do not require scattering to generate a momentum component in the overall direction of the floating gate 40. In fact, scattering is undesirable because it causes the electrons from the pinch-off point 295 to actually lose momentum and energy in the direction toward the floating gate 40. Thus, in the programming mechanism of the present invention, electrons in the depletion region are accelerated and injected into the floating gate 40 with little or no scattering.

  For memory cells that are not selected, a low or ground potential is applied to the source / drain regions 52/70 and control gates of the memory cell rows / columns that do not include the selected memory cell. Therefore, only the memory cells in the selected row and column are programmed.

  The injection of electrons into the floating gate 40a continues until the charge reduction of the floating gate 40a cannot maintain a high surface potential along the vertical channel region portion 92 for generating hot electrons. At this point, the electrons of the floating gate 40a, that is, negative charges, reduce the flow of electrons from the drain region 70 to the floating gate 40a.

  Finally, a ground potential is applied to the source region 52 in order to read the selected memory cell. A read voltage (eg, 0.5 to 2 volts) is applied to its drain region 70, and approximately 1 to 4 volts (depending on the power supply voltage of the device) is applied to the control gate 68. When the floating gate 40a is positively charged (ie, when the floating gate emits electrons), the vertical channel region portion 92 (which is directly adjacent to the floating gate 40a) is turned on. As control gate 68 rises to the read potential, horizontal channel region portion 94 (directly adjacent to control gate 68) is also turned on. Thus, the entire channel region 90 is turned on, and electrons flow from the source region 52 to the drain region 70. This sensed current is in a “1” state.

  On the other hand, when the floating gate 40a is negatively charged, the vertical channel region portion 92 is either weakly turned on or completely closed. Little or no current flows through the vertical channel region portion 92 even when the control gate 68 and drain region 70 rise to the read potential. In this case, the current is either very low compared to the “1” state, or no current is present. In this way, the memory cell is sensed and programmed with a "0" state. Since the ground potential is applied to the source / drain regions 52/70 and the control gate 68 of the unselected column and row, only the selected memory cell is read.

  The memory cell array includes peripheral circuitry including well-known row address decoding circuits, column address decoding circuits, sense amplifier circuits, output buffer circuits, and input buffer circuits, as is well known in the art.

  The present invention provides a memory cell array that is miniaturized and has excellent program efficiency. Since the source region 52 is embedded inside the substrate 10 and self-aligned with the second trench 34, the size of the memory cell can be greatly reduced, and space is wasted due to limitations during lithography generation, contact alignment, and contact integrity. Never become. Each floating gate 40a receives a tunnel effect electron during a program operation, and a lower portion provided in a second trench 34 formed in the substrate for turning on the vertical channel region portion 92 during a read operation. have. Each floating gate 40a also has an upper portion that extends from a second trench formed in the substrate and terminates at an edge facing the control gate due to the Fowler-Nordheim tunnel effect during the erase operation. doing.

  Program efficiency is greatly increased in the method of the present invention by the electrons being accelerated by the magnetic field lines generated from the floating gate and little or no impact ionization that causes the electrons to lose momentum or energy. The estimated program efficiency (number of injected electrons with respect to the total number of electrons) of the prior art device shown in FIG. 10A is estimated to be about 1/1000. However, in the present invention, the program efficiency is improved by 10 times or 100 times, and almost all electrons are injected into the floating gate.

  In the present invention, there is also an enhanced voltage coupling between each floating gate 40a and the corresponding source region 52 via a polyblock 54 (which is electrically connected to the source region 52). . At the same time, the voltage coupling between the floating gate 40a and the control gate 68 is relatively low. Furthermore, since the source region 52 and the drain region 70 are separated in the vertical direction and the horizontal direction, the reliability parameter can be easily optimized without affecting the cell size.

First Alternative Embodiment FIGS. 5A through 5J show cross-sectional views of structures within active region 22 in an alternative method for fabricating the memory cell array of the present invention. This first alternative processing begins with the structure shown in FIG. 2A. For the sake of brevity, elements common to the first embodiment are indicated using the same component numbers.

  A thick nitride layer 32 (eg, a thickness of 1000 to 10,000 か ら) is formed on the oxide layer 30. A second trench 34 parallel to the nitride layer 32 is applied by applying a photoresist material over the nitride layer 32 and then performing a masking process to remove the photoresist material from the selected parallel stripe regions. Form. An anisotropic nitride etch is used to remove the exposed portion of the nitride layer 32 in the stripe region and form a second trench 34 that extends down to the oxide layer 30 to expose the oxide layer 30. . After removing the photoresist layer, an oxide spacer 102 is formed in the second trench 34 by an oxide deposition process and a subsequent oxide anisotropic etching process. During this oxide etching process, the portion of the oxide layer 30 at the center of the bottom of the second trench is also removed, and the underlying substrate 10 is exposed. The structure after processing is shown in FIG. 5A.

  Using a silicon anisotropic etch process, the second trenches 34 are extended down into the substrate 10 in each active region 22 (eg, from about 500 to a few microns deep for 0.15 um technology). The width of the second trench 34 in the substrate 10 is basically the distance between the oxide spacers 102. A suitable ion implantation (and possibly also annealing) is then performed across the surface of the structure to form a first (source) region 52 in the exposed substrate portion at the bottom of the second trench 34. The source region 52 is self-aligned with the second trench 34 and has a second conductivity type (eg, N-type) that is different from the first conductivity type (eg, P-type) of the substrate. The ions do not affect the nitride layer 32 at all. The structure after processing is shown in FIG. 5B.

  Next, an oxide layer 100 is formed on the exposed silicon substrate 10 (forming the bottom and lower sidewalls of the second trench 34), preferably by thermal oxidation (eg, thickness is 70 to 150 mm). . Next, a thick poly layer is formed to cover the structure, thereby filling the second trench 34. Using the nitride layer 32 as an etch stop, a poly CMP etch process is used to leave the polyblock 54 in the second trench 34 and remove the other poly layer. A controlled poly etch is then used to lower the height of polyblock 54 below the top surface of nitride layer 32. Next, an optional oxide layer 104 is formed on the polyblock 54 (eg, by thermal oxidation). A thin nitride layer 106 is then deposited over the structure, followed by a masking step and nitride etch to remove the nitride layer 106 other than the portions covering the oxide layer 104 and polyblock 54. This can be accomplished by depositing a photoresist on the structure and then performing a controlled exposure so that only the photoresist in the second trench 34 remains over the deposited nitride. The structure after processing is shown in FIG. 5C.

  Using the nitride layer 106 as a mask, the oxide spacers 102 are removed using dry and / or wet oxide etching. This is followed by a thermal oxidation process to form an oxide layer 108 on the exposed sides of the polyblock 54 and the exposed portions of the substrate. An anisotropic oxide etch is used to remove the oxide layer 108 just formed on the substrate. The structure after processing is shown in FIG. 5D.

  Using the nitride layers 32 and 106 as a mask, silicon etching is used to etch away the exposed silicon substrate in the second trench 34 down to the same depth as the bottom of the polyblock 54. Additional ion implantation (and possibly also annealing) is used to widen the source region 52 under the second trench 34, as shown in FIG. 5E.

  Next, an insulating layer 110 (eg, 70 to 150 mm thick) is formed on the sidewalls of the second trench, preferably by oxide CVD deposition. A thick poly layer is formed over the structure to fill the second trench 34, followed by a CMP poly etch (using the nitride layer 32 as an etch stop) and an additional poly etch to form the top surface. Forms a lower polyblock 40a than the STI oxide block 26 in the isolation region 24. Next, the edge 96 on the top surface of the polyblock 40a is sharpened using gradient etching or oxidation. Next, an oxide deposition and etchback process is used to fill the upper portion of the second trench 34 with oxide 112, thereby sealing the polyblock 40a and providing an oxide spacer on top of the second trench 34. To produce. The processed structure is shown in FIG. 5F, but each second trench contains three polyblocks surrounded and sealed with oxide. Polyblock 54 is in electrical contact with source region 52 and is disposed between a pair of polyblocks 40a (insulated from source region 52).

  The polyblock 54 can optionally be stretched by removing nitride layer 106 and oxide layer 104 by controlled nitride and oxide etching, followed by poly deposition and poly CMP etchback. Prior to forming a protective oxide layer 114 overlying polyblock 54 using an oxidation process, an optional poly etch may be used to lower the new top surface of polyblock 54 as shown in FIG. 5G. Next, nitride layer 32 is removed using nitride etching. A controlled oxide etch is then used to excavate the exposed oxide by about 10 to several hundred angstroms, followed by a thermal oxidation process to re-form oxide layers 30 and 114, thereby forming polyblock 40a. There is a dent in the oxide surrounding the top surface. The structure after processing is shown in FIG. 5H.

  Poly spacers 68 adjacent to oxide spacers 112 are formed using poly deposition and anisotropic poly etching. A second (drain) region is formed in the substrate using suitable ion implantation (and annealing). Next, an insulating spacer 76 is formed by depositing an insulating material and anisotropic etching (eg, nitride or oxide) and placed facing the poly spacer 68. A metal deposition process is then performed to deposit a metal, such as tungsten, cobalt, titanium, nickel, platinum, or molybdenum, on the structure, and anneal in that state to allow the hot metal to flow into the exposed top portion of the poly spacer 68. So that the polycide 78 is formed thereon. The remaining metal deposited on the remaining structure is removed by a metal etching process. The structure after processing is shown in FIG. 5I.

  Insulating material 80, metal contacts 82, and drain wiring contacts 84 are formed as described above in connection with FIG. 2Q, resulting in the final structure shown in FIG. 5J. The advantage of this embodiment is that the solid source line polyblocks 54 and their electrical contacts with the source region 52 can be easily formed. Further, by separating the floating gate / polyblock 40a formed later using the polyblock 54, a short circuit between the floating gates can be easily prevented.

Second Alternative Embodiment FIGS. 6A-6G and FIGS. 7A-7G illustrate a second alternative method for fabricating the memory cell array of the present invention. This second alternative process begins with the structure shown in FIGS. 2B and 3B, but the oxide layer 30 is not formed under the nitride layer 32, and the oxide layer 30 is optional in this embodiment. It is. After forming the insulating material 36 described above in connection with FIG. 2C, the first (source) region 52 is formed on the exposed substrate portion at the bottom of the second trench 34 using ion implantation (and possibly also annealing). Form. A thin poly layer 118 is then formed over the structure, as shown in FIGS. 6A and 7A. The poly layer 118 may be (eg, n +) doped by ion implantation or by in situ processing. The thickness of the poly layer 118 is desirably 50 to 500 mm, but determines the final thickness of the floating gate for the final memory cell device.

  An oxide is formed over the structure, followed by a planarization oxide etch (eg, a CMP etch using the poly layer 118 portion on the nitride layer 32 as an etch stop), and the second trench 34 is oxidized. Fill with block 120. A subsequent poly etch removes the exposed portion of the poly layer 118 (ie, the portion on the nitride layer 32). An oxide etch is then used to dig the oxide block 120 until it is flush with the portion of the poly layer 118 left on the STI block 26 in the isolation region 24 (eg, a poly layer in the inactive region). The portion covering 118 STI blocks 26 is used as an oxide etch stop). The active / peripheral region structure after processing is shown in FIGS. 6B / 7B.

  Note that two separate portions of the poly layer 118 located at two different topography levels are used as etch stops in the oxide etch, poly etch, and oxide etch just described. . Specifically, as shown in FIG. 6A, the poly layer 118 has a first portion 119 a formed on the nitride layer 32 outside the trench 34. FIG. 6H is the same view as the second trench 34 shown in FIG. 6A, but in the isolation region 24 instead of the active region 22. As shown in FIG. 6H, the poly layer 118 has a second portion 119b formed on the STI block. Thus, the poly layer portion 119a is provided at a fine structure level higher than the fine structure level of the poly layer portion 119b. To form the oxide block 120 in the active region, a first oxide etch is performed using the poly layer portion 119a as an etch stop to fill the second trench 34 evenly in both the active and isolation regions 22/24. . In the next oxide etch, poly layer portion 119b is used as an etch stop to set the appropriate level of oxide block 120 in the active region and poly layer 118 is completely exposed in isolation region 24.

  A poly etch is then used to remove exposed portions of the poly layer 118 (ie, along the upper portion of the second trench 34 in the active region and covering the STI block 26 in the isolation region 24). Thereafter, an oxidation process is performed to form an oxide block 122 on the exposed end of the poly layer 118. Next, as shown in FIG. 6C, an oxide-like layer is formed by oxide deposition and etch back so as to cover the oxide block 122 and partially cover the oxide block 120 inside the second trench. A dielectric spacer 124 is formed. Using oxide etching again, the exposed central portion of the oxide block 120 is removed (the height between the spacers 124 is reduced by the oxide etching), and the poly layer in the central portion of the second trench 34 is removed. 118 is exposed. Subsequently, poly etching and oxide etching are performed to remove the exposed portion of the poly layer 118 and the oxide layer 36 at the center of the bottom of the second trench 34, thereby exposing a portion of the substrate. The structure after processing is shown in FIGS. 6D / 7D.

Next, a dielectric spacer 125 is formed inside the second trench 34 by depositing nitride (or oxide) on the structure and then performing anisotropic nitride etching. Next, the second trench 34 is filled with poly blocks 54 using a poly deposition and CMP etch back process (with nitride layer 32 as an etch stop) as shown in FIG. 6E. Nitride layer 32 is removed from active and isolation regions 22/24 and peripheral region 28 using a nitride etch. A tunnel oxide layer 56 is then formed on the exposed upper edge of the poly layer 118 by thermal oxidation, oxide deposition, or both. Since the oxide layer 32 has not been previously formed in this process, the oxide layer 56 extends to cover the exposed portion of the substrate 10. In this oxide formation step, an oxide layer 58 is also formed on the exposed upper surface of the polyblock 54. By masking the active region 22, an optional V _t implant may be performed at this point in the peripheral region 28. The active / peripheral region 22/28 after processing is shown in FIGS. 6F / 7F.

  Next, the remaining processing steps described above in connection with FIGS. 2M through 2Q are performed on the structure shown in FIGS. 6F and 7F, resulting in the final active region memory cell structure shown in FIG. 6G. Thus, the final peripheral area control circuit structure shown in FIG. 7G is completed.

  As shown in FIG. 6G, an L-shaped poly layer 118 constitutes a floating gate for each memory cell. Each floating gate 118 includes a pair of orthogonal elongated portions 118a / 118b joined together at the proximal end. The floating gate portion 118a extends along and is insulated from the substrate sidewall of the second trench 34, and the upper portion 118c extends above the substrate surface. The floating gate portion 118b extends along and is insulated from the bottom substrate wall of the second trench 34 (ie, extends over and is insulated from the source region 52). The control gate spacer 68 has a first portion laterally adjacent to and insulated from the upper portion 118c of the floating gate and a second portion disposed over and insulated from the upper portion 118c. Yes. The floating gate portion 118c terminates in a thin tip portion having a distal end directly facing the control gate 68 and insulated from it, thus floating the path for the Fowler-Nordheim tunnel. It is formed between the gate 118 and the control gate 68.

  A second alternative embodiment of the present invention provides a memory cell that is miniaturized and has excellent program efficiency. The size of the memory cell is such that the sole region 52 is embedded inside the substrate 10 and is self-aligned with the trench 34 so that space is not wasted due to constraints in lithography generation, contact alignment, and contact integrity. Can be significantly reduced. By “aiming” the horizontal portion 94 of the channel region 90 of the floating gate 118, the program efficiency is greatly enhanced. The L-shaped floating gate configuration of the present invention provides many advantages. Since the floating gate portion 118a / 118b is made of a thin layer of poly material, its upper tip is narrow and the Fowler-Nordheim tunneling effect for the control gate 68 is enhanced. There is no need for extensive thermal oxidation processes to form sharp edges with the aim of enhancing the tunnel effect. The voltage coupling ratio between each floating gate 118 and the corresponding source region 52 is also enhanced by the close proximity of the horizontal floating gate portion 118b and the source region 52 (separated by only the thin oxide layer 36). Has been. The upper tip of the floating gate upper portion 118c of the floating gate portion 118a is not formed by using an oxide process, but instead is formed by depositing a thin layer of polysilicon. To prevent, more heavily doped polysilicon can be used. Furthermore, by separating the source region 52 and the drain region 70 in the vertical and horizontal directions, the reliability parameters can be easily optimized without affecting the cell size.

  It should be noted that in this embodiment, the voltage coupling between the floating gate 118 and the source region 52 is sufficient, so additional voltage coupling with the polyblock 54 is preferred but not necessary. The poly block 54 of this embodiment mainly serves to electrically connect all the source regions 52 of each row of the paired memory cells electrically. Thus, the polyblock 54 can be omitted from this embodiment as long as electrical contacts similar to the contacts 82 are formed up to each source region 52. It should also be noted that each polyblock 54 needs to be insulated from the substrate so as not to short-circuit with the substrate when intersecting the isolation region. This can be done by making the depth of the STI block 26 in the isolation region deeper than the bottom of the second trench 34, or ensure that the material of the STI block 26 is slower than the material used to form the oxide block 120. This is realized by making it be etched.

Third Alternative Embodiment FIGS. 8A-8D and 9A-9D illustrate a third alternative method for fabricating the memory cell array of the present invention. This third alternative process begins with the structure shown in FIGS. 2B and 3B. After formation of the insulating material 36 described above in connection with FIG. 2C, the first (source) region 52 is formed in the exposed substrate portion at the bottom of the second trench 34 using ion implantation (and possibly also annealing). Form. Next, a polysilicon layer is formed on the structure, and thereafter, an anisotropic poly etching is performed to remove the poly layers other than the poly spacers 126, thereby forming the second trench 34 as shown in FIGS. 8A and 9A. A poly spacer 126 is formed on the substrate. The poly-spacer is preferably not higher in height than the STI block 26 in the isolation region 24 (eg, using the non-active region STI block 26 as an etch stop) to ensure that all polysilicon is removed from the isolation region. The

  An oxide is formed on the structure of FIGS. 8A / 9A and then etched by planarization oxide etching (eg, CMP using nitride layer 32 as an etch stop) to form second trench 34 in oxide block 128. Fill with. An oxide etch is then used to dig down the oxide block 128 so that it is flush with the top surface of the poly spacer 126 (eg, using the poly spacer 126 as an oxide etch stop). Next, as shown in FIG. 8, an oxide-like dielectric spacer 130 is formed on the inner side of the second trench 34 and on the poly spacer 126 through oxide deposition and etch back. Here, the oxide etching is again used to remove the exposed central portion of the oxide block 128 and the oxide layer 36 (the height between the spacers 130 is reduced by the oxide etching), and the substrate portion is removed. Expose. The structure after processing is shown in FIGS. 8C / 9C.

  Next, the remaining processing described above with reference to FIGS. 2K to 2Q is applied to the structure shown in FIGS. 8C and 9C, resulting in the final active region memory cell structure shown in FIG. The final peripheral area control circuit structure shown in 9D is completed. In this embodiment, the polyspacer 126 constitutes a floating gate, which is insulated from the control gate 68 via an oxide 56. By forming the floating gate as a spacer, the number and / or complexity of treatment steps is reduced. The floating gate spacers 126 each terminate at a sharp edge 96 that directly faces and is insulated from the control gate 68, and thus for the Fowler-Nordheim tunnel between the floating gate 126 and the control gate 68. Provides a route.

  It should be understood that the present invention is not limited to the embodiments described above and shown here, but includes all modifications that fall within the scope of the claims. For example, the trench 20/34 may end in any shape in the substrate, and is not limited to the elongated rectangle shown in the figure. Further, while the above method describes an example of using appropriately doped polysilicon as a conductive material for use in forming a memory cell, as will be apparent to those skilled in the art, in the present disclosure and claims The term “polysilicon” refers to any suitable conductive material that can be used to form the components of a non-volatile memory cell. Also, any suitable insulating material can be used in place of silicon dioxide or silicon nitride. In addition, any suitable material that differs in etching characteristics from silicon dioxide (or any insulator) and polysilicon (or any conductor) may be used in place of silicon nitride. Moreover, as is apparent from the claims, all method steps need not be performed in the order described in the description or the claims, but in any order as long as the memory cells of the present invention can be formed correctly. May be implemented. Further, although the invention has been shown to be formed on a substrate that is shown as being uniformly doped, the memory cell elements may be doped to have a conductivity type that differs from the rest of the substrate. It is also well known and considered in the present invention that it can be formed in the well region of the substrate being fabricated. Finally, a single layer of insulating or conductive material can be formed as multiple layers of such material and vice versa.

It is a top view of the semiconductor substrate used for the 1st process of the method of this invention for forming an isolation region. It is sectional drawing of the structure which follows the 1B-1B line | wire of FIG. 1A which shows the initial processing process of this invention. FIG. 1C is a top view of the structure illustrating the next processing step of the structure of FIG. FIG. 2 is a cross-sectional view of the structure taken along line 1D-1D of FIG. 1C, showing isolation trenches formed in the structure. 1D is a cross-sectional view of the structure of FIG. 1D showing a state in which an isolation block of material is formed in the isolation trench. FIG. FIG. 1E is a cross-sectional view of the structure of FIG. 1E showing the final structure of the isolation region. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. 2B is a cross-sectional view of the semiconductor structure taken along 2A-2A of FIG. 1F, sequentially illustrating the processing steps of the semiconductor structure when forming a non-volatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. FIG. 3 is a cross-sectional view of a peripheral region of a semiconductor structure, which sequentially shows the processing steps of the semiconductor structure when forming a nonvolatile memory array of floating gate memory cells of the present invention. It is a top plan view of the memory cell array of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating the steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2 is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2 is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating the steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating the steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating the steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2 is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating the steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating the steps in the first alternative processing embodiment of the semiconductor structure of the present invention. FIG. 2C is a cross-sectional view of the semiconductor structure taken along line 2A-2A of FIG. 1F, sequentially illustrating the steps in the first alternative processing embodiment of the semiconductor structure of the present invention. 3 is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a second alternative processing embodiment of the semiconductor structure shown in FIG. 2B; 3 is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a second alternative processing embodiment of the semiconductor structure shown in FIG. 2B; 3 is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a second alternative processing embodiment of the semiconductor structure shown in FIG. 2B; 3 is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a second alternative processing embodiment of the semiconductor structure shown in FIG. 2B; 3 is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a second alternative processing embodiment of the semiconductor structure shown in FIG. 2B; 3 is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a second alternative processing embodiment of the semiconductor structure shown in FIG. 2B; 3 is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a second alternative processing embodiment of the semiconductor structure shown in FIG. 2B; 3 is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a second alternative processing embodiment of the semiconductor structure shown in FIG. 2B; FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure sequentially illustrating steps in a second alternative working example of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure sequentially illustrating steps in a second alternative working example of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure sequentially illustrating steps in a second alternative working example of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure sequentially illustrating steps in a second alternative working example of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure sequentially illustrating steps in a second alternative working example of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure sequentially illustrating steps in a second alternative working example of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure sequentially illustrating steps in a second alternative working example of the structure shown in FIG. 3B. FIG. 2D is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a third alternative processing embodiment of the semiconductor structure illustrated in FIG. 2B. FIG. 2D is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a third alternative processing embodiment of the semiconductor structure illustrated in FIG. 2B. FIG. 2D is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a third alternative processing embodiment of the semiconductor structure illustrated in FIG. 2B. FIG. 2D is a cross-sectional view of a semiconductor structure sequentially illustrating steps in a third alternative processing embodiment of the semiconductor structure illustrated in FIG. 2B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure, sequentially illustrating steps in a third alternative processing embodiment of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure, sequentially illustrating steps in a third alternative processing embodiment of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure, sequentially illustrating steps in a third alternative processing embodiment of the structure shown in FIG. 3B. FIG. 3C is a cross-sectional view of an isolation region of a semiconductor structure, sequentially illustrating steps in a third alternative processing embodiment of the structure shown in FIG. 3B. FIG. 2 is a partial cross-sectional view of a prior art flash type nonvolatile memory cell and its plug-lamming mechanism. It is a fragmentary sectional view of a prior art EPROM type non-volatile memory cell and its pramming mechanism. It is a fragmentary sectional view of a part of nonvolatile memory cell of the present invention, and its programming mechanism.

Claims (5)

Electrically having a substrate of a semiconductor material of a first conductivity type and having first and second regions spaced apart by forming a non-coplanar channel region therebetween on the second conductivity type substrate A programmable and erasable memory device, wherein the non-coplanar channel region has two parts, a first part and a second part, and a conductive control gate is a first part of the channel area. The floating gate is adjacent to the second portion of the channel region and is then insulated by an insulator, In a method of programming a memory device having a portion provided to create a depletion region having magnetic field lines directed to a floating gate, and wherein the first region is configured to be adjacent to the inversion layer.
Creating the inversion layer;
Generating a flow of electrons in the first region and traversing the flow of electrons through the inversion layer;
Accelerating the flow of electrons through the depletion region by the magnetic field lines with little or no scattering so that the electrons are accelerated and injected through the insulator into the floating gate; A method characterized by comprising.   The method of claim 1, wherein the channel region has a first portion along a horizontal plane and a second portion in a trench.   The method of claim 1, wherein the channel region has a first portion in a trench and a second portion along a horizontal plane.   The method of claim 2, wherein the first portion is substantially perpendicular to the second portion.   The inversion layer has a pinch-off point adjacent to or in the depletion region, and the electron flow starts from the pinch-off point to accelerate through the depletion region. The method of claim 4.

Images