JP2000269365A - Nonvolatile semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics in a nonvolatile semiconductor storage device. SOLUTION: A nonvolatile semiconductor storage device is provided with floating gates 32 which are buried in the step sections of a P-type silicon substrate 21, tunnel insulating films 33 covering the gates 32, and control gates 36 which are formed to have areas overlapping the gates 32 through the insulating films 33. The storage device is also provided with N-type source and drain areas 39 and 40 formed adjacently to the floating gates 32 and control gates 36 on the surface of the silicon substrate 21, a conductive film 45 which is formed on the surface of the source area 39 and can reduce the resistance of the area 39, and metallic wiring 44 connected to the source and drain areas 39 and 40 through an interlayer insulating film 42.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate formed so as to overlap the floating gate via a tunnel insulating film covering the floating gate, and a method of manufacturing the same. About.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory device in which a memory cell is composed of a single transistor, particularly a programmable ROM (Electrically Erasable a EEPROM).
In an nd programmable ROM, a flash EEPROM also called a flash memory, etc.), each memory cell is formed by a transistor having a double gate structure having a floating gate and a control gate. In such a memory cell transistor having a double gate structure, data is written by accelerating and injecting hot electrons generated on the drain region side of the floating gate into the floating gate. And
Data is erased by extracting charges from the floating gate to the control gate by FN conduction (Fowler-Nordheim tunnelling).

FIG. 6 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.
Is a sectional view taken along line X1-X1. FIG. 1 shows a split gate structure in which a control gate is arranged alongside a floating gate.

In a surface region of a P-type semiconductor silicon substrate 1, a plurality of element isolation films 2 each formed of a LOCOS oxide film selectively formed thick by a LOCOS (Local Oxidation Of Silicon) method are formed in a strip shape. Is partitioned. Floating gate 4 is arranged on silicon substrate 1 so as to straddle between adjacent element isolation films 2 via oxide film 3A. This floating gate 4
Are arranged independently for each memory cell. Also,
The selective oxide film 5 on the floating gate 4 is formed to be thick at the center of the floating gate 4 by a selective oxidation method, and a sharp corner is formed at an end of the floating gate 4. This makes it easier for electric field concentration to occur at the end of the floating gate 4 during the data erasing operation.

On the silicon substrate 1 on which a plurality of floating gates 4 are arranged, a control gate 6 is arranged via a tunnel insulating film 3 integrated with the oxide film 3A corresponding to each column of the floating gates 4. Is done. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the silicon substrate 1 via the oxide film 3A. The floating gate 4 and the control gate 6 are
The adjacent rows are arranged so as to be plane-symmetric with each other.

An N-type drain region 7 and a source region 8 are formed in a substrate region between the control gate 6 and a substrate region between the floating gates 4. The drain region 7 is formed between the control gate 6 and the device isolation film 2.
Are separated from each other, and the source region 8 continues in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a memory cell transistor.

Then, on the control gate 6,
Metal wiring 10 is arranged in a direction intersecting control gate 6 with interlayer insulating film 9 interposed therebetween. This metal wiring 10
Is connected to the drain region 7 through the contact hole 11. Each control gate 6 becomes a word line, and the source region 8 extending in parallel with the control gate 6 becomes a source line. Also, the drain region 7
Wiring 10 made of aluminum alloy or the like to be connected to
Becomes a bit line.

In the case of such a memory cell transistor having a double gate structure, the on-resistance between the source and the drain varies depending on the amount of charge injected into the floating gate 4. Therefore, by selectively injecting charges into the floating gate 4, the on-resistance value of a specific memory cell transistor is changed, and the resulting difference in the operating characteristics of each memory cell transistor is made to correspond to the stored data. ing.

The data write, erase, and read operations in the above nonvolatile semiconductor memory device are performed, for example, as follows. In the write operation, the potential of the control gate 6 is 2 V, the potential of the drain region 7 is 1 V, and the high potential of the source region 8 is 11 V. Then, between the control gate 6 and the floating gate 4 and between the floating gate 4 and the substrate (source region 8) are capacitively coupled (the capacitance between the control gate 6 and the floating gate 4 <the floating gate 4 and the substrate (source region 8). ), The potential of the floating gate 4 is 9
The hot electrons generated near the drain region 7 are accelerated to the floating gate 4 side and are injected into the floating gate 4 through the oxide film 3A to write data.

On the other hand, in the erasing operation, the potentials of the drain region 7 and the source region 8 are set to 0 V, and the control gate 6 is set to 15 V. As a result, the charges (electrons) accumulated in the floating gate 4 are transferred from the FN (Fowler-Nor
The tunnel insulating film 3 is formed by conduction.
Is released to the control gate 6 to erase the data.

In the read operation, the potential of the control gate 6 is set at 4 V, and the drain region 7 is set at 2 V.
V and the source region 8 is set to 0V. At this time, if charges (electrons) are injected into the floating gate 4, the potential of the floating gate 4 becomes low, so that no channel CH is formed below the floating gate 4 and no drain current (read current) flows. . Conversely, if charges (electrons) have not been injected into the floating gate 4,
Since the potential of the floating gate 4 becomes higher, a channel CH is formed below the floating gate 4 and a drain current (read current) flows.

[0012]

The nonvolatile semiconductor memory device having such a structure has the following problems due to its structure. That is, since the common source line (SL) including the source region 8 has the diffusion layer structure as described above, the SL resistance naturally is high. At the time of writing, a high voltage (11 V) needs to be applied to the source electrode, and the writing voltage is high. Further, the writing efficiency at the time of hot electron injection is poor. The split gate structure of the present structure has a problem that the cell area is large in order to secure the channel length of the channel region below the floating gate 4 and the control gate 6.

[0013]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and a nonvolatile semiconductor memory device of the present invention has a P-type semiconductor silicon substrate as shown in FIG. 21, a floating gate 32 buried in the step portion, a tunnel insulating film 33 covering the floating gate 32, and a control gate 36 formed to have a region overlapping the floating gate 32 via the tunnel insulating film 33. N-type source / drain regions 39 and 40 formed on the surface of the silicon substrate 21 adjacent to the floating gate 32 and the control gate 36; and a low resistance of the source region 39 formed on the source region surface. Via a conductive film 45 which enables the formation of the source and the interlayer insulating film 42.
And a metal wiring 44 connected to the drain regions 39 and 40.

The manufacturing method is as follows. After forming an insulating film (pad oxide film 23) on a P-type semiconductor silicon substrate 21 as shown in FIG. 3A, as shown in FIG. Using the resist film 24 as a mask, the insulating film 23 is patterned to expose the substrate. Next, FIG.
As shown in (c), after removing the resist film 24, a polysilicon film 25 is formed on the entire surface, N-type impurities are added to the polysilicon film 25 to make it conductive, and the substrate surface is exposed. N-type impurities are exuded to the portion (N-type diffusion layer 27). Subsequently, the polysilicon film 2
After a tungsten silicide (WSix) film 26 is formed on the substrate 5, the polysilicon film is formed by using the resist film 28 and the insulating film 23 formed in a portion where the substrate surface is exposed as shown in FIG. The film 25 and the tungsten silicide film 26 are patterned to form a conductive film 45.
Is formed, and a part of the substrate 21 is removed by etching to form a concave portion 29. Further, after removing the insulating film 23 as shown in FIG. 4B, a gate insulating film 30 is formed on the entire surface, and a polysilicon film 31 is formed on the gate insulating film 30 as shown in FIG. After the polysilicon film 31 is formed, the polysilicon film 31 is anisotropically etched so that at least the polysilicon film 31 remains in the recess 29, and as shown in FIG.
To form Next, as shown in FIG. 5B, a tunnel insulating film 33 is formed on the entire surface including the floating gate 32.
Is formed, and a control gate 36 having a region overlapping with the floating gate 32 via the tunnel insulating film 33 is formed. Then, as shown in FIG. 5 (c), N-type impurities are ion-implanted into the surface of the substrate adjacent to the control gate 36, and heat treatment is applied to exude the ion-implanted N-type impurities and the substrate surface. After forming the N-type source / drain regions 39 and 40 by diffusing the N-type diffusion layer 27A thus formed, a metal wiring 44 contacting the source / drain regions 39 and 40 via an interlayer insulating film 42 is formed. And a step.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a nonvolatile semiconductor memory device according to the present invention and a method for manufacturing the same will be described with reference to the drawings.

FIGS. 1 and 2 are a plan view and a partial (X2-X2) sectional view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate.

In the figure, reference numeral 21 denotes a semiconductor silicon substrate of one conductivity type, for example, a P-type, 32 denotes a floating gate buried in a step (recess 29) provided on the substrate 21, and 33 denotes a floating gate. A control gate 36 is formed to cover the floating gate 32 with the tunnel insulating film 33 interposed therebetween. Further, N-type source / drain regions 39 and 40 are formed on the surface layer of the silicon substrate so as to be adjacent to the floating gate 32 and the control gate 36, and the surface of the source region 39 shared by the adjacent memory cells is formed on the surface. In addition, a conductive film 45 that enables the source region 39 to have a low resistance is formed. The nonvolatile semiconductor memory device has a structure in which a metal wiring 44 is connected to the source / drain regions 39 and 40 via an interlayer insulating film 42.

The feature of the present invention is that the source region 39
By forming the conductive film 45 on the common source line (SL) made of, the SL resistance is reduced as compared with the conventional diffusion layer structure. For example, while the SL resistance in the conventional diffusion layer structure is about 100Ω / □, the SL resistance in the structure of the present invention is about 25Ω / □.
The resistance is reduced by about 1/4. Therefore, the access time at the time of writing and reading can be shortened.

The source region 39 and the drain region 40
Since the floating gate 32 is formed at a position (between the source region 39 and the drain region 40) where hot electrons generated between the source electrode 39 and the drain region 40 are easily injected, the injection efficiency is improved. The applied high voltage (write voltage) can be reduced.
Therefore, at the time of writing, in the conventional structure, it was necessary to increase the write voltage applied to the source electrode to about 11 V, but in the structure of the present invention, the write voltage applied to the source electrode was about 5 V, which was sufficient. ,
The boosting time can be omitted, and the writing time can be shortened.

Further, in the split gate type of this structure,
By forming the floating gate 32 on the step portion of the substrate 21, the total channel C in the channel region below the floating gate 32 and the control gate 36 is formed.
The cell area for securing the H length is reduced as compared with the conventional configuration. That is, in the conventional split gate type (shown in FIG. 7), the cell area required for obtaining the channel CH length L1 needs L1 as it is, but in the split gate type of this structure (shown in FIG. 2). , The cell area required to obtain the channel CH length L1 is L2 (L1
> L2), and the size was reduced. Although this differs depending on the design rule, when this configuration is applied to the 0.35 μm rule, the cell area can be reduced by about 10%.
Large capacity can be achieved.

Hereinafter, a method of manufacturing a memory cell of such a nonvolatile semiconductor memory device will be described with reference to the drawings.

First, in FIG. 3A, an element isolation film 22 is formed in a predetermined region of a P-type semiconductor substrate 21 (see FIG. 1), and a pad oxide film 23 is formed on a surface layer other than the element isolation film 22. Is formed to a thickness of about 200 °. still,
As a method for forming the element isolation film 22, a well-known LOCOS method or a trench method may be used.

Next, referring to FIG.
4 is used as a mask, a part of the pad oxide film 23 is wet (or dry) etched to expose the substrate surface.

Subsequently, in FIG. 3C, after removing the resist film 24, a polysilicon film 25 is formed to a thickness of about 600.degree.
Six) film 26 is formed to a thickness of about 1000 °.
Here, the polysilicon film 25 may be formed of, for example, 83 before the tungsten silicide (WSix) film 26 is laminated.
At 0 ° C., POCl ₃ is doped with phosphorus as a thermal diffusion source to make it conductive. It should be noted that N-type impurities, for example, arsenic ions may be made conductive by ion implantation at an acceleration voltage of 30 to 40 KeV at an implantation amount of 1 × 10 ¹⁵ / cm ² . At this time, the N-type diffusion layer 27 is formed on the surface of the substrate from which the pad oxide film 23 has been removed, by the N-type impurities seeping out from the polysilicon film 25. Note that phosphorus ions or the like may be used as the N-type impurities to be ion-implanted.

Further, in FIG. 4A, a resist film 28 formed on the substrate from which the pad oxide film 23 has been removed is formed.
Using the tungsten silicide (WSi
x) The conductive film 4 composed of the polysilicon film 25 and the tungsten silicide (WSix) film 26 by patterning the film 26, the polysilicon film 25, and the substrate 21, respectively.
5 and a recess 29 having a depth of about 0.2 μm from the substrate. At this time, after performing anisotropic etching to about 0.1 μm to 0.15 μm from the substrate surface, the substrate is further isotropically etched to about 0.05 μm. In this step, for example, after anisotropic etching is performed using Cl ₂ or SF ₆ gas, isotropic etching is performed using CF ₄ gas.

The substrate 21 is anisotropically etched and then isotropically etched, whereby the laterally diffused diffusion portion of the diffusion layer 27 can be completely removed. The bottom corner of the concave portion 29 provided in the taper 21 has a tapered shape, and it is possible to suppress a problem such as a leak current which is likely to occur due to a sharp corner or the like.

Next, in FIG. 4B, after removing the resist film 28 and the pad oxide film 23, the entire surface is thermally oxidized to form a dummy oxide film. In order to prevent the inversion layer, for example, boron ions are implanted at an acceleration voltage of 20 KeV at an implantation amount of 1 × 10 ¹² / cm ² . The ion implantation region is not shown for convenience. After removing the dummy oxide film, a gate insulating film 30 is formed to a thickness of about 100 °. By this thermal oxidation step, the N-type diffusion layer 27 diffuses into the substrate to form an N-type diffusion layer 27A.

Subsequently, as shown in FIG. 4C, a polysilicon film 31 is formed on the entire surface to a thickness of about 2000.degree., And the polysilicon film 31 is formed in the same manner as described above (phosphorus doping or arsenic ion implantation). Is made conductive.

Further, in FIG. 5A, the polysilicon film 31 is anisotropically etched to leave a film on the side wall of the conductive film 45. At this time, the inside of the concave portion 29 is completely buried with the polysilicon film to form the floating gate 32. In this state, for example, boron ions are implanted into the entire surface at an acceleration voltage of 20 KeV at an implantation dose of 1 × 10 ¹² / cm ² for adjusting the threshold voltage. The ion implantation region is not shown for convenience.

Next, in FIG. 5B, the entire surface including the floating gate 32 is thermally oxidized in a dry atmosphere to be integrally formed with the gate insulating film 30 and has a thickness of about 300 to 400 °. A tunnel insulating film 33 having a thickness of about 200 ° is formed between the floating gate 30A and the floating gate 32 and the control gate. Subsequently, a polysilicon film 34 is formed to a thickness of about 600 °, and a tungsten silicide (WSix) film 35 is formed to a thickness of about 1000 °. Here, before the tungsten silicide (WSix) film 35 is laminated, the polysilicon film 34 is made conductive in the same manner as described above (phosphorus doping or arsenic ion implantation).

In FIG. 5C, the polysilicon film 34 and the tungsten silicide (WSix) film 35 are patterned using a resist film (not shown) as a mask, and the control gate 36 is connected to the tunnel insulating film 33.
Is formed so as to overlap with a part of the floating gate 32 through the gate. And the control gate 36
Is used as a mask, N-type impurities, for example, phosphorus ions, are added to the surface of the substrate at an acceleration voltage of 30 KeV to 3 × 10 ¹³ / cm ^2.
The low-concentration drain region 38 is formed by ion implantation at an implantation amount of (a diffusion region is formed through an annealing process in a later step). Note that arsenic ions or the like may be used as the N-type impurities to be ion-implanted. Subsequently, a sidewall insulating film 37 is formed so as to cover the sidewall of the control gate 36. Then, by reoxidizing the entire surface, the floating gate 32 and the control gate 36 are re-oxidized.
The shape of the sharp edge in the direction toward the substrate at the end of the overlapping region becomes gentle. That is, in the floating gate 32 and the control gate 36 formed so as to overlap with each other with the tunnel insulating film 33 interposed therebetween, when the side wall of the control gate 36 (particularly, the polysilicon film portion) is oxidized, the polysilicon film is oxidized. And the floating gate 3
2 is also oxidized, so that the lower portion of the polysilicon film is rounded as shown, the upper portion of the floating gate 32 has a so-called bowl shape, the portion overlapping the end of the control gate 36 is rounded, and the floating portion is floating. The tip corner of the gate 32 has a sharper shape (the sharp portion 3).
2A). As a result, the movement of charges (electrons) from the control gate 36 to the floating gate 32 can be suppressed, and when the charges (electrons) accumulated in the floating gate 32 are removed from the floating gate 32 to the control gate 36 during erasure, Electric field concentration occurs at the sharp portion 32A, and the movement of charges (electrons) to the control gate 36 proceeds, thereby improving the erasing efficiency.

Further, using the control gate 36 and the side wall insulating film 37 as a mask, an N-type impurity, for example, arsenic ion is added to the substrate surface layer at an acceleration voltage of 50 KeV for 3 ×.
A high concentration drain region 40 is formed by ion implantation at a dose of 10 ¹⁵ / cm ² . The ion-implanted N
Phosphorus ions or the like may be used as the type impurity. Then, by performing the annealing process, the N-type impurity ion-implanted in the previous step is diffused to form the drain region 40 having the LDD structure. At this time, the N-type diffusion layer 27A is simultaneously formed.
Diffuses deep into the substrate to form a high-concentration source region 39 (see FIG. 2).

Then, as shown in FIG. 2, the entire surface is covered with an interlayer insulating film 42 and the source / drain regions 39 and 40 are covered.
After forming a contact hole 43 that contacts the metal wiring 44, a metal wiring 44 is formed on the source / drain regions 39 and 40 via a barrier metal film (not shown) (for example, a laminated film of a titanium film and a titanium nitride (TiN) film). (For example, Al, Al-Si, Al-Cu, Al-Si-Cu
Etc.) to complete the nonvolatile semiconductor memory device.
A contact plug (for example, made of a tungsten film or the like) is formed in the contact hole via a barrier metal film, and a metal film (for example, A
1, Al-Si, Al-Cu, Al-Si-Cu, etc.) to form metal wiring.

As described above, according to the present invention, the tungsten silicide (WSix) film 2 is formed on the source region 39.
6 and the polysilicon film 25, the resistance of the source region 39 is reduced.

Further, since the floating gate 32 is formed in a step (recess 29) formed between the source region 39 and the drain region 40 on the surface layer of the substrate, the floating gate 32 is generated between the source region 39 and the drain region 40. Hot electron injection efficiency can be improved, and a high voltage (write voltage) applied to the source electrode during writing can be reduced.

Further, in the split gate type having this structure,
By forming the floating gate 32 on the step portion of the substrate 21, the total channel C in the channel region below the floating gate 32 and the control gate 36 is formed.
The cell area for securing the H length can be reduced.

The operations of writing, erasing, and reading data in the nonvolatile semiconductor memory device described above are performed, for example, as follows. Since the basic operation in each operation is the same as that of the conventional structure, the operation will be briefly described.

First, in the writing operation, the potential of the control gate 36 is applied to 1 V, the potential of the drain region 40 is applied to 0 V, and the potential of the source region 39 is applied to 5 V. Then, the capacitance coupling ratio between the control gate 36 and the floating gate 32 and between the floating gate 32 and the substrate (source region 39) (the control gate 36
And the capacitance between the floating gate 32 and the capacitance between the floating gate 32 and the substrate (source region 39) raises the potential of the floating gate 32 to about 5V, and hot electrons generated near the drain region 40 are directed to the floating gate 32 side. The data is accelerated and injected into the floating gate 32 through the gate insulating film 30A to write data.

On the other hand, in the erase operation, the potential of the drain region 40 and the source region 39 is set to 0 V, and the control gate 6 is set to 15 V. As a result, charges (electrons) stored in the floating gate 32 are transferred from the sharp portion 32A at the upper portion of the floating gate 32 to F
-N (Fowler-Nordheim tunnelling) conduction penetrates through the tunnel insulating film 33 and is released to the control gate 36 to erase data.

In the read operation, the potential of the control gate 36 is set to 4 V and the drain region 40
Is 2V, and the source region 39 is 0V. At this time, if electric charges (electrons) are injected into the floating gate 32, the potential of the floating gate 32 becomes low.
No channel CH is formed below the floating gate 32, and no drain current (read current) flows. Conversely, if charges (electrons) have not been injected into the floating gate 32, the potential of the floating gate 32 increases, so that a channel CH is formed below the floating gate 32 and a drain current (read current) flows.

[0041]

According to the present invention, a film is formed on one of the diffusion regions shared by adjacent memory cells so as to reduce the resistance of the diffusion region. Therefore, the access time at the time of writing and reading can be shortened.

Further, by forming a floating gate at a step formed between the source region and the drain region on the surface of the substrate, the injection efficiency of hot electrons generated between the source region and the drain region can be improved. The writing voltage at the time of writing can be reduced.

Further, in the split gate type of this structure,
By forming the floating gate on the step portion of the substrate, the cell area for securing the total channel length of the channel region below the floating gate and the control gate can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a partial (X2-X2) sectional view of FIG.

FIG. 3 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 5 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device of the present invention.

FIG. 6 is a plan view showing a structure of a memory cell of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a partial (X1-X1) sectional view of FIG. 6;

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) JA37 JA39 JA40 JA53 MA06 MA20 PR03 PR12 PR36

Claims (5)

[Claims] 1. A floating gate formed on a silicon substrate of one conductivity type, an insulating film covering the floating gate, and a region overlapping the floating gate with the insulating film interposed therebetween. A control gate; a diffusion region of a reverse conductivity type formed on the surface of the silicon substrate adjacent to the floating gate and the control gate; and a metal wiring connected to the diffusion region via an interlayer insulating film. The nonvolatile semiconductor memory device according to claim 1, wherein the metal wiring is formed on a surface of one of the diffusion regions via a film capable of reducing the resistance of the diffusion region. 2. A floating gate buried in a step portion of a silicon substrate of one conductivity type, a tunnel insulating film covering the floating gate, and a region overlapping the floating gate via the tunnel insulating film. A diffusion region of the opposite conductivity type formed on the surface of the silicon substrate adjacent to the floating gate and the control gate; and a low resistance of the diffusion region formed on the surface of one of the diffusion regions. And a metal wiring connected to the diffusion region via an interlayer insulating film. 3. The one diffusion region is used in common with an adjacent memory cell, and the film that can reduce the resistance of the diffusion region is a polysilicon film or a laminated film of a polysilicon film and a tungsten silicide film. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is a conductive film made of: 4. A step of forming an insulating film on a silicon substrate of one conductivity type, patterning the insulating film using a resist film as a mask to expose the substrate, and removing the resist film to form an entire surface. A step of forming a polysilicon film, a step of adding a reverse conductivity type impurity to the polysilicon film to make the polysilicon film conductive and exposing the reverse conductivity type impurity to a portion where the substrate surface is exposed, and Patterning the polysilicon film using the resist film and the insulating film formed in the portion where the surface is exposed as a mask, and etching away a part of the substrate to form a concave portion; and removing the insulating film. Forming a gate insulating film on the entire surface later; and forming an anisotropically etching the polysilicon film after forming the polysilicon film on the gate insulating film. Forming a floating gate by leaving at least a polysilicon film in the recess; forming a tunnel insulating film on the entire surface including on the floating gate; overlapping with the floating gate via the tunnel insulating film Forming a control gate having a region, and ion-implanting a reverse-conductivity-type impurity into a surface layer of the substrate adjacent to the control gate and applying a heat treatment to the ion-implanted reverse-conductivity-type impurity and stain on the surface of the substrate. Forming a diffusion region of the opposite conductivity type by diffusing the extracted impurity of the opposite conductivity type; and forming a metal wiring contacting the diffusion region via the interlayer insulation film after forming the interlayer insulation film. And a method for manufacturing a nonvolatile semiconductor memory device. 5. A step of forming an insulating film on a silicon substrate of one conductivity type, patterning the insulating film using a resist film as a mask to expose the substrate, and removing the resist film to form an entire surface. A step of forming a polysilicon film; a step of adding a reverse conductivity type impurity to the polysilicon film to make the polysilicon film conductive and exuding a reverse conductivity type impurity to a portion where the substrate surface is exposed; and After forming a tungsten silicide film on a silicon film, the polysilicon film and the tungsten silicide film are patterned using the resist film and the insulating film formed in a portion where the substrate surface is exposed, and a part of the substrate is patterned. Forming a recess by etching away; forming a gate insulating film over the entire surface after removing the insulating film; Forming a floating gate by forming a polysilicon film on the gate insulating film and then anisotropically etching the polysilicon film so that at least the polysilicon film remains in the concave portion; Forming a tunnel insulating film on the entire surface including: a step of forming a control gate having a region overlapping with the floating gate via the tunnel insulating film; and an impurity of a reverse conductivity type in a substrate surface layer adjacent to the control gate. Forming an ion-implanted region for forming a low-concentration diffusion region by ion-implanting, forming a sidewall insulating film so as to cover a sidewall portion of the control gate, and thermally oxidizing the entire surface to form the control gate. Oxidize the end of the floating gate that overlaps with the gate, and Forming a sharp portion at an upper corner of the gate, and forming an ion-implanted region for forming a high-concentration diffusion region by ion-implanting an impurity of the opposite conductivity type into a surface layer of the substrate adjacent to the sidewall insulating film. Forming a diffusion region of the opposite conductivity type by diffusing the impurity of the opposite conductivity type ion-implanted by applying heat treatment and the impurity of the opposite conductivity type exuded to the surface of the substrate; and an interlayer insulating film. Forming a metal wiring in contact with the diffusion region via the interlayer insulating film after forming the semiconductor device.