TW200537696A - An improved method of programming electrons onto a floating gate of a non-volatile memory cell - Google Patents

Abstract

A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is-disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region. A method of programming the cell comprises the steps of creating an inversion layer in the second portion of the channel. A stream of electrons is generated at the drain region which is adjacent to the inversion layer, and the stream of electrons is passed through the inversion layer, reaching a pinch off point. The electrons are accelerated through the depletion region by the field lines from the floating gate, with little or no scattering, causing the electrons to be accelerated through the insulator, separating the floating gate from the substrate, and injected onto the floating gate.

Description

200537696 IX. Description of the invention: This case is part of the follow-up application of US Patent Application No. 10/358623 filed on February 4, 2003. Therefore, the rights of the following cases must also be requested: No. 60/370888 US provisional application, 5 is named highly coupled non-volatile trench memory cell; July 2, 2002, ν 60 · 393696 US provisional application, named as non-volatile Trench memory cell and manufacturing method thereof; and ν 60 · 398146 US provisional application filed on July 23, 2002, named as a non-volatile trench memory cell with embedded floating gate; 1 The contents of all these cases are hereby incorporated by reference. [Belonging to the Institute of Technology] Technical Field: The invention relates to a method for self-alignment of a semiconductor memory array for manufacturing floating gate memory cells. The present invention also relates to a semiconductor memory array having the above-mentioned types of floating gate 15 memory cells. BACKGROUND OF THE INVENTION Non-volatile semiconductor memory cells using a sequential gate to store charge and memory 20 arrays of non-volatile memory cells such as those fabricated in semiconductor substrates are well known in the art. Generally, these floating interpolar memory cells are split-gate or stacked-gate. One of the major problems in manufacturing such semiconductor floating-gate memory cell arrays is the alignment of its various components such as source, drain, gate, and floating gate. As the design specifications of the semiconductor integration process are reduced, the size of the smallest lithography structure is reduced, so the need for precise alignment becomes more important. The alignment of various components will also determine the manufacturing yield of semiconductor products. Self-alignment is widely known in the art. Self-alignment refers to the practice of enabling the feature structures 5 to automatically align with each other in the process when performing one or more dream steps including one or more materials. Therefore, the present invention will use self-alignment technology to achieve the fabrication of the semiconductor memory array of floating gate memory cell type. In order to maximize the number of memory cells on a single wafer, the size of the memory cell array must be continuously reduced. It is known that these memory cell 10 lines are made in pairs, and each pair will share a source region, and adjacent cell pairs will share a drain region, which can reduce the memory cell array. size. But 'the array still has a large area typically reserved for bit lines to connect to these > and polar regions. This bit line area is usually occupied by the contact holes between the memory cell pairs, and the contacts spaced by the word lines. This is very dependent on the lithography generation's contact alignment and contact integrity. . Moreover, sufficient space will be reserved for the word line transistor, and its size is set by lithography generation and interface sizing. Traditionally, a floating gate will be provided with a sharp-edged counter-control gate to enhance Fowler-Nordheim tunneling, which can be used to remove electrons from the floating gate during an erase operation. The sharp edge is typically made by unevenly oxidizing or partially etching the top surface of the floating gate material. However, the smaller the size of the floating gate, the more difficult it is to make this sharp edge. There is also a need to improve the planning efficiency of memory cell arrays. Please refer to Figure 10A, 200537696, which is a partial cross-sectional view of a conventional flash memory cell 200 (as disclosed in US Patent No. 5029130, the contents of which are incorporated herein by reference). When planning, an area 210 will be maintained at or near ground voltage. The region 220 is supplied with a high voltage, such as + ι〇ν. An empty area 5 250 is set around this area 220. Also, because there will be a high capacitive coupling between this region 22o and the floating gate 230, the floating gate 23 () will "appear" a voltage of approximately + 7V. A voltage that is slightly more positive than the threshold voltage, such as +1. 5V is applied to the control gate 240. Since the voltage at the control gate 240 is lower than the voltage at the floating gate 23 °, the field line will flow from the floating gate to the substrate 260 and then to the control gate 240. '' When a positive voltage is applied to the control gate 240, a portion of the channel region under the control gate 240 will be “conducted,” and an inversion layer 28 will be formed. The electrons flowing from the first region 210 will Close to the surface of the substrate 26 in the inversion layer 28 until it reaches the extrusion point 295. At this point, the electrons will be accelerated by the 15 field lines. However, if the electrons are to be "shot out" to float On the gate 230, the electrons of the first region 210 must collide (ie, scatter) with impurities or lattice defects in the substrate 26, and generate momentum in a vertical direction. In addition, only those electrons having a vertical velocity sufficient to overcome the energy barrier between the oxide and silicon will be ejected onto the floating gate 230. Therefore, only a small percentage (about one-thousandth) of the electron current in the inversion layer 280 will have sufficient energy to be incident on the floating gate 230. Therefore, the scattering system is one of the main focuses in this planning mechanism. Please refer to FIG. 10B, which shows another conventional planning mechanism including an EPROM cell 300. Similar to the flash cell 200 shown in Figure 10a, 200537696, when planning, the first region 210 will be maintained at or near the ground voltage. The other area 220 is supplied with a high voltage such as + 12V. An empty area 250 is provided around the second area 220. A high voltage, such as + 12V, will also be applied to the control gate 240, which makes the floating gate 230 appear to have approximately + 7V. Since the voltage on the floating gate 230 is smaller than the voltage on the empty region 250, the field line will be sent from the empty region 250 to the floating gate 230. In addition, since the floating gate "looks like" about + 7V, the portion of the channel region under the floating gate 230 will "conduct", that is, an inversion layer 280 will be formed. The electrons will flow from the first region 210 to the surface of the substrate 260 close to the inversion layer 280 until it reaches the extrusion point 295. At this point 295, the electrons are accelerated by the field lines. However, these electrons will actually be repelled away from the surface of the substrate 260 by field lines. These electrons therefore operate in a downward direction. In order to emit electrons onto the floating gate 230, the electrons in the first region 210 must collide with impurities or lattice defects in the substrate 260 to generate a vertical component of momentum. Only those with a sufficient initial vertical velocity of 15 are sufficient to overcome in the upward vertical direction: 1) the repulsive field in the substrate; 2) the energy barrier at the interface of Shi Xi with the oxide; and 3) at the oxide Only electrons in the repulsive field can be irradiated onto the floating gate 230. However, since the electrons actually run "down" at the beginning, the electron flow from the inversion layer 280 will only have 20 ratios of electrons (about several hundreds of thousands) than the flash cell 200 described above. (Even parts per million) can be planned with sufficient energy to be projected onto the floating gate 230. So again, scattering is also a major focus in this planning mechanism. It is therefore an object of the present invention to create a method to improve the planning efficiency of a non-volatile memory cell having a floating gate capable of storing electrons. 200537696 It is also known that memory cell elements can be fabricated on non-flat parts of the substrate. For example, Ogura's US Patent No. 5,780,341 has disclosed many memorable 70-piece structures that include first-order channels in the surface of the substrate. Although the purpose of this step-shaped channel is to shoot the hot electrons to the floating pole more efficiently, the design of memory devices such as Liyi is still inadequate because it is difficult to optimize the size and manufacturing of such devices. And the% operating parameters required for efficient and reliable operation. @ '10 15 Therefore, there is a need for a non-volatile floating-gate memory cell array that can sufficiently reduce the cell size and has a better offensive rate. t > Contents of the Invention Summary of the Invention In this fortune, “Ke Xian-memory cells are used to improve simple efficiency. The 2 series is located in the first conductive semiconductor substrate and has a first and a second distinction. The non-coplanar channel region is located in the substrate and has a first non-coplanar channel. The non-coplanar channel has two parts:-[part and a = Serving. -The conductivity control pole has-a part adjacent to the part of the channel region and insulated from it to form a ~ 4 mesh layer therein. _ The floating question pole 2 is located next to the second part of the channel area and takes the insulator insulator, so that when the positive voltage of i decreases to the floating gate, one or two depleted areas have field lines. Guide the floating pole. The first-three adjacent to the inverse layer: the method of planning the element includes causing the inversion layer. An electron ^ is generated in the [area ', etc. The electron will traverse through the inversion layer. 4 The electron chirp will be accelerated by the field line and pass through the lacking area, but there will be no more or less 20 200537696 scattering, so that the electron can accelerate through the insulator and be shot to the floating gate. The first step of the method of the present invention is used to make a top view of a semiconductor substrate with isolated 5 regions. Fig. 1B is a cross-sectional view of the structure along line 1B-1B, showing the initial process steps of the present invention. Figure 1C is a top view of the structure, showing the next process steps of the structure of Figure 1B, in which an isolation region is formed. 10 Figure 1D is a cross-sectional view of the structure in Figure 1C along line 1D-1D, showing the isolation trenches in the structure. Figure 1E is a cross-sectional view of the structure in Figure 1D, showing the formation of blocks of isolation material in the isolation trenches. FIG. 1F is a cross-sectional view of the structure in FIG. 1E and shows the final structure of the isolation regions 15. Figures 2A to 2Q are cross-sectional views of the semiconductor structure in Figure 1F along the line 2A-2A, and sequentially show each of the semiconductor structures when manufacturing the non-volatile memory array of the floating gate memory cell of the present invention. Process steps. Figures 3A to 3Q are cross-sectional views of the peripheral region of the semiconductor structure. Sequences 20 show the steps of the semiconductor structure when manufacturing the non-volatile memory array of the floating gate memory cell of the present invention. Figure 4 is a top view of a memory cell array of the present invention. 5A to 5J are cross-sectional views of the semiconductor structure in FIG. 1F along the line 2A-2A, and sequentially show the steps of the 2005 2005696696 example of the first method of manufacturing the semiconductor structure of the present invention. 6A to 6H are cross-sectional views of the semiconductor structure in FIG. 2B, and each step of the second variation manufacturing method embodiment of the semiconductor structure is sequentially shown. 7A to 7G are cross-sectional views of the isolation structure of the semiconductor structure in FIG. 3B, which sequentially show the steps of the second variation of the manufacturing method embodiment of the structure. 8A to 8D are cross-sectional views of the semiconductor structure in FIG. 2B, and each step of the third variation of the manufacturing method embodiment of the structure is sequentially shown. 9A to 9D are cross-sectional views of the isolation region of the semiconductor structure in FIG. 3B. The steps of the third variation of the manufacturing method of the structure are sequentially shown. 10 Figures 10A ~ 1 (> B are partial cross-sectional views of conventional flash and EPROM non-volatile memory cells and their planning mechanisms, respectively. Figure 10C is part of the non-volatile memory cells of the present invention. Sectional view and its planning mechanism. [Embodiment] 15 Detailed description of the preferred embodiment The method of the present invention is shown in Figures 1A to 1F and Figures 2A to 2Q (showing the fabrication of the memory cell array of the present invention Steps), and FIGS. 3A to 3Q (showing steps for manufacturing the peripheral region of the semiconductor structure). The method starts with a semiconductor substrate 10, which is preferably p-type, and is a practice in this field. The thickness of each layer described below will depend on the design rules and process technology generation. The ones described here are 0.10 micron process. However, professionals should understand that the present invention is not limited to any Specific process technology generation, or any specific value of any process parameter described later. ^ Isolation zone formation ^ 200537696 Figures 1A to IF show a conventional STI method of forming an isolation zone on a substrate. See Section 1A Figure, which shows a semiconductor substrate 10 (or half The top plan view of the well is preferably p-shaped and is known in the art. The first and second material layers 12 and 14 are fabricated (eg, grown or deposited) on the 5 substrate. For example, the first layer 12 may be silicon dioxide (hereinafter referred to as “oxide”), which is fabricated by any conventional technique such as an oxidation method or an oxide deposition method (such as chemical vapor deposition or CVD method). On the substrate 10 to a thickness of about 50 to 150 A. Nitrogen-doped oxide or other insulating dielectrics may also be used. The second layer 14 may be silicon nitride (hereinafter referred to as "nitride") 10 is preferably formed by CVD or PECVD on the oxide layer 12 to a thickness of about 1000 to 5000 A. Figure 1B shows a cross-sectional view of the formed structure. When the first and second layers After 12 and 14 have been made, an appropriate photoresist material 16 will be placed on the nitride layer 14 and a masking step will be performed 15 to selectively select certain areas (grooves extending in the Y or straight direction) The photoresist material is removed from the belt as shown in FIG. 1C. Where the photoresist material 16 is removed, the exposed nitride is The layer 14 and the oxide layer 12 are etched along the stripe 18 using standard post-etching techniques (ie, anisotropic nitride and oxide / dielectric etching processes), and trenches 20 are formed in the structure. The distance 20 between the ribs 18 can be minimized to the smallest lithographic structure of the process used. A silicon etching process will be used to extend the trenches 20 and the like down to the Shixi substrate. 10 (for example, a depth of about 500 A to several micrometers), as shown in Figure 1D. Where the photoresist 16 has not been removed, the nitride layer 14 and the oxide layer 2 are all retained. The completed structure is shown in Figure 1D, and will now form an active area 12 200537696 22 and an isolating area 24. This structure will be further processed to remove the remaining photoresist 16. Riding, an isolation material such as-oxidized stone will be made in these grooves 20, which is first deposited-a thick oxide layer, and then chemical mechanical polishing or engraving (using 5 gaseous material layer) 14 is used as the remaining stop layer) to remove the oxide layer other than the oxide block 26 in each trench 20, as shown in FIG. 1E. The remaining nitride and oxide layers 14/12 are removed using a nitride / oxide etch method, leaving STI oxide blocks 26 and the like extending along the isolation regions 24, as shown in FIG. 1F. 10 The aforementioned STI isolation method is a preferred method for forming each isolation region 24. However, the conventional LOCOS isolation method (for example, recessed LOCOS, polycrystalline silicon buffered LOCOS, etc.) can also be used, in which the trenches 20 may not protrude into the substrate, and the isolation material must be set. On the surface of the substrate of the stripe regions 18. Figures 1A to 1F show the memory cell array area of the substrate, in which the memory cells that are traveling straight will be made in the active areas 22 and separated by the isolation areas 24. Please note that the substrate 10 also includes at least one peripheral region 28, in which a control circuit is provided to operate a memory cell located in the memory cell array region. Preferably, the isolation blocks 26 can be similarly formed in the peripheral region 28 in the above-mentioned STI or LOCOS manufacturing method. 20 ~ Formation of memory cells ~ The structure shown in Figure 1F is further processed as described below. Figures 2A to 2Q are cross-sectional views of the structure within the active area 22 as viewed perpendicular to Figure 1F (along lines 2A-2A of Figures 1C and 1F), and Figures 3A to 3Q are peripheral areas 28 The structural cross-sectional views in Fig. 2 are the subsequent steps of the method of the present invention performed simultaneously in the area of the two kinds of 13 200537696. -The insulating layer 3G (preferably an oxide or a nitrogen-doped oxide) is first covered on the substrate 10, as shown in Figs. 2A and 3A. At this time, the active region portion of the substrate 10 may be doped, and the cell array portion of the memory device is better controlled independently than the peripheral region. These hybridizations are commonly referred to as tritium implants or cell well implants, which are known techniques. When implanted here, the peripheral region will be protected by a photoresist layer, which is deposited on the entire structure, and only removed from the memory cell array region of the substrate. Alas, a thick layer of hard cover material 32, such as nitride, is coated on the oxide layer 30 (for example, about 3500 A thick). A plurality of parallel second trenches 34 are formed on the nitride layer 32. A photoresist (masking) material can be laid on the nitride layer 32 first, and then a masking step is performed to select the The parallel ribbon region removes the photoresist material. An anisotropic nitride etch will be used to remove the exposed portion of the nitride layer 32 in the ribbon region, leaving a second trench 34 and the like extending downward 15 and exposing the oxide layer 30. When the photoresist is removed, an anisotropic oxide #etch will be used to remove the exposed portion of the oxide layer 30, so that the second trench 34 and the like extend downward to the substrate 10. The anisotropic post-etching process of Yiyi Shixi will be used to extend the second trenches 34 in each active region 22 down into the substrate 10 (for example, down to a depth of about a fine texture size, With 200.15μm technology, about 500 people to several microns). Alternatively, the photoresist may be removed after the second trench 34 is formed in the substrate 10. The active area 22 and the peripheral area 28 thus produced are shown in Figs. 2B and 3B, respectively. Then a layer of insulating material 36 (preferably using a thermal oxidation method or a CVD oxide method) will be formed along the exposed silicon in the second trench 34, which will constitute the bottom and lower sidewalls of the 200537696 second trench 34 (for example, (Approximately 60 ~ 150). A thick layer of polycrystalline stone 38a will be overlaid on the structure and will fill the second trench 34. The polycrystalline silicon layer 38 can be doped by an ion implantation method or an in-situ doped polycrystalline silicon method (e.g., η). The active area 22 and the peripheral area 28 thus produced are shown in Figs. 2C and 3C. A polycrystalline stone lithography method (for example, a CMP method using the nitride layer 32 as an etch stop layer) will be used to remove the polycrystalline silicon layer% and leave the polycrystalline silicon block 40 remaining in the second trench 34. A controlled polysilicon etch will be used to reduce the height of the polycrystalline silicon blocks 40, so that the tops of the polycrystalline silicon blocks 40 are higher than the surface of the substrate 10, but lower than the STI oxide in the isolation region 24. The top surface of the block 26 is shown in Figs. 2D and 3D. Another alternative polysilicon etching process is performed to create a slope portion 42 on the top surface of the polycrystalline silicon block 40 (adjacent to the side wall of the second trench), as shown in FIG. 2E. A thermal oxidation method will be used to form or strengthen the tips of the slope portions 42 15, which will oxidize the exposed top surface of the polycrystalline silicon block 40 (and form an oxide layer 46 thereon), as shown in FIG. 2F . An oxide spacer 48A is formed along the sidewall of the second trench 34. The formation of these spacers is a conventional technique, which involves depositing a material on the profile of a structure, and then performing an anisotropic etching to remove the material from the horizontal surface of the structure, so that 2 〇Remains substantially unchanged on the vertical surface of the structure (and has a rounded top surface). The seeker 48 is made by depositing an oxide on the structure (for example, about 300 to 1000 A thick) and then applying an anisotropic oxide for 14 minutes. The oxide etch also removes the central portion of the oxide layer 46 in each second trench 34. The surrounding area 28 will remain unaffected. The active area 22 and the peripheral area 28 formed in 15 200537696 in this way are shown in the 2G and 3G diagrams. An anisotropic polycrystalline silicon etch combined with some oxide etch (the height of the oxide can be adjusted along the trench 34) will be performed, which will remove the poly silicon block 40 is not protected by the oxide spacer 48 And a pair of opposite polycrystalline silicon blocks 40a are left in each of the 35th and second trenches 34, as shown in FIG. 2H. An insulator deposition and anisotropic etching back process is used to form an insulating layer 50 along the exposed side of the polycrystalline silicon block 40a in the second trench 34. The insulating material may be any insulating material (for example, 0N0, ie, oxide / nitride / oxide, or other dielectric materials). Preferably, the insulating material is an oxide, so that the oxide deposition / etching process can also thicken the spacers 48 and allow the exposed portion of the oxide layer 36 at the bottom of each second trench 34 to be thickened. The substrate 10 is removed and exposed, as shown in FIGS. 21 and 31. Depending on the shape of the substrate 10, suitable ion implantation may include arsenic, phosphorus, boron, and / or antimony (and possibly annealed) will be spread over the substrate surface 15 and in the second groove 34 The bottom exposed substrate portion forms a first (source) region 52. The source regions 52 are aligned with the second trench 34 by themselves, and have a second electrical property (for example, N-type) ', which is different from the first conductivity (for example, P-type) of the substrate. The plasma does not have much effect on the hydride layer 32. The active area 22 and the peripheral area 28 thus produced are shown in Figs. 2J and 3J. A polycrystalline silicon deposition step, followed by a polycrystalline silicon CMP etch (using the vapor layer 32 as an etch stop layer), will be used to fill the second trench 34 with the polycrystalline silicon block 54 as shown in FIG. 2K. A further nitride etch is performed to remove the nitride layer 32, and the top edge of the polycrystalline silicon block 40a is exposed. A tunnel oxide layer 56A is formed on the exposed top edge of the polycrystalline silicon block 40a by a thermal oxidation method and / or an oxide deposition method. This oxide manufacturing step will also form an oxide layer on the exposed top surface of the polycrystalline silicon block 54 and may thicken the oxide layer 30 on the substrate 10. At this time, the active region 22 can be masked to selectively perform iliac implantation in the peripheral region ^. The active area 22 and the peripheral area 28 5 made by Shikou are shown in Figures 2L and 3L. The oxide layer 30 can be used as a gate oxide of a memory cell in the active region and a control circuit in the peripheral region. For each device, the thickness of the gate oxide determines its maximum operating voltage. Therefore, if it is necessary to make certain control circuits operate at a voltage different from that of the memory cell or other devices of the control circuit, the thickness of the gate oxide 30 can be corrected at this point in the process. Merely by way of example and not limitation, a photoresist 60 may be placed on the structure, and then a masking step may be used to selectively remove a portion of the photoresist in the peripheral region and expose a portion of the oxide layer. 3〇. The 30 part of the exposed oxide layer may be thinned (for example, by using a controlled etching method), or replaced by an oxide layer 30a having a desired thickness of 15 (for example, by using oxide etching and deposition), As shown in Figure 2M, 3M. After removing the photoresist 60, a polycrystalline silicon deposition step is used to form a polycrystalline silicon layer 62 (e.g., about 5,000 to 3,000 people thick) on the structure. The photoresist deposition and masking steps are used to form 20 photoresist blocks 64 on the polycrystalline debris layer 28 in the peripheral region 28, as shown in Figures 2N and 3N. Then an anisotropic polycrystalline stone will be used in the rest of the evening to remove the debris 66 ′ beside the photoresist block 64 (in the peripheral region 28) and the adjoining emulsion spacer 48 (in the active region). Region 22) other than the polycrystalline silicon spacer 68 and the like. Appropriate ion implantation (and annealing) will be used to make each of these devices a second (drain) in the active region of the substrate 17 200537696 region 70 and source / drain region 72 in the peripheral region 28 / 74 and so on. The active area 22 and the peripheral area 28 thus produced are shown in Figs. After the photoresist block 64 is removed, the insulating spacer 76 is made by depositing an insulating material and anisotropic etching (such as nitride or oxide), and abuts the poly 5 silicon spacer 68, the oxide spacer 48 and polycrystalline silicon block 66. Rhenium performs a metal deposition step, and a metal such as tungsten, metal, titanium, nickel, platinum, or molybdenum is deposited on the active region 22 and the peripheral region 28. The structure is annealed so that the hot metal can flow into the exposed tops of the polycrystalline silicon spacers 68 and the polycrystalline silicon blocks 66, etc., and a conductive layer of metallized polycrystalline silicon 78 (polyolide) is formed thereon. ’Metal that accumulates on the rest of the structure is removed using the metal surname method. The active area 22 and the peripheral area 28 thus produced are shown in Figs. 21 &31; and 31 >. An insulating material 80, such as BPSG or oxide hafnium, is applied to the entire structure. A masking step is performed to define an etched area on the drain region 70/74. The insulating material 80 in the masked area will be selected to form I5 as a contact hole extending down to the electrodeless region 70/74. These contact holes will be filled-a conductive metal (such as a crane) to form a metal contact 82 and be electrically connected to the non-polar region 70/74. The drain line contact 84/86 (such as aluminum, copper, etc.) will be added to the active area M and the surrounding area by the metal covering the insulating material 80, and all contacts in the active area 22 will be added. Object 82 (that is, the 7G drain region) is all connected at 20, and the active cell memory cell structure after the 7-keys of the ZigZee polar region in the surrounding frame is connected as shown in the figure. As shown in the figure, the final peripheral area control circuit structure is shown in Figure 3Q. As shown in Figure 2Q, the manufacturing method of the present invention will form pairs of memory cells' which are mirror images of each other, and each side of the polycrystalline material 54 is provided with a memory cell 200537696. In each-memory cell, the first region 52 and the second region 70 will form a source region and a drain region, respectively (however a professional should know that the source and drain are interchangeable during operation). The polycrystalline fragment 40a will constitute a floating gate, and the multi-day stone evening object 68 will constitute a control pole. The channel region 90 of each memory cell is formed in the surface portion of the substrate, and is between source 52 and drain%. Each -channel region 90 includes two parts connected at approximately right angles, and its-(vertical) part 92 will extend along the vertical wall of the filled second trench 34, and the (horizontal) ^ 94 The side wall and the drain region of the filled second trench 34 are extended. Each pair of memory cells will share a common source region 52, which is located under the filled second trench 34, and will be electrically connected to the polycrystalline stone block 54. Similarly, each drain region 70 will be shared between adjacent memory cells of different mirror groups. FIG. 4 is a top view of the aforementioned structure, which shows the connection between the bit line 84 and the drain region 70, and the control gate ⑽, etc., which continuously form a work (sub) line to extend the teeth. Pass these active and isolated areas 24. The above manufacturing method does not cause the source region 52 extending through the isolation region 24 (this can be easily achieved by deep implantation, or can be partially removed by the isolation regions of the second trenches 34 before ion implantation). To achieve this, drop the material of the sm euphemum). However, the polycrystalline stone blocks (which are in electrical contact with the source region 52) will continuously pass through these isolation regions and adjoin the main 20 mobile regions, and will form source lines, etc. each row of memory cells All source regions 52 of a pair are electrically connected together. The floating gate 40a is disposed in the second trench 34, and each floating gate faces a vertical portion 92 of a channel region, a source region 52, and a polycrystalline silicon block 54 and is insulated therefrom. Each floating gate 40a includes a top projecting above the surface of the 19 200537696 substrate and ending at an end edge 96, which will oppose and insulate a control gate 68, so it can provide a pass through the oxide The Fowler-Nordheim tunneling path for layer 56. The polycrystalline silicon blocks 54 each extend along the floating gate 40a and are insulated from it (with an oxide layer 50) to enhance the voltage lightening of 5 of them. There can only be some vertical overlap between any control gate and floating gate ', so that too much capacitive coupling between them will not hinder the operation of memory cells as described later. That is to say, if there is any vertical overlap between the control pole and the floating pole, the control gate must never extend too far (in the horizontal direction) enough to completely overlap (in the vertical direction). The floating gate. ~ Operation of Memory Cells ~ Operation of Memory Cells will now be explained. The operation and operating principle of these memory cells are also disclosed in the US Patent No. 5572054, the content of which is hereby incorporated by reference, which is related to the Yi 15 with a floating gate and a control gate §Remember the operation and operating principle of the cell, and the floating gate that can control the gate penetration, and the memory cell array made. When erasing a selected memory cell in any given active area 22, a ground voltage is applied to its source 50 and drain 70. A high positive voltage (eg + 7V ~ + 15V) will be applied to the control gate 68. 20 electrons on the floating gate 40a can be injected into the tunnel by the Fowler-Nordheim tunneling mechanism, and the top of the net moving gate 40a (mainly by the edge 96) passes through the oxidation The physical layer is allowed to enter the control gate 68, so that the floating gate 40a is positively charged. This tunneling effect can be enhanced by the sharpness of the end edge 96. It should be noted that, since the control gates 68 are continuous control (word) lines to extend through the active recesses and the 20 200537696 isolation zone, one memory cell in each active zone will be “erased” at the same time. > Xiao 0 When a selected memory cell needs to be planned, a small voltage (for example, 0. 5 to 2. 0V) will be applied to its drain region 70. The positive voltage level near the threshold voltage of the MOS structure (about 70 + 0 above the drain node). 2 ~ IV) will be applied to its control gate 68. A positive high voltage (for example, about 5 to 10 V) is applied to the source region 52 thereof. Because the floating gate 40 is highly capacitive, it is at the same potential as the source region 52, so the floating gate 40 will "seem like + 4 ~ + 8V This will form a deep 10 empty region 250 in the substrate 10. Also, since the voltage of the floating gate 40 is higher than the voltage on the control gate 68, the field line will be floated by the floating The gate 40 is extended to the control gate 68, as shown in FIG. 10C. And, because a positive voltage is applied to the control gate 68, an inversion layer 280 is formed in the substrate 10. The The inversion layer 280 is connected to the drain region 70. Therefore, a planned electron flow 15 will be caused in the drain region 70 (as is known, the current will flow in a direction opposite to the electron flow). These electrons will run through the The inversion layer 280 reaches an extrusion point 295. At this extrusion point 295 (which is at or inside the empty region 250), these electrons will be accelerated by the field lines from the floating gate 40. It can be seen in the figure ico that, because the field lines emitted by the floating gate 40 will lead to the control gate 68, these electrons will only follow the direction of the field line that is larger than 20 Acceleration. When they are accelerated to obtain energy, electrons with sufficient energy will pass through the insulating layer 36 and be injected onto the floating gate 40. Therefore, unlike the planning mechanism of the conventional technology, the empty area 250 The electrons in it do not need to be scattered to cause a momentum component in the approximate direction of the floating gate 40. In fact, scattering is not appropriate because it will cause the electrons at 21 200537696 extrusion point 295 to actually face the floating gate. Momentum and energy are lost in the direction of 40. Therefore, in the planning mechanism of the present invention, electrons in the empty region will be injected into the floating gate 40 with little or no scattering. As for non-selected memory cells, it is more Low or ground potentials will be applied to the source / drain regions 52/70 and control gate 68 of each memory cell row / column that does not contain the selected memory cell. Therefore, only the selected The memory cells in the rows / columns will be planned. Ejecting electrons out of the floating gate 40a will continue until the charge on the floating gate 40a is reduced to not maintain a surface potential of 10% in the vertical channel region. To generate thermionic electrons At this time, the electrons or negative charges on the floating gate electrode 4 will reduce the electron flow from the drain region 70 to the floating gate electrode 40a. Finally, when reading a selected memory cell, The ground potential will be applied to its source region 52. A read voltage (for example, about 0.5 ~ 2ν) will be applied to its drain region 70, and about 1 to 4V (depending on the power supply voltage of the device) (Fixed) will be applied to its control gate 68. If the floating gate 4 is positively charged (that is, it will release electrons), then the vertical channel area portion 92 (close to the floating gate 4a) When the control gate 68 is boosted to the read potential, the horizontal channel region portion 94 (close to the control gate 68) will also be turned on. Therefore, the entire channel 20 region 90 will be turned on, so that electrons can flow from the source region 52 to the non-polar region%. The current thus sensed is a "1" state. Conversely, if the floating gate 40a is negatively charged, the vertical channel region portion 92 will be weakly turned on or completely closed. Even when the control asks that the drain region 70 is boosted to the read potential, little or no current will flow through the vertical channel region portion 92. In this case, compared to "丨, the current will be very small, or there will be no current at all. In this way, the memory cell will be measured as the" 0 "state. The ground potential will be The source / impulse regions 52/70 and the control gate 68 are applied to non-selected rows, so only the selected memory cell can be read. The memory cell array contains peripheral circuits, which contain traditional column addresses. Decoding circuits, row address decoding circuits, sense amplifier circuits, output buffer circuits, and input buffer circuits are all known in the art. The present invention can provide a memory with reduced size and better planning efficiency. Cell array. The size of the memory cell will be greatly reduced because its source region 52 is buried in the substrate 10 and will be aligned with the second trench by itself, so the space will not be affected by lithographic generation and contact. It is wasteful due to the limitation of the alignment of the object and the integrity of the contact object. Each floating gate 40a has a lower portion disposed in the first groove 34 in the substrate 10, and can receive tunneling during the planning operation. Electrons, and can turn on the vertical channel area during the fetch operation Portion 92. Each floating gate 40a also has an upper portion that protrudes outside the second groove of the substrate, and ends at a pair of end lines to the control gate, which can be used for Fowler during the erasing operation- Nordheim's tunneling operation. The planning efficiency will also be greatly increased in the method of the present invention, because the electrons will be accelerated by the field lines without self-floating gates, and there will be little or no collisional dissociation. To make electrons lose kinetic energy or energy. The estimated planning efficiency (the number of emitted electrons compared to the total number of electrons) of the conventional clothes shown in Figure 1GA is about 1/1000. However, in the present invention, its planning The efficiency will be increased by 10 times or even 100 times, and almost all electrons will be emitted onto the floating gate. 23 200537696 According to the present invention, the polycrystalline silicon block is transmitted between each floating gate 40a and the corresponding source region 52. 54 (connected to the source region 52) will also have stronger voltage coupling. At the same time, there will be a lower voltage between the floating gate 40a and the control gate 68. In addition, the source region 52 and The drain region 70 is separated vertically and horizontally, and 5 will be easier to optimize reliability The number does not affect the cell size. ~ First modified embodiment ~ Figures 5A to 5J show a cross-sectional view of the structure of the active cell 22 in the active region 22, which is one of the methods for fabricating a memory cell array of the present invention. The structure of the first variation of the first manufacturing method is shown in FIG. 2A. For simplicity, the same elements as those in the aforementioned eleventh embodiment will be labeled with the same numbers. The thick nitride layer 32 (for example, about 1000 ~ 10000 people thick) will be covered on the oxide layer 30. Parallel second trenches 34 and the like will be provided on the nitride layer 32, which is first coated on the gas layer 32. Photoresist (masking) material, followed by a masking step to remove the photoresist material 15 from the selected parallel stripe region. An anisotropic nitride etch is used to remove these patterns The exposed portion of the nitride layer 32 in the band region, while leaving the second trench 34 and the like extending downward to the oxide layer 30 and exposing it. After the photoresist is removed, the oxide spacer 102 is formed in the second trench 34 by an oxide deposition step and then an oxide anisotropic etching step. A part of the oxide 20 layer 30 in the center of the bottom of the second trench is also removed in this oxide remaining step, and the substrate 10 underneath is exposed. The structure thus produced is shown in Fig. 5A. A silicon anisotropic etching process is used to extend the second trenches 34 in each active region 22 down to the substrate 10 (for example, the technique can be extended down to about 500 μA with a technique of 0.5 μm). Micron depth). The degree of the second trench 24 200537696 34 in the substrate 10 will form a space between the oxide spacers 102. Appropriate ion implantation (and possibly annealing) will occur on the surface of the structure, and the first (source) regions 52 are formed in the exposed substrate portion at the bottom of the second trenches 34. The source regions 52 are aligned with the second trench 34 by themselves, and have the second 5 types of electrical properties (for example, N-type), which are different from the first conductivity of the substrate (for example, P-type). ). The plasma does not have much influence on the nitride layer 32. The structure thus produced is shown in Figure 5B. The hafnium oxide layer 100 is provided on the exposed silicon substrate 10 (forming the bottom and lower side walls of the second trench 34), and it is preferably made by a thermal oxidation method (e.g., about 70 to 150) Into the thick). A thick polycrystalline silicon layer is deposited on the structure and fills the second trenches 34 and the like. A polycrystalline silicon CMP process using the nitride layer 32 as an etch stop layer will be used to remove the polycrystalline silicon layer, leaving only the stone block 54 remaining in the second trench 34. A controlled polycrystalline stone engraved seal will be used to lower the height of the polycrystalline stone block 54 below the top surface of the nitride layer 32. An optional oxide layer 104 (e.g., by thermal oxidation) is formed on the polycrystalline silicon block 54. A thin nitride layer 106 may be deposited on the structure. The nitride layer 1 is then removed by a masking step and a nitride leave, but remains on the oxide layer 104 and the polycrystalline silicon block 54. Serving. This can be made by depositing a photoresist on the structure and then leaving only 20 photoresist in the second trench 34 over the deposited nitride with controlled exposure. The structure thus produced is shown in Fig. 5C. Using the nitride layer 106 as a mask, a dry and / or wet oxide etch is used to remove the oxide spacers 102. A thermal oxidation process will be performed, and the exposed sides of the polycrystalline stone block 54 and the substrate will be exposed. 25 200537696 ^ Surface layer 1Q8. ―Anisotropic oxides are used to remove the oxide layer formed on the substrate. The structure thus produced is shown in Fig. 5D. Using the nitride layer 32 and 1G6 as a mask, the secret engraving will be used to expose the inside of the fifth trench 34; ^ the substrate ㈣, so that it is lowered to be flush with the bottom of the polycrystalline stone block 54 块degree. The additional ion implantation (and possibly annealing) will be used to expand the source region 52 under the second trench 34, as shown in Figure 5E. The first insulating layer no is preferably formed on the side wall of the second trench by a cVDa product method of a halide (for example, 70 to 150 mm thick). A thick polycrystalline silicon layer 10 will cover 5 and fill the second trench 34 on the structure. Then, a polycrystalline silicon block is formed by a CMP polycrystalline silicon etch (using the nitride layer 32 as an etch stop layer) and an additional polycrystalline silicon etch. 40a, etc., whose top is lower than the STI oxide block 26 in the isolation region 24. The oblique etching or oxidation method is used to sharpen the end edge 96 of the top of the polycrystalline silicon block 40a. The oxide deposition and etch-back process is used to fill the top of the second trench 34 with oxide U2, which seals the polycrystalline silicon block 40a and creates an oxide spacer on top of the second trench 34. The structure made in this way is shown in Fig. 5F, which will contain three polycrystalline silicon blocks in each second trench, which will be surrounded and sealed by the oxide. The polycrystalline silicon block 54 will be in electrical contact with the source region 52 and interposed between a pair of polycrystalline silicon blocks 40a (they are separated from the source region 52). An optional polycrystalline silicon block 54 extension can be performed in the following manner ... The nitride layer 106 and oxide 104 are first removed by controlled nitride and oxide etching, and then completed by a polycrystalline silicon deposition and polycrystalline silicon etching back. An optional polycrystalline stone engraving can be used to form a protective oxide layer on the polycrystalline silicon block 54 in a one-oxide process before it is used to lower the polycrystalline silicon block. The new top surface, as shown in Figure 5G.—Nitride money engraving will be used to remove the gas layer 32. Then a controlled oxide engraving will be used to collapse the exposed oxide by about 10 to Hundreds of A, followed by a thermal oxidation process to reform the oxygen pendant layers 30 and 114 and create a recess in the oxide surrounding the top of the polycrystalline stone 40a. The resulting structure is shown in Figure 5H A polycrystalline silicon deposition and anisotropic polycrystalline silicon etching will be used to make polycrystalline spacers 68 adjacent to the oxide spacer 112. Appropriate ion implantation (and annealing) will be used to form the Second (drain) region. Insulating spacers 76 嗣 can be made by insulating material deposition and anisotropic etching (such as nitride or oxide), and will rely on polycrystalline silicon spacers 68. A metal deposition step 沉积Will be carried out, a metal such as tungsten, cobalt, titanium, nickel, platinum The structure will be annealed to cause hot metal to flow into the exposed top of the polycrystalline silicon spacer 68 to form a polycrystalline silicon metallization 78 thereon. 15 The remaining metal deposited on the remaining structure will be replaced with a metal residue. The structure is made as shown in FIG. 51. The insulating material 80, the metal contact 82, and the drain line contact 84 are formed as shown in FIG. 2Q to form the first structure. The final structure shown in Figure 5J. The advantage of this embodiment is that solid source line polycrystalline silicon blocks 54 20 and the like can be easily made and brought into electrical contact with the source region 52 and so on. Furthermore, the polycrystalline silicon block 54 is used to separate the silicon substrate The fabricated floating gate polycrystalline silicon block 40a, etc., will make it easier to prevent short circuits between these floating gates. ~ Second modified embodiment ~ Figures 6A to 6G and Figures 7A to 7G are shown The second variation method for manufacturing the 27 200537696 memory cell array of the present invention is produced. The second variation method starts from the structure shown in FIGS. 2B and 3B, but it is not necessary to make the oxide under the nitride layer 32. Material layer 30, because the oxide layer 30 is The middle system is optional. After the insulating material 36 is made as shown in FIG. 2C, the ion implantation (and 5 may be annealed) process will be used in the exposed substrate portion at the bottom of the second trench 34. A first (source) region 52 is formed. A thin polycrystalline silicon layer 118 嗣 will be coated on the structure, as shown in Figures 68 and 78. The polycrystalline silicon layer n8 can be ion implanted or an in-situ method Doped (such as n +). The thickness of the polycrystalline silicon layer 118 is preferably about 50 ~ 500A, which will determine the actual thickness of the 10 floating gate of the final memory cell device. The oxide will be covered On this structure, a planarization etching is performed (for example, using a part of the polycrystalline silicon layer 118 on the rat compound layer 32 as the CMP remainder of the etch stop layer), and the oxide block 12 is used to fill the first portion.二 槽 34。 Two trenches 34. A polysilicon etch will be performed to remove the exposed portion of the polycrystalline silicon layer 118 (the portion located on the nitride layer 32). The oxide blocks 120 are recessed downward by oxide etching to be flush with a portion of the polycrystalline silicon layer U8 remaining on the STI block 26 of the isolation region 24 (for example, in the non-active region on the STI block 26). Part of the polycrystalline stone layer 118 is used as an oxide coin engraved stop layer. The structure of the active area and the surrounding area is shown in Figures 6B and 7B. Different polycrystalline silicon layers M ′ at the profile level will be used as the stop layer in the above oxides, polycrystalline silicon oxides, oxide oxides, etc. In other words, as shown in the figure below, The stone evening layer 118 has a first portion 119a provided outside the trench 34 on the nitride layer 32. Fig. 6H is the same view as the trench 34 of Fig. 6A, but in 28 200537696 isolation region 24 and not in active In the area 22. As shown in FIG. 6H, the polycrystalline layer 118 has a second portion 119b disposed on the ST1 block 26. Therefore, the polycrystalline portion of the polycrystalline layer 119a will be located higher than the 119b. At the structural level, in order to make the oxide block 120 in the active region, the first oxide etch will be performed using the polycrystalline silicon layer portion 5 119a as an etch stop layer, and The second trench 34 in the active region 22 and the isolation region 24 is filled in one place. Subsequent oxide names will use 11% of the polycrystalline silicon layer as an etch stop layer to set the oxide block 120 in the active region. And the polycrystalline silicon layer 118 in the isolation region 24 is completely exposed. A polycrystalline silicon etch will be used to remove the exposed part of the polycrystalline silicon layer 118 (ie, along the second trench 34 in the active region). Top, and above the STI block 26 in the isolation region 24). An oxide process is performed, and an oxide block 122, etc. is formed on the exposed end of the polycrystalline silicon layer 118. The dielectric spacer 124, such as oxide, may be oxidized The material is deposited and etched inside the second trench 34, and covers 15 over the oxide block 122 and partially covers the oxide block 120, as shown in FIG. 6C. Another oxide etch may be used The exposed central portion of the oxide block 12 is removed (that is, between the spacers 124, which is etched by the oxide to reduce the southness), and the polycrystalline silicon layer 118 exposed in the center of the second trench 34 is removed. Polycrystalline silicon etching and monoxide etching will be successively removed to the second The exposed portions of the polycrystalline silicon layer 118 and the oxide layer 36 in the center of the bottom of the trench 34 2 are exposed to W parts of the substrate. The structure thus produced is shown in Figures 7 and 7. The dielectric spacer 125 will be The nitride (or oxide) is deposited on the structure, and then anisotropic nitride etching is performed to form the second trenches 34. The second trenches 34 may be deposited using a polycrystalline silicon. And CMP etch 29 200537696 back process (using nitride layer 32 as a money stop layer) to fill the polycrystalline silicon block 54 as shown in Figure 6E. The nitride layer 32 will be nitride etched by the active area 22 and isolated Zone 24 and peripheral zone 28 are removed. The ytterbium tunnel oxide layer 56 is formed on the exposed top edge of the polycrystalline silicon layer 1185 by thermal oxidation and / or oxide deposition. Since the oxide layer 32 is not formed earlier in this process, the oxide layer 56 will also extend over the exposed portion of the substrate 10. This oxide formation step also forms an oxide layer 58 on the exposed top surface of the polycrystalline silicon block 54. Optional% implantation can also be performed in the peripheral area 28 by masking the active area 22 at this time. The active area 22 and the peripheral area 28 thus produced are shown in FIGS. 6F 10 and 7F. For example, the remaining processing steps of uranium described in Figures 2M to 2Q will be performed on the structures shown in Figures 6F and 7F, and the final active area memory cell structure will be shown in Figure 6G. And the final peripheral area control circuit structure is shown in Figure 7G. 15 As shown in Fig. 6G, the L-shaped polycrystalline layer 118 will form the floating interpole of each memory cell. Each floating gate 118 includes a pair of orthogonal elongated portions 118a / l 18b and the like joined together at their adjacent ends. The floating gate portion ⑽ will extend along the side wall of the substrate of the second trench 34 to be insulated from it, and a button 118 is provided to extend above the surface of the substrate. The part of the floating gate extends along the bottom substrate of the first trench 34 and is insulated from it (ie, it is provided on the source region 52 and insulated from it). The control gate spacer 68 has a first portion laterally abutted and insulated from the floating gate top section 118c. And a second part is provided above the top section and insulated from it. The top cymbal has a sharp end 96 which ends and is insulated from the control closed pole, so it can form a blessing between the floating gate 30 200537696 and the control gate 68. Le-Nordheim tunneling path. A second variation of the present invention provides a memory cell array, which can reduce the size and has better planning efficiency. The memory cell size will be reduced by 5 because the source region 52 is buried inside the substrate 10 and aligned with the trench 34 by itself, so its space will not be affected by lithography generation, contact object alignment, and contact. Constraints such as the integrity of the object are wasted. The planning efficiency can be greatly enhanced by aiming the horizontal portion of the channel area 90 at the floating gate 118. The L-shaped floating gate structure of the present invention will have many advantages. Because these floating gate portions 10 parts of llSa / llSb are made of a thin layer of polycrystalline stone material, and its narrow tip can strengthen the Fowler-Nordheim tunnel control gate 68. It does not require large-scale Thermal oxidation step to make sharp edges to enhance tunneling. Near the horizontal floating gate portion 118b and the source region 52 (separated only by the thin oxide layer%), each floating gate 118 and the corresponding source region 52 will also have an enhanced ratio of 15%. Because the floating gate top section U8c is made by the oxide gate method and is made by depositing a thin layer of polycrystalline stone, Heavier doped polysilicon can be used to prevent the polysilicon starvation problem during operation + and ^, so that the source region 52 and the drain region 7Q are vertically and horizontally grounded. It is easier to optimize reliability parameters without affecting the cell The element size ⑴θ can be known from this embodiment that the voltage consumption between the floating gate 118 and the source region 52 is sufficient. Enough, so it is not necessary to merge with the extra electric dust surface of the polycrystalline stone block 54. It is not necessary. The polycrystalline stone block 54 in this embodiment is mainly used to align the source region in each column with 7L. 52 are electrically connected together. Therefore, the polycrystalline stone block 54 can be omitted in this embodiment, as long as there is an electricity 31 200537696 similar to the contact 82, and the contact is not extended down to each source region 52. Please note that the polycrystalline silicon blocks 54 must be insulated from the substrate when passing through the isolation areas, so as not to cause a short circuit with the substrate. This can be compared by the depth of §11 block 26 in the isolation areas. The bottom of the first trench 34 is deeper, or it can be achieved that the material of the §11 block 26 can be etched more slowly than the material used to form the oxide block 120. ~ Third Variation Example ~ 8A Figures 8D and 9A to 9D show the third variation method of the present invention for fabricating a memory cell array. The third variation method starts with the structure not shown in Figures 2B and 3B. 〇: After the insulating material 10 36 is made as shown in the figure, the ion implantation (and possibly annealing) process will be used in the second trench The first (source) region 52 is formed in the exposed substrate portion at the bottom of the 34. The polysilicon spacer 126 嗣 will be changed in the second trench 34, which is a layer of polysilicon first deposited on the substrate ' Anisotropic polycrystalline silicon is used to remove the polycrystalline silicon layer except the spacers 126, as shown in Figures 8A and 9A. The height of the polycrystalline silicon 15 spacers is preferably not greater than that in the isolation region 24. STI block 26 (for example, STI block 26 in the non-active area is used as an etch stop layer), which will ensure that all polycrystalline silicon can be removed from these isolation areas. The oxide will be covered in Figure 8A / 9A On the structure, planarizing oxide etching (for example, CMP etching using the nitride layer 32 as the etch stop layer 20) is performed to fill the second trench 34 with the oxide block 128. The mono-oxide etching method is used to recess the oxide block 128 down to be flush with the top surface of the polycrystalline silicon spacer 126 (for example, using the polycrystalline silicon spacer 126 as an oxide etch stop layer). A dielectric spacer 130, such as an oxide, is formed inside the second trench 34 and the polycrystalline silicon 32 200537696 spacer 126 through an oxide deposition method and etching back, as shown in FIG. 8B.嗣 Another oxide etch will be used to remove the exposed central portion of oxide block 128 and oxide layer 36 (between the spacers 130, which will be reduced in height by this oxide #), and Exposed part of the substrate. The structure thus made is shown in Figure 8C / 9C. The remaining processing steps described previously in Figures 2K to 2Q will be performed on the structures shown in Figures 8C and 9C, resulting in a final active area memory cell structure as shown in Figure 8D. And the final peripheral area control circuit structure is shown in Figure 9D. In this embodiment, the polycrystalline silicon spacer 126 will constitute a snap gate 'which is insulated from the control gate 68 through the oxide 56. By making the floating gate into a spacer by 10 15 20, the number and / or complexity of processing steps will be reduced. These floating gate spacers 126 will each end at-sharp edges 96 'which are directly opposite and insulated from the control, so they can be formed between the floating gate and the control gate 68-available for Fowler · Norders should understand that the present invention is not limited to the above and illustrated embodiments, but can be any and all. "Please full-time headings." Grooves can also have any terminations that extend into the substrate ^ As shown in the figure, a long rectangle. Also, although the above-mentioned heterogeneous polycrystalline lysate is a conductive material that forms a memory cell, it can be appropriately mixed to understand that described in the scope of this specification and in the patent application. Cai Yueyue can be used to make non-volatile memory cell Fengyue Yuexi materials. In addition, any suitable conductive insulator of 0 to 1000 ohms can also be used to obtain silicon. Moreover, any etching material that is different from silicon monoxide or silicon) and polycrystalline silicon (or any conductor) is suitable material (or any insulating stone). In addition, according to the scope of the patent application, it can be seen that 0 is used to replace nitride Not all material steps must be performed in the order described, but in any order in which the memory cells of the present invention can be properly made. In addition, the invention described above is shown in a In the uniformly doped substrate, but if known and the present invention can also be adopted, the memory cell elements are fabricated in the well area of the substrate, and the 5 areas of the wells are doped to communicate with the Other parts of the substrate have different conductivity types. Finally, a single layer of insulating or conductive material can be made into multiple layers of these materials, and vice versa. L Schematic Illustration 3 • Figure 1A is used in The first step of the method of the present invention is to make a top view of a semiconductor substrate isolated from 10 regions. Figure 1B is a cross-sectional view of the structure along line 1B-1B, showing the initial process steps of the present invention. Figure 1C is the Top view of the structure, showing the bottom of the structure of Figure 1B During the manufacturing process, an isolation region is formed. 15 Figure 1D is a cross-sectional view of the structure in Figure 1C along the line 1D-1D, showing the isolation trench in the structure. ® Figure 1E is the structure in Figure ID Figure 1F shows the formation of blocks of isolation material in the isolation trenches. Figure 1F is a cross-sectional view of the structure in Figure 1E, showing the final structure of the isolation areas 20. Figures 2A ~ 2Q FIG. 1F is a cross-sectional view of the semiconductor structure along line 2A-2A, and sequentially shows the steps of the semiconductor structure when manufacturing the non-volatile memory array of the floating gate memory cell of the present invention. Section 3A ~ The 3Q diagram is a cross-sectional view of a peripheral region of the semiconductor structure, and sequentially 34 200537696 shows each process step of the semiconductor structure when manufacturing the non-volatile memory array of the floating gate memory cell of the present invention. The fourth diagram is The top view of the memory cell array of the invention. Figures 5A to 5J are cross-sectional views of the semiconductor structure along line 2A-2A in Figure 1F, which sequentially show a first variation of the semiconductor structure of the present invention. Figures 6A to 6H are semiconductors in Figure 2B The cross-sectional view of the structure sequentially shows the steps of the second variation of the manufacturing method of the semiconductor structure. • FIGS. 7A to 7G are 10 cross-sectional views of the isolation region of the semiconductor structure in FIG. 3B, which sequentially show the structure. The steps of the second variation of the manufacturing method embodiment. FIGS. 8A to 8D are cross-sectional views of the semiconductor structure in FIG. 2B, which sequentially show the steps of the third variation of the manufacturing method embodiment of the structure. FIGS. 9A to 9D 3B is a cross-sectional view of the isolation region of the semiconductor structure in FIG. 3B, which sequentially shows the steps of the third variation of the manufacturing method embodiment. 15 FIGS. 10A to 10B are the conventional flash memory and EPROM non-volatile memory, respectively. A partial cross-section of a cell and its planning mechanism. Figure 10C is a partial cross-sectional view of the non-volatile memory cell of the present invention and its planning mechanism. [Description of main component symbols] 10 ... semiconductor substrate 12, 100, 104, 108, 112, 114 ... oxide layer 14, 106 ... nitride layer 16, 60 ... photoresist 18 ... ribbon 35 200537696 20 ... trench 22 ... active area 24 ... isolation area 26 ... oxide block 28 ... peripheral area 30, 30a ... insulating layer (oxide) 32 ... hard cover (nitride)

34 ... Second trench 36, 80 ... Insulating material 38 ... Polycrystalline stone 40, 40a, 54, 66 ... Polycrystalline stone block 42 ... Slope portion 46, 58 ... Oxide layer 48, 102 ... oxide spacers 50, 110 ... insulating layer 52 ... source regions 56 ... with oxide layers 62, 118 ... polycrystalline silicon layers 64 ... photoresist blocks 68, 126 ... polycrystalline silicon spacers 70 ... Drain region 72/74 ... source / inverter region 76 ... insulating spacer 78 ... polycrystalline silicon metallization 36 200537696 82 ... contact 84/86 ... drain line contact 90 ... channel region 92, 118a ... vertical portion 94 , 118b ... horizontal part 96 ... edge 118c ... top section 119a ... first part

11% ... Second part 120, 122, 128 ... Oxide block 124, 125, 130 ... Dielectric spacer 200 ... Flash memory cell 210 ... Ground voltage region 220 ... High voltage region 230 ... · Floating gate 240 ... control gate 250 ... empty area 260 ... substrate 280 ... inverting layer 295 ... extrusion point 300 ... · ΕΡΙΙΟΜ cell 37

Claims (1)

200537696 X. Scope of patent application: 1. A method for electrically planning and erasing a memory device. The memory device has a substrate of a first conductive semiconductor material, and a first and second conductive device. Two sections are disposed in the substrate separately, and a non-coplanar channel region is disposed in the substrate therebetween, and the channel region has first and second parts, and a conductive control gate has a part It will be adjacent but insulated to the first part of the channel area to create an inversion layer. A floating closed electrode has a part that will be adjacent to the second part of the channel area, but insulated from it by an insulator. An empty region has field lines or the like to guide the floating gate, wherein the first region is adjacent to the inversion layer; the planning method includes: causing the inversion layer; generating an electron flow in the first region and causing the Electron current traverses the inversion layer; and by the field lines, the electron flow is accelerated through the empty region with little or no π scattering, and the electrons are accelerated through the insulator and projected on the floating gate. 2. If the method of applying for the patent scope W, the channel area of the towel has a first part of the layout along the horizontal surface and the second part of the method of applying the patent scope W in a groove 3. The channel area has an i-th part in a groove, and-the second part is arranged along the horizontal surface. If the method of applying a special object is used, its _1-part is approximately 38. 200537696 Perpendicular to the second part. 5. The method according to item 4 of the patent application, wherein the inversion layer has an extrusion point adjacent to or in the empty area, and the electron flow will begin to accelerate through the extrusion point at the extrusion point. Empty area. 39