TW565912B - Manufacturing method of flash memory - Google Patents

Abstract

A manufacturing method of memory is provided. A pad layer and a mask layer are formed on the substrate sequentially. The mask layer is patterned for forming a opening, and the pad layer exposed by the opening is removed. After a tunneling dielectric layer is formed on the bottom of the opening, a floating gate is formed on the sidewalls of the opening. The top of the floating gate is lower than the mask layer surface. After a source region is formed in the substrate, an inter-gate dielectric layer is formed in the opening and a control gate is filled in the opening. After the mask layer is removed, a gate dielectric layer is formed on substrate and a spacer is formed on the sidewalls of floating gate and control gate. A select gate is formed on the sidewalls of floating gate and control gate, a drain region is formed in the substrate of one side of select gate.

Description

565912

Technology The present invention is related to the manufacture of a main type of flash memory: the v system process, and in particular to the pre-i technology memory, as the name implies, early components. When the computer micro-processing of crying At At, the semiconductor type and operation of storing data or data are becoming more and more powerful; U Yueqiang 'dragon's process as a memory element technology "three bodies" meets this demand. The trend, the driving force behind the challenge of accumulation and accumulation has become the continuing high of semiconductor technology: for example: 'Flash memory elements have multiple times of data = =: action such as division' and the stored data is broken. Even after the electricity; M — # fc point has become a non-volatile memory element widely used in personal computers and electronic equipment. A typical flash memory device of the tray 1 is made of doped polycrystalline silicon to make a floating gate and a control gate. In addition, the gate electrode and the control gate electrode are separated by a dielectric layer @, and the floating gate electrode is separated from the base electrode & Tunnel Oxide layer. When writing / erasing data to the flash memory, the gate and source / drain regions are biased by the control gate, so that electrons are injected into the floating gate 1 or Pull the electrons out of the floating gate. When reading the data in the flash memory, f applies a working voltage to the control gate. At this time, the charged state of the floating gate will affect the opening / closing of its lower channel (Channel). Off is the basis for judging the data value "0" or "1". sweat

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^ When the memory is erased, the relative potential of the substrate and the drain gate is increased, and the tunneling effect is used to pass the gate through the tunneling oxide layer (Tunneling Oxide) and ( Source) electrode (that is, Substrate Erase or i) rain de E rase), or drain through the dielectric layer to the control gate + erase the data in the flash memory due to the The number of miles is not easy to control, so it is easy to cause the floating gate to discharge too much positive current f ', which is called excessive erasure (0ver-Erase). When this transition is too severe, even the channel under the floating gate will continue to be in a conducting state when the working voltage is controlled and applied to the data. In order to solve the problem of excessive erasure of components, the industry currently proposes three levels. High-density flash memory.

When the fast (source) electrons float from the substrate or (Source). However, the electrode discharged by the electrode with erasure phenomenon is not misjudged. Because of

Please refer to Figure 1. This flash memory is on the substrate 丨 (), and also has a trailing oxide layer 102 and a floating gate! 04. The inter-gate dielectric layer 106, the control electrode 108 and the top cover layer 110, and the floating gate 104 are located below the control gate 108. After the foreign gate 104 and the control gate 108 are formed, impurities are implanted into the substrate 10Q to form a source region 1 12. After the source region 丨 2 is formed, a gap wall 丨 4 is formed on the side wall of the floating gate 104 and the control gate 108. Next, a polycrystalline silicon layer (not shown) is deposited on the substrate 100, and then the polycrystalline silicon layer is etched by anisotropic etching to form a select gate on the sidewall of the spacer 14 116. Then, a drain region 118 is formed in the bottom 100 on the side of the selection gate 116. I Floating gate 104 is controlled. The manufacturing process is relatively. In the flash memory manufacturing process described above, gate 1 106 is defined using a lithographic etching process.

V. Description of the invention (3) It is complicated and there is a problem of so-called alignment control. Under the trend of piece product accumulation, according to the design ’s current, the polar surface between the floating floating pole and the control pole

Rat10, the larger the GC, the work required for its operation to improve component performance. To increase the inter-electrode coupling chamber, the lower the ratio, the higher the ratio. The method of GCI0 includes increasing the capacitance of the Gak Coupie oxide layer. Among them, the capacitance of the electrical layer or reducing the control of the gate layer and the gate layer is reduced. The method of floating gate two = second electrical layer capacitance is to increase the accumulation degree of the conductor element, in the form of the above: ^. However, with the semi-intermediate pole, it is not possible to increase the control of the open electrode layer and the electrode layer and the floating The problem is that it is impossible to increase the surface sandwiched by the poles. Hand and increasing the component integration degree Summary of the invention In view of this, the manufacturing method of one aspect of the present invention uses self-alignment, a type of flash memory, The process can be simplified, and the second is: the gate coupling rate between the f open electrode and the selection, and the invention of a σ / sub open electrode and control gate provides: a piece of efficiency and product yield. Basic " Sequential formation of the lining layer and the cover screen Ldti screen: The method is based on; 彳 == ::: =. In: =: form == pole. Form the tracer in the base F% 丨 lower than the surface of the cover screen layer. After the gate is filled to fill the opening J, an inter-gate dielectric lightning layer is formed in the opening and separated in Gate counter: forming gate sidewalls of the gate dielectric, Ltd. l 565 912 a gap is formed on the titanium substrate ::

After the pre-set gate and the control gate form a selection gate, a drain region is formed in the substrate on the side of the selection gate. '

It can be adjusted in a standard way, and the gate gate can be over-processed outside the one layer of conductor. The area ratio of this outer gate stack gate clamp on one side, and the time required for erasing the material can make it easier to understand. The detailed description is as shown in Figure 2A, but it is not saved. After the hair layer is divided, the degree of the conductor and the use of arc flashes can be increased because the floating tip is short and the invention is short. The following is specific: The control and utilization layer has been used in a floating process until the same is not possible. Due to the memory phase, the floating gate of the floating gate can be raised or lowered quickly. The above gates are selected and the lithography technology is used. The gates are made by mechanical grinding. The exposed cover layer is used to the micro-saving process. The cost method makes this. Compared with the present invention, the floating increases the operating speed of the floating gate, and the introduction of a pole with a disaster angle can produce a low speed. Selecting a preferred embodiment for controlling the gate and other purposes. between. The flash gates and poles and control elements produced by the on-substrate method or the back-and-forth technique have a sharper angle and a select gate with a higher effective angle. The features and features are matched. It's in shape, so it's time. Floating gate memory and control gate. Therefore, in the electric field, the erasing plus the voltage, and the advantages of the drawings can automatically control the opening of the process, and the opening control can be increased, and its known gate coupling is used to obtain electronic data. Can be more clear 'Drawing detailed drawing to FIG. 2E is a quick view of the preferred embodiment of the present invention.

565912 V. Description of the invention (5) Sectional flow chart of flash memory manufacturing.

First, please refer to FIG. 2A to provide a substrate 200. This substrate 2000 has formed an element isolation structure (not shown). The element isolation structure is arranged in a stripe layout and is used to define an active area. The formation method of the element isolation structure is, for example, a local oxidation method (LOCOS) or a shallow trench isolation method (STI). Then, a pad layer 02 (Pad layer) is formed on the substrate 2000. The formation method of the pad layer 202 is, for example, a thermal oxidation method. The material is, for example, silicon oxide, and the thickness is, for example, about 150 angstroms. . Next, a mask layer 204 is formed on the substrate 2000. The method for forming the mask layer 204 is, for example, a chemical vapor deposition (CVD) method. The material of the cover layer 204 includes those with different surnames from the floating gates and control gates formed later, such as silicon nitride. Next, the patterned mask layer 204 is formed with openings 20 6, and the openings 2 06 are arranged in a stripe shape, and the openings 20 are perpendicular to the isolation structure.

Next, referring to FIG. 2B, a part of the liner 202 exposed by the opening 206 is removed. A method of removing a part of the liner 20 exposed by the opening 206 includes a wet etching method, which uses, for example, hydrofluoric acid as an etchant. Next, a tunnel oxide layer 20 is formed on the surface of the substrate 2000 exposed by the opening 2006_. The method of forming the oxide layer 208 is, for example, a thermal oxidation method, and the material is, for example, oxidized. The thickness is, for example, about 90 to 95 Angstroms. Then, a conductive layer 21 is formed on the substrate 200. The conductor layer 21o is, for example, doped polycrystalline silicon. An example of a method for forming the conductor layer 21o. 形成 After forming an undoped polycrystalline silicon layer by chemical vapor deposition,

Page 10 565912 V. Description of the invention (6) Ion implantation step to form it. Next, please refer to FIG. 2C, remove a part of the conductor layer 2 10 and form a conductor gap on both side walls of the opening 2 06. A method of removing a part of the conductor layer 210 is, for example, an anisotropic etching method. Then, the conductor gap wall is patterned (a portion of the conductor gap wall above the isolation structure is removed) to form a floating gate 210a. Then, a dopant implantation process is performed using the floating gate electrode 2 10a and the mask layer 204 as a mask to form a source region 2 12 in the substrate 200. Then, Yu Ji

An inter-gate dielectric layer 214 is formed on the bottom 200. The material of the inter-gate dielectric layer 2 1 4 is, for example, silicon oxide / silicon nitride / silicon oxide, and the thickness of each layer is 60 ~ 100 Angstroms, 70 to 100 Angstroms, and 60 to 100 Angstroms. Of course, the material of the inter-gate dielectric layer 2 1 4 may also be a silicon oxide layer, a oxidized stone / gasified stone. The step of forming the inter-gate dielectric layer 2 1 4 is, for example, first forming a silicon oxide layer 2 1 4a by a thermal oxidation method, and then forming a nitride layer 214b ′ by a chemical vapor deposition method, and then using wet hydrogen / oxygen (fj2 / 02 gas) formed by deoxidizing a part of the nitrided layer.夂 _ Next, referring to FIG. 2D, a control gate 2 1 6 is formed on the substrate 200 to fill the opening 206. The material of the control gate 2 1 6 is, for example, doped polycrystalline silicon. Its formation method is, for example, forming a non-doped polycrystalline silicon layer by chemical vapor deposition, and then performing an ion implantation step to form it. The control electrode 216 is formed by, for example, first forming another conductive layer (not shown) on the substrate 200, and then removing a part of the conductive layer until the surface of the mask layer 204 is exposed to form it. A method of removing a part of the conductive layer is, for example, an etch-back method < 4D vapor deposition method.

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Next, the mask layer 204, part of the inter-gate dielectric layer 214, and the liner 202 are removed to expose the sidewall of the control gate 216, the sidewall of the floating gate 210a, and the surface of the substrate 200. The method of removing the mask layer 204, the inter-gate dielectric layer 214, and the liner layer 202 is, for example, a wet etching method or a dry etching method. Then, a spacer 218, a spacer 22, and a gate dielectric layer 222 are formed on the side wall of the control gate 216, the side wall of the floating gate 21a, and the surface of the substrate 2000, respectively. The materials of the spacer 2 1 8, the spacer 2 2 0 and the gate dielectric layer 2 2 2 are, for example, silicon oxide, and the formation method is, for example, first forming a layer of silicon oxide by a thermal oxidation method, and then forming a four- on the oxide layer. Tetra Ethyl 〇rth.

Silicate, TEOS) / ozone (〇3) was used as a reactive gas source, and another oxide layer was formed by chemical vapor deposition. Among them, when the gap 220 is formed on the side wall of the floating gate 2a, a sharp corner is formed at the top of the floating gate. This sharp corner can generate a higher electric field when data is erased, and It can increase the efficiency of flash memory when erasing data. Next, referring to FIG. 2E, a selection gate 224 is formed on the side wall of the control gate 2 16 and the floating gate 210a. Select the method for forming the gate 224. For example, first form a conductor layer (not shown), remove a part of the conductor layer, and form a conductor gap on the side walls of the control gate 2 16 and the floating gate 2 10a.

This conductor gap serves as the selection gate 224. The material of the gate 224 is selected, for example, doped polycrystalline silicon. The formation method is, for example, forming an undoped polycrystalline silicon layer by chemical vapor deposition, and then performing an ion implantation step to form it. A method of removing a part of the conductive layer is, for example, an anisotropic etching method. The floating gate 210a, the control gate 216, and the selection gate 224 constitute a gate structure of the flash memory. Then, in the substrate 200 on the side of the selection gate 224, a dopant is implanted.

Page 12 565912 V. Description of the invention (8) The drain region 2 2 6 is formed. The subsequent process of completing the flash memory is well known to those skilled in the art, and will not be repeated here. According to the embodiment of the present invention, 'the present invention is formed by self-alignment when forming the floating gate 2 10a and the selection gate 2 24, and the lithography technology is not used, so < Increase process margin, and can save process cost and process time. _ Furthermore, the control gate electrode 2 16 of the present invention is formed on the substrate 2000 to form a conductive layer that fills the opening 2 06, and then removes the portion other than the opening 2 6 by a chemical mechanical polishing method or an etch-back method. In the process of forming the control gate 2 1 6, the conductive layer is shaped until the exposed cover layer 2 is exposed. The lithography technology is also not used, so the process margin can be increased and the process cost can be saved. . The floating gate 21a, which is manufactured by the method of the present invention, has an arc on one side and a top side. Therefore, compared with the flash memory of the Xi 2 stack and the 4-pin flash memory of the present invention, the area between the floating gate 2 10a and the control gate is increased, and the floating gate can be increased by 21 h. And ^ μ 二 urge 2 丨 6 gate coupling ratio, which can improve the speed and element operation

The row data w ^ has a sharp turning angle at the gate 2 1 〇a, so that the electrons can generate a high electric field at the turning angle of the gate 21 ^. In the middle, wipe ^ ^ ^ Fast introduction of the turning angle to select the gate 224. Example: 2 = shorter time required, and it can also reduce the control gate 2 1 6

Page 13 565912 V. Description of the invention (9) To limit the invention, anyone skilled in the art can make various modifications and retouches without departing from the spirit and scope of the invention. Therefore, the protection scope of the invention should be regarded as The appended application patent shall prevail.

10325twf.ptd Page 14 565912 Brief Description of Drawings Figure 1 is a cross-sectional structure diagram showing a conventional split-gate flash memory. Figures 2A to 2E show cross-sectional flowcharts of the manufacture of a flash memory according to a preferred embodiment of the present invention. Graphical description: 1 00, 2 0 0: substrate 102, 208: tunneling oxide layer 1 4 4, 2 1 0 a: floating gate electrode 1 06, 2 1 4: inter-gate dielectric layer 1 0 8, 2 1 6: Control gate 1 1 0: Top cover 1 1 2, 2 1 2: Source region 1 1 4, 2 1 8, 2 2 0: Gap wall 1 1 6, 2 2 4: Select gate 1 1 8, 2 2 6 > and polar region 2 0 2 2 2 2 2 2 2 2 4 4 2 4 4 2 4 4 2 2 4 4 2 4 4 2 2 4 4 2 2 4 4 2 2 4 4 2 2 4 222: Gate dielectric layer

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Claims (1)

565912 VI. Application for patent scope 1. A method for manufacturing flash memory, the method includes the following steps: providing a substrate, the substrate has formed an isolation structure, the isolation structure defines an active area; the active area on the substrate Forming a general layer on the area; forming a mask layer on the substrate; patterning the mask layer to form an opening; removing the liner layer exposed by the opening; forming a tunneling dielectric layer at the bottom of the opening A floating gate is formed on the side wall of the opening, and the top of the floating gate is lower than the surface of the cover layer; the floating gate is formed in the base of the opening at the bottom of the opening; A source region; forming an inter-gate dielectric layer in the opening; forming a control gate filling the opening on the substrate; removing the mask layer; forming a gate dielectric layer on the substrate and Forming a gap wall on the floating gate and a side wall of the control gate; forming a selection gate on the floating gate and a side wall of the control gate; and in the substrate on the side of the selection gate A drain region is formed. 2. The method for manufacturing a flash memory according to item 1 of the scope of patent application, wherein the floating gate is formed on a side wall of the opening, and the top of the floating gate is lower than the surface of the cover layer. include: 10325twf.ptd Page 16 565912 6. The scope of the patent application forms a first conductor layer on the substrate; a part of the first conductor layer is removed by an anisotropic etching process, and a first conductor has been formed on the side wall of the opening. A gap wall, and the top of the first conductor gap wall is lower than the surface of the cover layer; and patterning the first conductor gap wall to form the floating gate. 3. The method of manufacturing a flash memory as described in item 1 of the scope of patent application, wherein the step of forming the control gate to fill the opening on the substrate includes: forming a second conductor layer on the substrate; And removing a portion of the second conductor layer other than the opening to form the control jp gate. 4. The method of manufacturing a flash memory as described in item 3 of the scope of patent application, wherein the method of removing the second conductor layer other than the opening includes a back etch method. 5. The method of manufacturing a flash memory as described in item 3 of the scope of patent application, wherein the method of removing the second conductor layer other than the opening includes a chemical mechanical polishing method. 6. The flash memory manufacturing method as described in item 1 of the scope of patent application, wherein the step of forming the selection gate on the side wall of the floating gate and the control gate includes: _ forming a A third conductive layer; and removing a portion of the third conductive layer by an anisotropic etching process, the selective gate has been formed on a side wall of the floating gate and the control gate. 7. Manufacture of flash memory as described in item 1 of the scope of patent application 10325twf.ptd Page 17 565912 6. The scope of patent application method, in which the material of the inter-gate dielectric layer includes silicon oxide / silicon nitride / stone oxide. 8. The method of manufacturing a flash memory as described in item 1 of the scope of the patent application, wherein the material of the liner includes silicon oxide. 9. The flash memory manufacturing method as described in item 1 of the scope of patent application, wherein the material of the cover layer includes those having different etching selectivity from the floating gate, the control gate and the selection gate. . 10. The method for manufacturing a flash memory as described in item 6 of the scope of the patent application, wherein the material of the cover layer includes silicon nitride. 1 1. A method of manufacturing a flash memory, the method includes the following steps: providing a substrate 'the substrate has formed an isolation structure'; the isolation structure defines an active region; and forming a general layer on the active region of the substrate Forming a mask layer on the substrate; patterning the mask layer to form an opening; removing the liner layer exposed by the opening; forming a tunneling dielectric layer at the bottom of the opening; on the substrate Forming a first conductor layer; removing a portion of the first conductor layer to form a first conductor gap wall on a side wall of the opening, and a top of the first conductor gap wall is lower than a surface of the cover layer; patterning the A first conductor gap wall to form a floating gate electrode; the floating gate electrode is formed in the substrate at the bottom of the opening; 10325twf.ptd Page 18 565912 Sixth, the scope of patent application is a source region, a gate dielectric layer is formed in the opening; a second conductor layer is formed on the substrate; a portion other than the opening is removed from the second A conductive layer to form a control gate; removing the cover layer; forming a gate dielectric layer on the substrate and forming a gap wall on the floating gate and a side wall of the control gate; on the substrate Forming a third conductor layer; removing a portion of the third conductor layer, forming a selection gate on the side wall of the floating gate and the control gate; and forming a selection gate in the substrate on one side of the selection gate Not polar. 1 2. The method of manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the method of removing the second conductor layer other than the opening includes a cash back method. 1 3. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the method of removing the second conductor layer other than the opening includes a chemical mechanical polishing method. 14. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the material of the inter-gate dielectric layer includes silicon oxide / silicon nitride / stone oxide. 15. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the material of the lining layer includes silicon oxide. 16 6. Manufacture of flash memory as described in item 11 of the scope of patent application 10325twf.ptd Page 19 565912 6. Method of applying for patent, wherein the material of the cover layer includes those with different etching selectivity from the floating gate, the control gate and the selection gate. 1 7. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the material of the cover layer includes silicon nitride. 10325twf.ptd Page 20