JP3459062B2 - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Currently, flash type EEPROM (Flass
h Electrically Erasable Programmable ROM)
It is widely used in electronic devices as a nonvolatile semiconductor memory device that can be electrically written and erased. The structure of the memory cell in the non-volatile semiconductor memory device is roughly classified into two types. The first is a stack gate type having an electrode structure in which a floating gate electrode and a control gate electrode are sequentially stacked on a semiconductor substrate, and the second is a semiconductor substrate in which the floating gate electrode and the control gate electrode are adjacent to each other. It is a split gate type having an electrode structure facing the channel region of.

A conventional split gate type non-volatile semiconductor memory device will be described below with reference to the drawings.

FIG. 42 shows US Pat. No. 5,780,341.
2 shows a cross-sectional structure of a split gate type nonvolatile semiconductor memory device in which a step portion is provided in a lower portion of a floating gate electrode in a semiconductor substrate. FIG. 42
As shown in FIG. 1, for example, on the main surface of the semiconductor substrate 201 made of p-type silicon, the first surface region 202 in the upper stage,
A step portion 205 is provided which includes a second surface area 203 which is a lower step and a step side surface area 204 which connects the upper step and the lower step.

The step portion 20 on the first surface region 202
5, a control gate electrode 210 is formed via a gate insulating film 211. In addition, the floating gate electrode 212 formed so as to straddle the step portion 205 has a silicon oxide film 21 on the side surface of the control gate electrode 210 on the step portion 205 side.
3 and capacitively couples with each other, and faces the second surface region 203 with a silicon oxide film 213 serving as a tunnel film.

An n-type high-concentration source region 221 is formed in the first surface region 202 of the semiconductor substrate 201,
In the second surface region 203, an n-type low-concentration drain region 222a is formed in a region below the floating gate electrode 212, and a high-concentration drain region 222b is formed outside the low-concentration drain region 222a. .

A p-type impurity region 223 having a p-type impurity concentration higher than that of the semiconductor substrate 201 is formed in a region of the first surface region 202 below the floating gate electrode 212. By adopting such a configuration, since the floating gate electrode 212 is located in the direction in which the electrons injected into the high-concentration source region 221 travel in the channel region, the injection efficiency of the channel electrons is improved.

[0008]

As a result of various studies including simulations and the like, the inventors of the present application have found that the conventional split gate nonvolatile semiconductor memory device has a stepped portion provided on a semiconductor substrate 201. It is concluded that 205 has an insufficient effect of increasing the electron injection efficiency.

That is, when an electric field is applied during the write operation, the high electric field is unlikely to propagate upward from the lower corner of the step 205 at the source-side end of the low-concentration drain region 222a. The electric field is likely to be concentrated only in the vicinity of the lower corners, and as a result, the region having the highest electric field is displaced below the step side surface region 204 where the channel electrons of the floating gate electrode 212 are to be actually injected. , Channel electrons flow directly to the low-concentration drain region 222a through a region away from the step side surface region 204. Therefore, the floating gate electrode 2 for channel electrons
That is, the high efficiency of injection into 12 has not been sufficiently achieved.

On the other hand, during the erase operation, the electrons accumulated in the floating gate electrode 212 are transferred to the silicon oxide film 2
An FN tunnel current is extracted from the tunnel film formed of a portion of the tunnel electrode 13 facing the floating gate electrode 212 to the high concentration drain region 222b. However, there is a problem that the area of the electron passage portion in the tunnel film is reduced with the miniaturization of the element, and the erase operation becomes difficult.

In order to facilitate the erase operation, there is a method of increasing the drain voltage to increase the electric field applied to the tunnel film. However, holes having high energy (hot holes) generated in the high concentration drain region 222b are available. ) Also occurs at the same time. The hot hole causes a problem that the reliability of the tunnel film is lowered, or the hot hole is trapped in the tunnel film to deteriorate the characteristics of the device.

Further, with the miniaturization of the element, especially with the reduction of the gate length of the control gate electrode 210, there is a problem that the short channel effect, which has not been realized in the conventional split gate type flash EEPROM device, is also realized. .

The present invention solves the above-mentioned problems of the prior art, ensures improvement of electron injection efficiency in a nonvolatile semiconductor memory device having a step portion, and realizes high-speed writing at a low voltage. Is the first purpose.

A second object is to improve the erasing speed while suppressing the generation of hot holes during the erasing operation, and the third object is to suppress the short channel effect and enable miniaturization of the device. The purpose of.

[0015]

In order to achieve the first object, the present invention provides a nonvolatile semiconductor memory device having a step portion on the drain side, which has a high conductivity type on the side opposite to the conductivity type of the drain region. The concentration impurity region is formed so as not to reach the first surface region and the step side surface region from the upper corner of the step portion and is formed at a position facing the corner portion, or an appropriate substrate voltage is applied during the writing operation. The method of applying is adopted.

In order to achieve the second object, the present invention has a structure in which the impurity concentration of the drain region is increased as the distance from the source region increases. An impurity region having a conductivity type opposite to that of the source region is provided.

Specifically, the first non-volatile semiconductor memory device according to the present invention achieves the first object and is formed on a semiconductor substrate and has a first surface region as an upper stage and a second surface region as a lower stage.
A step portion formed of a surface area and a step side surface area connecting the upper step and the lower step, a first insulating film formed on the first surface area, and a first insulating film interposed in the vicinity of the step portion on the first surface area. And a control gate electrode formed on the semiconductor substrate so as to straddle the step portion, and is capacitively coupled to the side surface of the control gate electrode on the step portion side via the second insulating film.
A floating gate electrode facing the surface region through the third insulating film; a source region formed in a region of the first surface region opposite to the floating gate electrode with respect to the control gate electrode;
The drain region formed in the region below the floating gate electrode in the second surface region and the semiconductor substrate below the step portion from a position spaced from the upper corner of the step portion below the first surface region. A depletion control layer formed of a high-concentration impurity region of a conductivity type opposite to the drain region, the depletion control layer being formed to extend toward the corner portion on the side and adjoin the drain region without reaching the step side surface region.

The first non-volatile semiconductor memory device is of a split gate type, and according to this, from the position spaced from the upper corner of the step portion below the first surface region inside the semiconductor substrate. A depletion control layer is formed which extends toward the lower corner of the step portion and is formed so as to be adjacent to the drain region without reaching the step side surface region and which is composed of a high-concentration impurity region of a conductivity type opposite to the drain region. Therefore, during the write operation, even if the drain region is provided in the second surface region below the step, the depletion layer does not extend to a region away from the step. In addition, the high electric field due to the drain region is in a reverse bias state due to the pn junction with the depletion control layer, the potential difference between the pn junctions also increases, and the high electron temperature region generated near the lower corner of the step portion. Since a path of carriers flowing toward the side surface is generated, the efficiency of injection of electrons, which have become hot electrons in the vicinity of the step side surface region, from the step side surface region to the floating gate electrode is surely improved.

The first non-volatile semiconductor memory device includes a high electric field forming layer formed between the upper corner of the step and the depletion limiting layer and formed of an impurity region of the same conductivity type as the depletion limiting layer. Further, it is preferable to further include. With this configuration, in the step side surface region, the gradient of the energy level of the pn junction formed by the interface between the high electric field forming layer and the drain region becomes steeper, so that the high electric field forming layer and the drain region have a higher gradient. An electric field is generated, and the generated high electric field overlaps the high electric field due to the step structure and the high electric field generated at the boundary between the depletion control layer and the drain region, so that the electron temperature near the lower corner of the step side surface region is increased. Rise even more. as a result,
The generation amount of hot electrons of channel electrons is increased, and the electron injection efficiency to the floating gate electrode is further improved.

In the first nonvolatile semiconductor memory device,
The impurity concentration of the high electric field forming layer is preferably lower than that of the depletion control layer and higher than that of the semiconductor substrate. By doing so, the high electric field forming layer formed between the stepped portion and the depletion control layer spaced from the stepped portion is depleted during the write operation, and the channel region is surely generated in the vicinity of the step side surface region. To be done.

A second nonvolatile semiconductor memory device according to the present invention is formed on a semiconductor substrate and comprises a first surface region which is an upper stage, a second surface region which is a lower stage, and a step side surface region which connects the upper stage and the lower stage. A step portion, a first insulating film formed on the semiconductor substrate so as to extend over the step portion, a floating gate electrode formed on the first insulating film so as to extend over the step portion, and a second insulating film formed on the floating gate electrode. A control gate electrode formed via an insulating film and capacitively coupled to the floating gate electrode, a source region formed in a region of the first surface region opposite to the step portion with respect to the floating gate electrode, and a second surface region. A drain region formed in a region below the floating gate electrode in
The semiconductor substrate extends from a position spaced from the upper corner of the step below the first surface region toward the lower corner of the step and is adjacent to the drain region without reaching the step side region. And a depletion control layer formed of a high-concentration impurity region of a conductivity type opposite to the drain region.

The second non-volatile semiconductor memory device is of a stack gate type, and according to this, from the position inside the semiconductor substrate, spaced from the upper corner of the step below the first surface region. A depletion control layer is formed which extends toward the lower corner of the step portion and is formed so as to be adjacent to the drain region without reaching the step side surface region and which is composed of a high-concentration impurity region of a conductivity type opposite to the drain region. Therefore, during the write operation, even if the drain region is provided in the second surface region below the step, the depletion layer does not extend to a region away from the step. In addition, since a high electric field due to the drain region causes a high electric field due to the pn junction with the depletion control layer, a carrier path that flows toward a high electron temperature region generated near the corner below the step is generated. Thus, the efficiency of injection of electrons, which have become hot electrons in the vicinity of the step side surface region, into the floating gate electrode from the step side surface region is surely improved.

The second non-volatile semiconductor memory device includes a high electric field forming layer formed between the upper corner of the step and the depletion limiting layer and formed of an impurity region of the same conductivity type as the depletion limiting layer. Further, it is preferable to further include.

In this case, the impurity concentration of the high electric field forming layer is preferably lower than that of the depletion control layer and higher than that of the semiconductor substrate.

In the first or second nonvolatile semiconductor memory device, the source region side end of the drain region is
It is preferably located in the step side surface region without reaching the first surface region. By doing so, a region having a conductivity type opposite to the conductivity type of the drain region is formed in the step side surface region, so that the channel region can be reliably formed using the region as a depletion layer and an inversion layer.

In the first or second non-volatile semiconductor memory device, the drain region includes at least three impurity regions formed so that the impurity concentration increases in the plane direction of the second surface region and from the source region side. It is preferable to have. In this case, since the impurity concentration on the side opposite to the channel region in the drain region is high, the electric field strength on the channel region side becomes relatively small, so that the generation of hot holes is suppressed in the peripheral portion of the drain region during the erase operation. It As a result, the reliability deterioration of the tunnel film can be prevented. Furthermore, since the short channel effect is also suppressed, the second and third objects can be achieved.

The first or second nonvolatile semiconductor memory device is formed in the first surface region so as to cover the junction surface of the source region, has the conductivity type opposite to that of the source region, and suppresses the short channel effect. It is preferable to further include an impurity region. By doing so, the expansion of the depletion layer in the channel region is suppressed, so that the short channel effect and the punch through effect can be suppressed, and the third object described above is achieved.

A third nonvolatile semiconductor memory device according to the present invention achieves the second and third objects, and is formed on a semiconductor substrate and has a first surface region as an upper stage and a second surface region as a lower stage. And a step portion formed of a step side surface region connecting the upper step and the lower step, and a first insulating film formed on the first surface area,
A control gate electrode formed on the first surface region in the vicinity of the step portion via a first insulating film, and a side surface of the control gate electrode on the step portion side and formed on the semiconductor substrate so as to straddle the step portion. A floating gate electrode that is capacitively coupled through the second insulating film and faces the second surface region through the third insulating film;
A source region formed in a region of the first surface region opposite to the floating gate electrode with respect to the control gate electrode;
The drain region is formed in a region below the floating gate electrode in the surface region, and is formed near a corner between the first surface region and the step side surface region in the semiconductor substrate, and has a higher impurity concentration than the semiconductor substrate. An impurity region having a conductivity type opposite to that of the drain region, and the drain region includes at least three impurity diffusion regions formed in the plane direction of the second surface region so that the impurity concentration increases from the source region side. Have

The third non-volatile semiconductor memory device is of a split gate type. According to this, the third non-volatile semiconductor memory device is formed in the vicinity of a corner between the first surface region and the step side surface region of the semiconductor substrate, and has an impurity concentration of the semiconductor substrate. Since the impurity region having a conductivity type higher than that of the drain region and the drain region is provided, a high electric field is generated at the pn junction surface between the impurity region and the drain region, and the generation amount of hot electrons of electrons in the channel is increased. By increasing the number, the efficiency of injecting electrons into the floating gate electrode is improved. In addition, since the drain region has at least three impurity diffusion regions formed in the plane direction of the second surface region so that the impurity concentration increases from the source region side, the drain region on the channel region side Since the electric field strength is relatively small, the generation of hot holes in the peripheral portion of the channel of the drain region is suppressed during the erase operation. Furthermore, the short channel effect is also suppressed.

A fourth nonvolatile semiconductor memory device according to the present invention achieves the third object and is formed on a semiconductor substrate, and has a first surface region as an upper stage, a second surface region as a lower stage and an upper stage. A step formed of a step side surface region connecting the lower step, a first insulating film formed on the first surface region, and a control formed via the first insulating film in the vicinity of the step on the first surface region The gate electrode is formed on the semiconductor substrate so as to straddle the step portion, and capacitively couples to the side surface of the control gate electrode on the step portion side via the second insulating film and via the second surface region and the third insulating film. A floating gate electrode facing each other, a source region formed in a region opposite to the control gate electrode in the first surface region, and a region below the floating gate electrode in the second surface region. With drain region and semi-conducting A first impurity region formed in the vicinity of a corner between the first surface region and the step side surface region of the substrate and having a conductivity type higher than the impurity concentration of the semiconductor substrate and opposite to the drain region; And a second impurity region formed to cover the junction surface of the source region and having a conductivity type opposite to that of the source region and suppressing a short channel effect.

The fourth non-volatile semiconductor memory device is of a split gate type. According to this, the fourth non-volatile semiconductor memory device is formed in the vicinity of a corner between the first surface region and the step side surface region of the semiconductor substrate, and has an impurity concentration of the semiconductor substrate. Since the first impurity region having a conductivity type higher than that of the drain region and the drain region is provided, the pn of the first impurity region and the drain region is formed.
A high electric field is generated at the junction surface, and the amount of hot electrons generated in the channel is increased, so that the efficiency of injecting electrons into the floating gate electrode is improved. In addition, since the second impurity region having a conductivity type opposite to that of the source region is formed so as to cover the junction surface of the source region, the depletion layer is suppressed from spreading in the channel region.
It is possible to suppress the short channel effect and the punch through effect.

A fifth nonvolatile semiconductor memory device according to the present invention achieves the second and third objects, and is formed on a semiconductor substrate and has a first surface region as an upper stage and a second surface region as a lower stage. A step portion formed of a step side surface region connecting the upper step and the lower step, a first insulating film formed on the semiconductor substrate so as to straddle the step portion, and formed on the first insulating film so as to straddle the step portion. A floating gate electrode, a control gate electrode formed on the floating gate electrode via a second insulating film and capacitively coupled to the floating gate electrode, and a region of the first surface region opposite to the step portion with respect to the floating gate electrode. And a drain region formed in a region below the floating gate electrode in the second surface region, and a corner region between the first surface region and the step side surface region in the semiconductor substrate. , Semiconductor substrate An impurity region having a conductivity type higher than that of the drain region and having a conductivity type opposite to that of the drain region, and the drain region is formed at least in the surface direction of the second surface region and from the source region side to have a higher impurity concentration. It has three impurity diffusion regions.

The fifth non-volatile semiconductor memory device is a stack gate type device. According to this, the fifth non-volatile semiconductor memory device is formed in the vicinity of a corner between the first surface region and the step side surface region of the semiconductor substrate, and has an impurity concentration of the semiconductor substrate. Since the impurity region having a conductivity type higher than that of the drain region and the drain region is provided, a high electric field is generated at the pn junction surface between the impurity region and the drain region, and the generation amount of hot electrons of electrons in the channel is increased. By increasing the number, the efficiency of injecting electrons into the floating gate electrode is improved. In addition, since the drain region has at least three impurity diffusion regions formed in the plane direction of the second surface region so that the impurity concentration increases from the source region side, the drain region on the channel region side Since the electric field strength is relatively small, the generation of hot holes in the peripheral portion of the channel of the drain region is suppressed during the erase operation. Furthermore, the short channel effect is also suppressed.

A sixth nonvolatile semiconductor memory device according to the present invention achieves the third object, and is formed on a semiconductor substrate and has a first surface region as an upper stage, a second surface region as a lower stage and an upper stage. A step portion formed of a step side surface region connecting the lower step and a first step formed on the semiconductor substrate so as to straddle the step portion.
An insulating film, a floating gate electrode formed on the first insulating film so as to straddle the step portion, and a control gate electrode formed on the floating gate electrode via the second insulating film and capacitively coupled to the floating gate electrode. A source region formed in a region of the first surface region opposite to the step portion with respect to the floating gate electrode,
The drain region is formed in the region below the floating gate electrode in the second surface region, and is formed in the vicinity of the corner between the first surface region and the step side surface region in the semiconductor substrate, and is higher than the impurity concentration of the semiconductor substrate. A first impurity region having a high conductivity type opposite to that of the drain region and a first surface region are formed to cover the junction surface of the source region, have a conductivity type opposite to that of the source region, and suppress a short channel effect. And a second impurity region.

The sixth non-volatile semiconductor memory device is of a stack gate type. According to this, the sixth non-volatile semiconductor memory device is formed in the vicinity of a corner between the first surface region and the step side surface region in the semiconductor substrate, and has an impurity concentration of the semiconductor substrate. Since the first impurity region having a conductivity type higher than that of the drain region and opposite to the drain region is provided, a high electric field is generated at the pn junction surface between the first impurity region and the drain region, and electrons in the channel are The increase in the amount of hot electrons generated improves the efficiency of injecting electrons into the floating gate electrode. In addition, since the second impurity region formed so as to cover the junction surface of the source region and having the conductivity type opposite to that of the source region is provided, the depletion layer is suppressed from spreading in the channel region, so that the short channel is formed. It is possible to suppress the effect, and further the punch-through effect.

In the first to sixth nonvolatile semiconductor memory devices, when a substrate voltage is applied to the semiconductor substrate, carriers are transferred from the lower part of the floating gate electrode in the first surface region toward the step side surface region. It is preferred to form a flowing channel region. By doing this, the first
In the semiconductor substrate surrounded by the surface region and the step side surface region, the potential of the floating gate becomes relatively high, so that the carriers are more strongly attracted to the surface of the semiconductor substrate. In addition, since the current density increases only when the substrate voltage is applied, the power consumption when the write operation is not performed can be significantly reduced.

In the first to sixth nonvolatile semiconductor memory devices, the floating gate electrode in the first surface region is formed by applying a predetermined drain voltage and a predetermined control gate voltage to the drain region and the control gate electrode. It is preferable to form a channel region in which carriers flow from the lower side portion toward the step side surface region.

A seventh nonvolatile semiconductor memory device of the present invention achieves the first object and is formed on a semiconductor substrate,
A step portion formed of a first surface area that is an upper step, a second surface area that is a lower step, and a step side surface area that connects the upper step and the lower step;
A first insulating film formed on the first surface region, a control gate electrode formed on the first surface region in the vicinity of the step portion via the first insulating film, and so as to straddle the step portion on the semiconductor substrate. The side surface of the control gate electrode on the step side and the second side.
The second surface region and the third surface are capacitively coupled through the insulating film.
A floating gate electrode facing through the insulating film, a source region formed in a region of the first surface region opposite to the control gate electrode, and a lower side of the floating gate electrode in the second surface region. A non-volatile region including a drain region formed in a region of the semiconductor substrate and an impurity region formed in the first surface region and the step side surface region of the semiconductor substrate and having a conductivity type higher than that of the semiconductor substrate and having a conductivity type opposite to that of the drain region. Assuming that the semiconductor memory device is a semiconductor memory device, applying a substrate voltage to the semiconductor substrate forms a channel region in which carriers flow from the lower side portion of the floating gate electrode in the first surface region toward the step side surface region.

The seventh non-volatile semiconductor memory device is a split gate type, and according to this, even if the depletion control layer is not provided inside the step portion of the semiconductor substrate away from the step side surface region. , For example, by applying a substrate voltage having a polarity opposite to that of the drain voltage during a write operation, that is, by applying a negative substrate voltage for an n-type channel and a positive substrate voltage for a p-type channel Since the potential of the floating gate is relatively high in the semiconductor substrate surrounded by the first surface region and the step side surface region, carriers are more strongly attracted to the surface of the semiconductor substrate, and carriers are injected into the floating gate electrode. The efficiency can be improved.

An eighth non-volatile semiconductor memory device of the present invention achieves the first object and is formed on a semiconductor substrate,
A step portion formed of a first surface area that is an upper step, a second surface area that is a lower step, and a step side surface area that connects the upper step and the lower step;
A first insulating film formed on the semiconductor substrate so as to straddle the step portion; a floating gate electrode formed on the first insulating film so as to straddle the step portion; and a second insulating film on the floating gate electrode. A control gate electrode that is formed by capacitive coupling with the floating gate electrode, a source region that is formed in a region of the first surface region opposite to the step portion with respect to the floating gate electrode, and a second region.
The drain region formed in the region below the floating gate electrode in the surface region, and the conductivity type higher than the impurity concentration of the semiconductor substrate and opposite to the drain region, formed in the first surface region and the step side surface region of the semiconductor substrate. Assuming a non-volatile semiconductor memory device including an impurity region having an impurity region, a carrier voltage is applied to the semiconductor substrate to cause carriers from the lower side portion of the floating gate electrode in the first surface region toward the step side face region. A channel region through which the current flows is formed.

The eighth non-volatile semiconductor memory device is a stack gate type, and according to this, even if the depletion control layer is not provided inside the step portion of the semiconductor substrate away from the step side surface region, For example, during a write operation, n
By applying a negative substrate voltage for the p-type channel and a positive substrate voltage for the p-type channel,
In the semiconductor substrate surrounded by the surface region and the step side surface region, the potential of the floating gate becomes relatively high, so that the carriers are more strongly attracted to the surface of the semiconductor substrate, and the carrier injection efficiency to the floating gate electrode is improved. it can.

A first method for manufacturing a non-volatile semiconductor memory device according to the present invention comprises a first step of forming a control gate electrode on a semiconductor substrate via a first insulating film, and a source formation region of the semiconductor substrate. And a second step of forming a high-concentration impurity region by ion-implanting a first-conductivity-type high-concentration impurity into the semiconductor substrate using the control gate electrode as a mask. Is formed, and the side wall and the control gate electrode are used as a mask and the source formation region is masked to perform etching on the semiconductor substrate.
A step is formed on the semiconductor substrate by forming a recess in the semiconductor substrate, and including a first surface region in which the lower side of the sidewall is an upper level, a second surface region in which the bottom of the recess is a lower level, and a step side surface region connecting the upper level and the lower level. A third step of forming a portion, and a second conductivity type low concentration impurity is selectively ion-implanted into the second surface region of the semiconductor substrate to form a second conductivity type low concentration impurity in the second surface region. By forming the drain region and inverting the conductivity type in the vicinity of the first surface region in the high-concentration impurity region, in the upper corner of the step and in the vicinity of the step side surface region, the high-concentration impurity region is formed. A fourth step of forming a depletion control layer that is localized at a distance from the surface region and the step side surface region and is adjacent to the low-concentration drain region; and after removing the sidewalls, ~ side A fifth step of forming a second insulating film on the first surface region, the step side surface region and the second surface region, and depositing a conductor film on the entire surface of the second insulating film, By etching,
A floating gate electrode is formed in a self-aligned manner while straddling the step portion and capacitively coupled to the side surface of the control gate electrode on the step portion side via the second insulating film and facing the second surface region via the second insulating film. And a second conductive type source region is formed in the first surface region by ion-implanting a second conductive type impurity into the semiconductor substrate using the control gate electrode and the floating gate electrode as a mask. And a seventh step of forming a drain region of the second conductivity type in the second surface region.

According to the first method for manufacturing a non-volatile semiconductor memory device, the second conductivity type low concentration impurity is selectively ion-implanted into the second surface region formed of the bottom surface of the recess of the semiconductor substrate, A second conductivity type low-concentration drain region is formed in the second surface region, and the conductivity type in the vicinity of the first surface region of the high-concentration impurity region, the upper corner of the step portion and the step side surface region is inverted. Accordingly, the method includes a step of forming a depletion control layer which is composed of a high-concentration impurity region of the first conductivity type, is localized at a distance from the first surface region and the step side surface region, and is adjacent to the low-concentration drain region. Therefore, the first nonvolatile semiconductor memory device of the present invention can be reliably manufactured.

In the first method of manufacturing a non-volatile semiconductor memory device, the second step is that after the high concentration impurity region is formed, the first conductivity type impurity is ion-implanted again into the high concentration impurity region. Accordingly, the fourth step includes the step of forming another impurity region of the first conductivity type whose diffusion depth is shallower than that of the high-concentration impurity region. It is preferable to include a step of forming a high electric field forming layer made of another impurity region in between.

According to the first method of manufacturing a nonvolatile semiconductor memory device, after the seventh step, the third non-volatile semiconductor memory device is formed on the floating gate electrode.
By depositing an insulating film and using the deposited third insulating film and floating gate electrode as a mask, ion-implanting impurities of the second conductivity type into the semiconductor substrate, so that the impurity concentration in the second surface region is higher than that in the drain region. It is preferable to further include an eighth step of forming a large second-conductivity-type high-concentration drain region. By doing so, the third nonvolatile semiconductor memory device of the present invention can be reliably manufactured.

In the first method for manufacturing a non-volatile semiconductor memory device, after the fourth step, the region from the control gate electrode to the second surface region is masked so that the diffusion depth in the source formation region is greater than that in the source region. It is preferable that the method further includes a step of forming a deep first conductivity type impurity region. By doing so, the fourth nonvolatile semiconductor memory device of the present invention can be reliably manufactured.

In the second method for manufacturing a non-volatile semiconductor memory device according to the present invention, the first conductive type high-concentration impurity is selectively ion-implanted into the drain formation region of the semiconductor substrate to thereby obtain the first conductive type. A first step of forming a high-concentration impurity region of the mold, and a region of the high-concentration impurity region other than the end on the source formation region side are selectively etched to form a recess in the semiconductor substrate. ,
A second step is formed on the semiconductor substrate. The step section includes a first surface area having an end portion of the high-concentration impurity region in an upper step, a second surface area having a bottom surface of the recess in a lower step, and a step side surface area connecting the upper step and the lower step. And the step of selectively implanting a second conductivity type low concentration impurity into the second surface region of the semiconductor substrate to form a second conductivity type low concentration drain region in the second surface region. A high-concentration impurity region is formed by inverting the conductivity type in the high-concentration impurity region in the vicinity of the first surface region, in the upper corner of the step portion and in the vicinity of the step side-surface region. A third step of forming a depletion control layer which is localized at a distance from and adjacent to the low-concentration drain region, and a first insulating film, a floating gate electrode, 2 Insulating film and control gate And a second step of sequentially forming the second conductive type source region in the source forming region by ion-implanting a second conductive type impurity into the semiconductor substrate using the control gate electrode as a mask. And a fifth step of forming a drain region of the second conductivity type in the drain formation region.

According to the second method for manufacturing a non-volatile semiconductor memory device, the second conductivity type low concentration impurity is selectively ion-implanted into the second surface region of the recess of the semiconductor substrate to form the second surface. A low-concentration drain region of the second conductivity type is formed in the region, and a conductivity type near the first surface region of the high-concentration impurity region of the first conductivity type, an upper corner of the step portion, and a step side surface region. By inverting, the method includes a step of forming a depletion control layer which is composed of a high-concentration impurity region, is localized at a distance from the first surface region and the step side surface region, and is adjacent to the low-concentration drain region. The second non-volatile semiconductor memory device of the present invention can be reliably manufactured.

In the second method of manufacturing a non-volatile semiconductor memory device, the first step is that after the high concentration impurity region is formed, the first conductivity type impurity is ion-implanted again into the high concentration impurity region. Thus, the third step includes the step of forming another impurity region of the first conductivity type having a diffusion depth shallower than that of the high-concentration impurity region. It is preferable to include a step of forming a high electric field forming layer made of another impurity region in between.

In the second non-volatile semiconductor memory device, after the fifth step, the third insulating film is deposited on the control gate electrode, the deposited third insulating film insulating film is etched, and the floating gate is formed. A sixth step of forming a sidewall on the side surface of the electrode and the control gate electrode, and ion implantation of an impurity of the second conductivity type into the semiconductor substrate using the control gate electrode and the sidewall as a mask to form a second surface. It is preferable to further include a seventh step of forming a second-conductivity-type high-concentration drain region having a higher impurity concentration than the drain region in the region. By doing so, the fifth nonvolatile semiconductor memory device of the present invention can be reliably manufactured.

In the second nonvolatile semiconductor memory device, after the third step, the region from the control gate electrode to the second surface region is masked, and the diffusion depth in the source formation region is deeper than that in the source region. It is preferable to further include a step of forming an impurity region of one conductivity type. This way,
The sixth nonvolatile semiconductor memory device of the present invention can be manufactured with certainty.

[0052]

(First Embodiment) First Embodiment of the Present Invention
Embodiments will be described with reference to the drawings.

FIG. 1 shows a sectional structure of one memory element of the split gate type non-volatile semiconductor memory device according to the first embodiment. As shown in FIG. 1, for example, LOCOS is formed on the main surface of the semiconductor substrate 11 made of p-type silicon.
Alternatively, in the active region surrounded by the element isolation layer 12 formed by trench isolation or the like, a step portion including an upper first surface region 13, a lower second surface region 14, and a step side surface region 15 connecting the upper and lower steps is formed. 16 are provided.

A control gate electrode 21 is formed on the first surface region 13 via a first insulating film 22. Also,
Floating gate electrode 23 formed so as to straddle the step portion 16
Is the second side surface of the control gate electrode 21 on the side of the step portion 16.
The capacitor is capacitively coupled via the insulating film 24 and faces the second surface region 14 via the third insulating film 25 serving as a tunnel film. The first insulating film 22 and the third insulating film 25 may be composed of one film, and the second insulating film 24 and the third insulating film 25 may be composed of one film.

In the first surface region 13 of the semiconductor substrate 11,
An n-type source region 31 is formed, and an n-type drain region 32 is formed in the second surface region 14 below the floating gate electrode 23.

In the nonvolatile semiconductor memory device according to the first embodiment, a space is provided in the vicinity of the step portion 16 inside the semiconductor substrate 11 with a corner above the step portion 16 below the floating gate electrode 23. A depletion formed of a p-type high-concentration impurity region formed so as to extend from the position toward the lower corner of the step portion 16 and to be adjacent to the end of the drain region 32 without reaching the step side surface region 15. It is characterized in that it is provided with a chemical regulation layer 33.

An example of each operation of writing, erasing and reading of data in the nonvolatile semiconductor memory device according to this embodiment will be described below.

First, at the time of writing data, a gate voltage of about 4.0 V to 7.0 V is applied to the control gate electrode 21, the source region 31 is grounded, and the drain region 32.
A drain voltage of about 4.0 V to 6.0 V is applied to the.
By applying this voltage, hot electrons are generated around the lower corner of the step portion 16, and the generated hot electrons are injected into the floating gate electrode 23 through the third insulating film 25.

At the time of erasing data, the control gate electrode 21
To the gate voltage of -5.0V to -7.0V,
A drain voltage of about 4.0 V to 6.0 V is applied to the drain region 23 and the source region 13 is grounded. As a result, the electrons accumulated in the floating gate electrode 23 are
By the (Fowler-Nordheim) type tunnel phenomenon, it is extracted to the drain region 32 through the third insulating film 25.

When reading data, a source voltage of about 1.0 V to 3.0 V is applied to the source region 31, the drain region 32 is grounded, and the control gate electrode 21.
A gate voltage of about 2.0V to 4.0V is applied to
Alternatively, a drain voltage of about 1.0 V to 3.0 V is applied to the drain region 32, the source region 31 is grounded, and a gate voltage of about 2.0 V to 4.0 V is applied to the control gate electrode 21. At this time, the threshold voltage value of the control gate voltage 21 differs depending on the presence / absence of electrons accumulated in the floating gate electrode 23, and the amount of current flowing between the source and drain differs. Therefore, the amount of current is detected to detect the data. The presence or absence of is determined.

In the nonvolatile semiconductor memory device according to this embodiment, the depletion control layer 33 including the p-type high concentration impurity region is formed.
Is the first surface region 13 and the step side surface region 15 of the step portion 16.
Is formed so as not to reach the drain region 32, and the end portion of the depletion control layer 33 on the drain region 32 side is formed adjacent to the drain region 32. As a result, as shown in the schematic diagram of FIG. 2, during the write operation, electrons that are carriers flow toward the high electron temperature region 1 and the high electron temperature region 2 generated near the lower corner of the step portion 16. A carrier path (= channel) is formed. As a result, the channel electrons that have become hot electrons near the step side surface region 15 are efficiently injected from the step side surface region 15 into the floating gate electrode 23.

FIG. 3A shows a result obtained by a computer simulation of the current density during the write operation in the vicinity of the step portion 16 of the nonvolatile semiconductor memory device according to the present embodiment, and FIG. 3B is for comparison. In addition, the simulation result of the conventional nonvolatile semiconductor memory device in which the depletion control layer 33 is not provided is shown.

The semiconductor memory device according to the present embodiment is shown in FIG.
As shown in (a), since the depletion control layer 33 has a high p-type impurity concentration, it is not depleted.
Surface region 13, step side surface region 15, and depletion control layer 33
The portion surrounded by is depleted and functions as a channel region. As a result, the electrons in the channel are transferred to the step side surface region 15
You can see that it flows with a spread toward.

Furthermore, since the carrier path is restricted by the depletion restriction layer 33, charges are accumulated in the floating gate electrode 23, the potential of the floating gate electrode 23 is lowered, and electrons are strongly attracted to the drain region 32. However, the electrons that have passed through the lower portion of the control gate electrode 21 in the channel region do not flow directly into the drain region 32,
The path of carriers flowing toward the lower corner of the step is maintained. As a result, a constant carrier path can be realized regardless of the potential of the floating gate electrode 23, and the carrier injection efficiency into the floating gate electrode 23 can be improved.

On the other hand, in the case of the conventional nonvolatile semiconductor memory device shown in FIG. 3B, the p-type impurity in the region spaced from the first surface region 13 and the step side face region 15 of the step portion 16. Since the concentration is low, even this region is depleted during the writing operation and functions as a channel. Therefore, the electrons in the channel flow directly to the drain region 32 without passing through the maximum electron temperature region generated near the lower corner of the step portion 16, and as a result, to the floating gate electrode 23. It can be seen that the probability of injection is low.

Next, the depletion control layer 33 also has the following effects. That is, the depletion control layer 33 formed of the p-type high-concentration impurity region is the n-type drain region 32.
Since it is formed so as to be adjacent to the end portion on the side, since a pn junction having a sharp concentration gradient is formed at the interface between the depletion control layer 33 and the drain region 32, a high electric field is generated at the interface. Occur. By providing the depletion control layer 33 so that the high electric field generated at the interface between the two is located near the lower corner of the step 16, electrons generated near the lower corner of the step 16 are provided. Temperature The electron temperature in the high temperature range rises dramatically, and as a result, the writing speed is greatly improved.

If the drain region 32 completely covers the lower corner of the step 16, the potential of the corner is kept at a high potential by the drain potential during the write operation. Since the potential gradient of the step side surface region 15 becomes steep and the high temperature region of the electron temperature generated near the lower corner of the step portion 16 spreads to the step side surface 13, the writing speed is improved.

In this embodiment, the step portion 16
Although the step side surface region 15 is formed substantially perpendicular to the second surface region 14, the angle formed between the step side surface region 15 and the second surface region 14 may be an obtuse angle.

Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

4 to 6 show sectional structures in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

First, as shown in FIG. 4A, p-type silicon is used.
For example, trench isolation is performed on the semiconductor substrate 51 made of silicon.
An element isolation layer 52 having a structure is formed. Next, the element
A thermal oxidation method is formed on the active region 10 surrounded by the release layer 52.
Alternatively, a protective oxide film 5 having a thickness of about 20 nm is formed by the CVD method.
3 is formed, and then the active region 1 is formed on the semiconductor substrate 51.
First register having a p-type well region forming pattern of 0
Pattern 91 is formed. Then, the first resist pattern
Using the turn 91 as a mask, boron (B) ions are used as an example.
For example, the implantation dose is 0.5 x 10¹³cm^-2~ 1 x 10¹⁴
cm^-2Implantation energy of about 300 keV
Under the conditions, ions are formed on the semiconductor substrate 51 through the protective oxide film 53.
Implanting the impurities to cause impurities near the surface of the active region 10.
Concentration is 5 × 10¹³cm^-3~ 1 x 10¹⁴cm^-3Degree p type
A well region is formed. Furthermore, the entire surface of the active region 10
And the implantation dose is 0.5 × 10¹³cm^-2~ 1 x 10¹³
cm ^-2Threshold of injection energy is about 30 keV
Protects the boron (B) ion for controlling the value voltage from the oxide film 53.
Ion implantation through.

Next, as shown in FIG. 4B, after removing the first resist pattern 91 and the protective oxide film 53,
Again, the gate oxide film 54 as the first insulating film is formed on the active region 10 by the CVD method or the thermal oxidation method. After that, for example, a first polysilicon film is deposited on the entire surface of the semiconductor substrate 51 by the CVD method, and the deposited first polysilicon film is patterned by the photolithography method to control the polysilicon. The gate electrode 55 is formed. Then, a second resist pattern 92 having an opening in the drain formation region of the active region 10 is formed on the semiconductor substrate 51, and the formed second resist pattern 92 and the gate electrode 55 are used as a mask, for example, implantation dose. The amount is 0.5 × 10 ¹³ cm ^-2 to 1 × 10 ¹⁴ cm
Boron (B) ions having an implantation energy of about ⁻² keV and about 15 keV are ion-implanted into the semiconductor substrate 51 through the gate oxide film 54.
A mold high concentration impurity layer 56 is formed.

Next, as shown in FIG. 4C, after removing the second resist pattern 92, a BPSG film is deposited over the entire surface of the semiconductor substrate 51 by using, for example, the CVD method. Subsequently, anisotropic etching is performed on the deposited BPSG film, whereby the control gate electrode 55 is formed.
A side wall 57 made of a BPSG film is formed on the side surface of the. Here, by adjusting the deposited film thickness of BPSG, the semiconductor substrate 5 is formed on the side surface of the control gate electrode 55 and in the subsequent process.
It is possible to determine the distance between the step portion formed at 1 and the step portion in a self-aligned manner.

Next, as shown in FIG. 4D, a third resist pattern 93 having an opening in the drain formation region is formed on the semiconductor substrate 51, and the formed third resist pattern 93 and gate electrode. The semiconductor substrate 51 is dry-etched using 55 and the sidewalls 57 as a mask to form a recess 51a in the drain formation region of the semiconductor substrate 51.

Next, as shown in FIG.
Gist pattern 93, gate electrode 55 and side war
With the mask 57 as a mask, for example, the implantation dose is 0.5 ×
10 ¹⁴cm^-2~ 5 x 10¹⁴cm^-2Inject energy at a degree
Arsenic (As) ion of about 10 keV is applied to the semiconductor substrate 5
By ion-implanting 1 into the
A low concentration drain region 58 of the mold is formed.

At this time, the p-type impurity concentration in the lower part of the sidewall 57 of the p-type high-concentration impurity layer 56 is reduced by the compensation effect of the n-type impurity implantation when forming the low-concentration drain region 58. . As a result, the control gate electrode 55 of the recess 51 a in the semiconductor substrate 51 is formed.
The side step portion 51b extends from a position spaced apart from the upper corner portion of the step portion 51b below the control gate electrode 55 toward the lower corner portion of the step portion 51b and reaches the step side surface region. Instead, it is possible to form the depletion control layer 56a formed of the p-type high concentration impurity layer 56 so as to be adjacent to the low concentration drain region 58.

Next, as shown in FIG. 5B, after removing the third resist pattern 93, the sidewall 57 is formed.
By removing the exposed portions of the gate oxide film 54 and the gate oxide film 54 by wet etching, the upper surface of the first surface region 5 is removed.
9. The step portion 51b including the second surface region 60 which is the lower step and the step side surface region 61 which connects the upper step and the lower step and the side surface of the control gate electrode 55 are exposed.

Next, as shown in FIG. 5C, a second insulating film and a third insulating film are formed on the exposed surface including the step portion 51b of the semiconductor substrate 51 and the surface of the control gate electrode 55 by the thermal oxidation method. Forming a thermal oxide film 62. The thermal oxide film 6
2 may be a silicon oxide film formed by a CVD method or the like.

Next, as shown in FIG. 5D, for example, C
The control gate electrode 5 is formed on the semiconductor substrate 51 by using the VD method.
By depositing a second polysilicon film over the entire surface including 5 and anisotropically etching the deposited second polysilicon film, the step portion 51b is straddled and the step portion 51b of the control gate electrode 55 is formed. Side surface and the second side surface region 60 through capacitive coupling through the thermal oxide film 62.
A floating gate electrode 63 made of polysilicon is formed in a self-aligned manner so as to oppose to the thermal oxide film 62. Here, the floating gate electrode 63 of the thermal oxide film 62 and the semiconductor substrate 5 are
The region sandwiched between 1 and 1 functions as a tunnel film.

Next, as shown in FIG. 6A, an insulating film 64 of silicon oxide or the like is formed on the entire surface of the semiconductor substrate 51, and then the formed insulating film 64 is etched to form the semiconductor substrate 51. Exposed.

Next, as shown in FIG. 6B, arsenic (As) ions are implanted into the semiconductor substrate 51 by using the control gate electrode 55, the floating gate electrode 63 and the insulating film 64 as a mask, and the semiconductor substrate 51 control gate electrode 55
A high-concentration source region 65 is formed in a region opposite to the floating gate electrode 63, and is connected to a low-concentration drain region 58 in a region on the floating gate electrode 63 side of the control gate electrode 55 of the semiconductor substrate 51. High concentration drain region 66
Are formed to complete one memory element of the nonvolatile semiconductor memory device.

As described above, according to the method of manufacturing the nonvolatile semiconductor memory device in the first embodiment, the p-type high concentration impurity layer 56 is formed in the drain forming region of the semiconductor substrate 51. Then, the control gate electrode 55
Of the semiconductor substrate 51 using the side walls 57 of
By forming the recess 51b in the semiconductor substrate 51, the lower portion of the sidewall 57 of the semiconductor substrate 51 is used as the first surface region (upper stage), and the bottom surface of the recess 51b is used as the second surface region 60.
A stepped portion 51b to be (lower) is formed. Then, the second
When the n-type low-concentration drain region 58 is formed in the surface region 60 by implantation, a compensation effect for the high-concentration impurity layer 56 causes a gap from the upper corner of the step portion 51b.
It is possible to reliably form the depletion control layer 56a having a desired impurity profile that faces the corner portion and is adjacent to the low-concentration drain region 58.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 shows a sectional structure of one memory element of the split gate type nonvolatile semiconductor memory device according to the second embodiment. In FIG. 7, the same components as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 7, in the nonvolatile semiconductor memory device according to the second embodiment, the depletion limiting layer 33 is formed between the upper corner of the step portion 16 and the depletion limiting layer 33.
It has a high electric field forming layer 34 made of a p-type impurity region having the same conductivity type as the above.

Here, the p-type impurity concentration of the high electric field forming layer 34 is set to be lower than the p-type impurity concentration of the depletion control layer 33 and higher than the p-type impurity concentration of the semiconductor substrate 11. .

According to the second embodiment, the p-type high electric field forming layer 34 is formed on the upper corner of the step portion 16 and the depletion regulating layer 33.
In the step side surface region 15, the gradient of the energy level due to the pn junction formed by the interface between the high electric field forming layer 34 and the drain region 32 becomes steeper by providing the gap between the and. As a result, the high electric field forming layer 34 and the drain region 3
A high electric field is generated at the interface between the depletion control layer 33 and the drain region 32, and a high electric field generated at the interface between the depletion control layer 33 and the drain region 32. And the electron temperature in the vicinity of the lower corner of the step 16 is further increased. As a result, the amount of hot electrons generated in the channel is increased, and the efficiency of injecting electrons into the floating gate electrode 23 is significantly improved.

Further, the high concentration forming layer 34 is replaced with the depletion control layer 3
When formed independently of No. 3, it also has the effect of improving the controllability of the threshold voltage of the memory element.

As described in the first embodiment,
A portion of the semiconductor substrate 11 surrounded by the depletion control layer 33, the first surface region 13 and the step side surface region 15 functions as a channel, and channel electrons are generated in the step side surface region 1.
In order to maintain a carrier path that flows with a spread toward 5, the high electric field forming layer 34 is preferably made to have an impurity concentration such that it is depleted during a write operation.

Also in this embodiment, the angle formed between the step side surface region 15 and the second surface region 14 may be an obtuse angle.

Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device having the above structure will be described with reference to the drawings.

8 to 10 show sectional structures in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

First, as shown in FIG. 8A, p-type silicon
For example, trench isolation is performed on the semiconductor substrate 51 made of silicon.
An element isolation layer 52 having a structure is formed. Next, the element
A thermal oxidation method is formed on the active region 10 surrounded by the release layer 52.
Alternatively, a protective oxide film 5 having a thickness of about 20 nm is formed by the CVD method.
3 is formed, and then the active region 1 is formed on the semiconductor substrate 51.
First register having a p-type well region forming pattern of 0
Pattern 91 is formed. Then, the first resist pattern
Using the turn 91 as a mask, boron (B) ions are used as an example.
For example, the implantation dose is 0.5 x 10¹³cm^-2~ 1 x 10¹⁴
cm^-2Implantation energy of about 300 keV
Under the conditions, ions are formed on the semiconductor substrate 51 through the protective oxide film 53.
Implanting the impurities to cause impurities near the surface of the active region 10.
Concentration is 5 × 10¹³cm^-3~ 1 x 10¹⁴cm^-3Degree p type
A well region is formed. Furthermore, the entire surface of the active region 10
And the implantation dose is 0.5 × 10¹³cm^-2~ 1 x 10¹³
cm ^-2Threshold of injection energy is about 30 keV
Protects the boron (B) ion for controlling the value voltage from the oxide film 53.
Ion implantation through.

Next, as shown in FIG. 8B, after removing the first resist pattern 91 and the protective oxide film 53,
Again, the gate oxide film 54 as the first insulating film is formed on the active region 10 by the CVD method or the thermal oxidation method. After that, for example, a first polysilicon film is deposited on the entire surface of the semiconductor substrate 51 by the CVD method, and the deposited first polysilicon film is patterned by the photolithography method to control the polysilicon. The gate electrode 55 is formed. Subsequently, a second resist pattern 92 having an opening in the drain formation region of the active region 10 is formed on the semiconductor substrate 51, and the formed second resist pattern 92 and the gate electrode 55 are used as a mask to form a boron (B ) Ions are implanted twice at different acceleration voltages. For the first time, for example, the implantation dose is 0.5
Ions are implanted into the semiconductor substrate 51 through the gate oxide film 54 under the implantation conditions of about 10 ¹³ cm ^-2 to 1 x 10 ¹⁴ cm ^-2 and the implantation energy is about 30 keV, and the p-type first region is formed in the drain formation region. The high concentration impurity layer 56 of No. 1 is formed. In the second time, the implantation dose is 0.5 × 10 ¹³ cm ⁻² to 1 so that the junction depth is shallower than that of the first high concentration impurity layer 56.
Injection energy of about 15 keV at about 10 ¹⁴ cm ^-2
Ion implantation is performed under the implantation conditions of 1 to form a p-type second high-concentration impurity layer 71 in the drain formation region.

Next, as shown in FIG. 8C, after removing the second resist pattern 92, a BPSG film is deposited over the entire surface of the semiconductor substrate 51 by using, for example, the CVD method. Subsequently, anisotropic etching is performed on the deposited BPSG film, whereby the control gate electrode 55 is formed.
A side wall 57 made of a BPSG film is formed on the side surface of the. Here, by adjusting the deposited film thickness of BPSG, the semiconductor substrate 5 is formed on the side surface of the control gate electrode 55 and in the subsequent process.
It is possible to determine the distance between the step portion formed at 1 and the step portion in a self-aligned manner.

Next, as shown in FIG. 8D, a third resist pattern 93 having an opening in the drain formation region is formed on the semiconductor substrate 51, and the formed third resist pattern 93 and gate electrode. The semiconductor substrate 51 is dry-etched using 55 and the sidewalls 57 as a mask to form a recess 51a in the drain formation region of the semiconductor substrate 51.

Then, as shown in FIG.
Gist pattern 93, gate electrode 55 and side war
With the mask 57 as a mask, for example, the implantation dose is 0.5 ×
10 ¹⁴cm^-2~ 5 x 10¹⁴cm^-2Inject energy at a degree
Arsenic (As) ion of about 10 keV is applied to the semiconductor substrate 5
By ion-implanting 1 into the
A low concentration drain region 58 of the mold is formed.

At this time, the p-type first high-concentration impurity layer 5 is formed.
In the lower part of the side wall 57 in 6, the p-type impurity concentration is reduced by the compensation effect of the n-type impurity implantation when forming the low-concentration drain region 58. As a result, in the step portion 51b on the control gate electrode 55 side of the recess 51a in the semiconductor substrate 51, the step portion 51b below the control gate electrode 55 is spaced apart from the upper corner portion of the step portion 51b. While extending toward the corner,
Low-concentration drain region 58 without reaching the step side surface region
It is possible to form the depletion control layer 56a formed of the p-type first high-concentration impurity layer 56 so as to be adjacent thereto.

At the same time, a high electric field from the p-type second high-concentration impurity layer 71 to a concentration lower than that of the first high-concentration impurity layer 56 due to the compensation effect when the low-concentration drain region 58 is formed. The formation layer 71a can be formed between the upper corner of the step portion 51b and the depletion control layer 56a.

Next, as shown in FIG. 9B, after removing the third resist pattern 93, the sidewall 57 is formed.
By removing the exposed portions of the gate oxide film 54 and the gate oxide film 54 by wet etching, the upper surface of the first surface region 5 is removed.
9. The step portion 51b including the second surface region 60 which is the lower step and the step side surface region 61 which connects the upper step and the lower step and the side surface of the control gate electrode 55 are exposed.

Next, as shown in FIG. 9C, a second insulating film and a third insulating film are formed on the exposed surface including the step portion 51b of the semiconductor substrate 51 and the surface of the control gate electrode 55 by the thermal oxidation method. Forming a thermal oxide film 62. The thermal oxide film 6
2 may be a silicon oxide film formed by a CVD method or the like.

Next, as shown in FIG. 9D, for example, C
The control gate electrode 5 is formed on the semiconductor substrate 51 by using the VD method.
By depositing a second polysilicon film over the entire surface including 5 and anisotropically etching the deposited second polysilicon film, the step portion 51b is straddled and the step portion 51b of the control gate electrode 55 is formed. Side surface and the second side surface region 60 through capacitive coupling through the thermal oxide film 62.
A floating gate electrode 63 made of polysilicon is formed in a self-aligned manner so as to oppose to the thermal oxide film 62. Here, the floating gate electrode 63 of the thermal oxide film 62 and the semiconductor substrate 5 are
The region sandwiched between 1 and 1 functions as a tunnel film.

Next, as shown in FIG. 10A, an insulating film 64 of silicon oxide or the like is formed on the entire surface of the semiconductor substrate 51, and then the formed insulating film 64 is etched to expose the semiconductor substrate 51. To do.

Next, as shown in FIG. 10B, arsenic (As) ions are implanted into the semiconductor substrate 51 by using the control gate electrode 55, the floating gate electrode 63 and the insulating film 64 as a mask. 51 control gate electrode 5
5, a high-concentration source region 65 is formed in a region opposite to the floating gate electrode 63, and is connected to a low-concentration drain region 58 in a region on the floating gate electrode 63 side with respect to the control gate electrode 55 of the semiconductor substrate 51. High-concentration drain region 6
6 is formed, and one memory element of the nonvolatile semiconductor memory device is completed.

As described above, according to the method of manufacturing the nonvolatile semiconductor memory device in the second embodiment, the p-type first high-concentration impurity layer 56 and the first high-concentration impurity layer 56 are formed in the drain formation region of the semiconductor substrate 51. The second high-concentration impurity layer 71 having a junction shallower than the high-concentration impurity layer 56 is formed in advance. After that, the sidewall 57 of the control gate electrode 55 is formed.
By using the mask as a mask to form the recess 51b in the semiconductor substrate 51, the lower portion of the sidewall 57 of the semiconductor substrate 51 is used as the first surface region (upper stage), and the recess 51 is formed.
Step portion 51 having the bottom surface of b as the second surface region 60 (lower stage)
b is formed. Subsequently, when the n-type low-concentration drain region 58 is formed by implantation in the second surface region 60, the step portion 5 is formed due to the compensation effect on the first high-concentration impurity layer 56.
It is possible to reliably form the depletion control layer 56a having a desired impurity profile that is spaced from the upper corner of 1b and faces the corner and is localized adjacent to the low-concentration drain region 58. In addition, the high electric field forming layer 7 having the desired impurity profile of the second high concentration impurity layer 71 is formed between the upper corner of the step portion 51b and the depletion control layer 56a.
1a can be formed.

In the second embodiment, the first high concentration impurity layer 56 and the second high concentration impurity layer 71 are continuously ion-implanted using the same third resist pattern 93. Although the desired impurity profiles were respectively formed by performing the same, the first high-concentration impurity layer can be obtained even if, for example, the first and second ion implantations are performed with different mask patterns instead. 56
It goes without saying that a desired impurity profile can be obtained in the second high-concentration impurity layer 71.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 11 shows a cross-sectional structure of one memory element of the stack gate type nonvolatile semiconductor memory device according to the third embodiment. 11, the same components as those shown in FIG. 1 are designated by the same reference numerals.

In the nonvolatile semiconductor memory device according to the third embodiment, the step portion 16 provided in the active region on the semiconductor substrate 11 is formed so as to straddle the first insulating film 22 serving as a tunnel insulating film. And the floating gate electrode 23A formed on the floating gate electrode via the second insulating film 24,
The floating gate electrode 23A is provided with a control gate electrode 21A that is capacitively coupled.

As described above, the nonvolatile semiconductor memory device according to the third embodiment has the drain region 32 in the second surface region 14 which is the lower step of the step portion 16, and the drain region 32 is formed on the substrate so as to straddle the step portion. It is a stack gate type having a floating gate electrode 23A and a control gate electrode 21A, which are sequentially stacked on top of each other, and is spaced inside the semiconductor substrate 11 from the upper corner of the step 16 below the first surface region 13. From the open position toward the lower corner of the step portion 16 and is formed so as to be adjacent to the drain region 32 without reaching the step side surface region 15 and from the high-concentration impurity region of the conductivity type opposite to the drain region 32. Has a depletion control layer 33.

Similar to the first embodiment, a depletion control layer 33 of a conductivity type which is adjacent to the drain region 32 and opposite to the drain region is provided at a position spaced from the upper corner of the step portion 16. Since the p-type impurity concentration is high, the depletion control layer 33 is not depleted during the write operation because it is provided and is surrounded by the first surface region 13, the step side surface region 15 and the depletion control layer 33 in the semiconductor substrate 11. The portion to be depleted functions as a channel. As a result, the electrons in the channel spread and flow toward the step side surface region 15, and the efficiency of carrier injection into the floating gate electrode 23A can be improved.

Since the depletion control layer 33 made of the p-type high-concentration impurity region is formed so as to be adjacent to the end portion on the n-type drain region 32 side, the depletion control layer 33 and the drain region 32 are formed. Has a sharp concentration gradient at the interface
Since an n-junction is formed, a high electric field is generated at the interface. By providing the depletion control layer 33 so that the high electric field generated at the interface between the two is located near the lower corner of the step 16, the electron temperature generated near the lower corner of the step 16 is provided. The electron temperature in the high temperature range is dramatically increased, and as a result, the writing speed is significantly improved.

When the drain region 32 completely covers the lower corner of the step 16, the potential of the corner is maintained at a high potential by the drain potential during the write operation. Since the potential gradient of the step side surface region 15 becomes steep and the high temperature region of the electron temperature generated near the lower corner of the step portion 16 spreads to the step side surface 13, the writing speed is improved.

Also in this embodiment, the angle formed by the step side surface region 15 and the second surface region 14 may be set to an obtuse angle.

Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

12 to 14 show sectional structures in the order of steps of the method for manufacturing a nonvolatile semiconductor memory device according to the third embodiment of the present invention.

First, as shown in FIG. 12A, an element isolation layer 52 having, for example, a trench isolation structure is formed on a semiconductor substrate 51 made of p-type silicon. Subsequently, a protective oxide film 53 having a film thickness of about 20 nm is formed on the active region 10 surrounded by the element isolation layer 52 by a thermal oxidation method or a CVD method, and thereafter, the active oxide film 53 is formed on the semiconductor substrate 51. A first resist pattern 91 having a p-type well region forming pattern in the region 10 is formed. Then, using the first resist pattern 91 as a mask, boron (B) ions are
For example, the implantation dose amount is 0.5 × 10 ¹³ cm ⁻² to 1 × 10
Ions are implanted into the semiconductor substrate 51 through the protective oxide film 53 under an implantation condition of about ¹⁴ cm ⁻² and an implantation energy of about 300 keV, whereby the impurity concentration in the vicinity of the surface of the active region 10 is 5 × 10 ¹³ cm ^−. P of about ³ to 1 × 10 ¹⁴ cm ^-3
Form a mold well region. Further, the implantation dose is 0.5 × 10 ¹³ cm ⁻² to 1 × 10 ^{13 on} the entire surface of the active region 10.
Boron (B) ions for controlling the threshold voltage having an implantation energy of about 30 cm ^{−2 at} about cm ⁻² are ion-implanted through the protective oxide film 53.

Next, as shown in FIG. 12B, after removing the first resist pattern 91, a second resist pattern having an opening in the drain formation region of the active region 10 is formed on the semiconductor substrate 51. 92 is formed, and using the formed second resist pattern 92 as a mask, for example, the implantation dose is about 0.5 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² ,
Boron (B) ions having an implantation energy of about 15 keV are ion-implanted into the semiconductor substrate 51 through the protective insulating film 53, thereby forming the p-type high-concentration impurity layer 56 in the drain formation region.

Next, as shown in FIG. 12C, after the second resist pattern 92 is removed, the source formation region and the end portion of the high concentration impurity layer 56 on the source formation region side are formed on the semiconductor substrate 51. Resist pattern 9 for masking
3 is formed, and the semiconductor substrate 51 is dry-etched using the formed third resist pattern 93 as a mask to form a recess 51a in the drain formation region of the semiconductor substrate 51. At this time, by adjusting the mask amount (overlap amount) of the end portion of the high concentration impurity layer 56 on the source formation region side, the depletion control layer 56a formed from the high concentration impurity layer 56 in the gate length direction in the gate length direction. The size of can be optimized.

Next, as shown in FIG. 12D, using the third resist pattern 93 as a mask, for example, with an implantation dose of about 0.5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁴ cm ⁻² . By implanting arsenic (As) ions having an implantation energy of about 10 keV into the semiconductor substrate 51, an n-type low concentration drain region 58 is formed in the drain formation region.

At this time, the p-type impurity concentration in the lower part of the side wall 57 of the p-type high-concentration impurity layer 56 is reduced by the compensation effect of the n-type impurity implantation when forming the low-concentration drain region 58. . As a result, the control gate electrode 55 of the recess 51 a in the semiconductor substrate 51 is formed.
The side step portion 51b extends from a position spaced apart from the upper corner portion of the step portion 51b below the control gate electrode 55 toward the lower corner portion of the step portion 51b and reaches the step side surface region. Instead, it is possible to form the depletion control layer 56a formed of the p-type high concentration impurity layer 56 so as to be adjacent to the low concentration drain region 58.

Next, as shown in FIG. 13A, by removing the third resist pattern 93 and the protective oxide film 53, the upper surface of the semiconductor substrate 51, that is, the first surface region 59 in the upper step, The step portion 51b including the second surface region 60 that is the lower step and the step side surface region 61 that connects the upper step and the lower step is exposed.

Next, as shown in FIG. 13B, a gate oxide film 54 as a first insulating film is formed on the exposed surface of the semiconductor substrate 51 including the step portion 51b by a thermal oxidation method. After that, the first polysilicon film 63A, the silicon oxide film 67A as the second insulating film, and the second polysilicon film 55A are deposited over the entire surface of the gate oxide film 54 by using, for example, the CVD method. The silicon oxide film 67A
May be formed as a thermal oxide film.

Next, as shown in FIG. 13C, a fourth resist pattern 94 having a gate electrode pattern straddling the step portion 51b is formed on the second polysilicon 55A, and the formed fourth resist pattern 94 is formed. Using the resist pattern 94 as a mask, the second polysilicon film 55A and the silicon oxide film 67 are formed.
A and the first polysilicon film 63A are anisotropically etched to form a floating gate electrode electrode 63B made of the first polysilicon film 63A and a silicon oxide film 67A.
And the second polysilicon film 5 and the capacitive insulating film 67B made of
The floating gate electrode 55B made of 5A is formed.
Here, the gate oxide film 54 between the semiconductor substrate 51 and the floating gate electrode 63B functions as a tunnel film.

Next, as shown in FIG. 13D, the fourth resist pattern 94 is removed, and thereafter, as shown in FIG. 14, a fifth resist pattern having an opening pattern of the source formation region and the drain formation region is formed. Arsenic (As) is formed on the semiconductor substrate 51 by forming the resist pattern 95 and using the formed fifth resist pattern 95 and the control gate electrode 55B as a mask.
By implanting ions, the high-concentration source region 65 is formed in the first surface region 59 of the semiconductor substrate 51, and the second surface region 60 of the semiconductor substrate 51 and the low-concentration drain region 5 are formed.
A high-concentration drain region 66 connected to 8 is formed to complete one memory element of the stack gate type nonvolatile semiconductor memory device.

As described above, according to the method for manufacturing the nonvolatile semiconductor memory device in the third embodiment, the p-type high concentration impurity layer 56 is formed in the drain forming region of the semiconductor substrate 51. Then, the high-concentration impurity layer 5
6 is masked at the end of the semiconductor substrate 51 on the source region side.
By forming the recess 51b in the semiconductor substrate 51, the lower portion of the sidewall 57 of the semiconductor substrate 51 is used as the first surface region (upper stage), and the bottom surface of the recess 51b is used as the second surface region 60.
A stepped portion 51b to be (lower) is formed. Then, the second
When the n-type low-concentration drain region 58 is formed in the surface region 60 by implantation, a compensation effect with respect to the p-type high-concentration impurity layer 56 causes a gap from the upper corner of the step portion 51b to form the corner. Opposing and low-concentration drain region 58
It is possible to reliably form the depletion control layer 56a having a desired impurity profile that is located adjacent to.

(Fourth Embodiment) A fourth embodiment of the present invention will be described below with reference to the drawings.

FIG. 15 shows a sectional structure of one memory element of the stack gate type nonvolatile semiconductor memory device according to the fourth embodiment. In FIG. 15, the same components as those of the third embodiment shown in FIG. 11 are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 15, in the nonvolatile semiconductor memory device according to the fourth embodiment, the depletion control layer 3 is formed between the upper corner of the step portion 16 and the depletion control layer 33.
3 is characterized by having a high electric field forming layer 34 made of a p-type impurity region having the same conductivity type as that of No. 3. here,
The p-type impurity concentration of the high electric field formation layer 34 is determined by the depletion control layer 3
3 is lower than the p-type impurity concentration of p.
It is set to be higher than the type impurity concentration.

According to the fourth embodiment, the p-type high electric field forming layer 34 is formed on the upper corner of the step portion 16 and the depletion control layer 33.
In the step side surface region 15, the gradient of the energy level due to the pn junction formed by the interface between the high electric field forming layer 34 and the drain region 32 becomes steeper by providing the gap between the and. As a result, the high electric field forming layer 34 and the drain region 3
A high electric field is generated at the interface between the depletion control layer 33 and the drain region 32, and a high electric field generated at the interface between the depletion control layer 33 and the drain region 32. And the electron temperature in the vicinity of the lower corner of the step 16 is further increased. As a result, the amount of hot electrons generated in the channel is increased, and the efficiency of electron injection into the floating gate electrode 23A is significantly improved.

Further, the high concentration forming layer 34 is replaced with the depletion control layer 3
When formed independently of No. 3, it also has the effect of improving the controllability of the threshold voltage of the memory element.

As described in the first embodiment,
A portion of the semiconductor substrate 11 surrounded by the depletion control layer 33, the first surface region 13 and the step side surface region 15 functions as a channel, and channel electrons are generated in the step side surface region 1.
In order to maintain a carrier path that flows with a spread toward 5, the high electric field forming layer 34 is preferably made to have an impurity concentration such that it is depleted during a write operation.

Also in this embodiment, the angle formed between the step side surface region 15 and the second surface region 14 may be set to an obtuse angle.

Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

16 to 18 show sectional structures in the order of steps of the method for manufacturing a nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

First, as shown in FIG. 16A, an element isolation layer 52 having, for example, a trench isolation structure is formed on a semiconductor substrate 51 made of p-type silicon. Subsequently, a protective oxide film 53 having a film thickness of about 20 nm is formed on the active region 10 surrounded by the element isolation layer 52 by a thermal oxidation method or a CVD method, and thereafter, the active oxide film 53 is formed on the semiconductor substrate 51. A first resist pattern 91 having a p-type well region forming pattern in the region 10 is formed. Then, using the first resist pattern 91 as a mask, boron (B) ions are
For example, the implantation dose amount is 0.5 × 10 ¹³ cm ⁻² to 1 × 10
Ions are implanted into the semiconductor substrate 51 through the protective oxide film 53 under an implantation condition of about ¹⁴ cm ⁻² and an implantation energy of about 300 keV, whereby the impurity concentration in the vicinity of the surface of the active region 10 is 5 × 10 ¹³ cm ^−. P of about ³ to 1 × 10 ¹⁴ cm ^-3
Form a mold well region. Further, the implantation dose is 0.5 × 10 ¹³ cm ⁻² to 1 × 10 ^{13 on} the entire surface of the active region 10.
Boron (B) ions for controlling the threshold voltage having an implantation energy of about 30 cm ^{−2 at} about cm ⁻² are ion-implanted through the protective oxide film 53.

Next, as shown in FIG. 16B, the first
After removing the resist pattern 91, on the semiconductor substrate 51
First, the opening having an opening is formed in the drain formation region of the active region 10.
Second resist pattern 92 is formed, and the formed second resist pattern is formed.
Boron (B) io
Ion implantation with different acceleration voltages.
U For the first time, for example, the implantation dose is 0.5 × 10¹³c
m^-2~ 1 x 10¹⁴cm ^-2The injection energy is about 3
A semiconductor via the gate oxide film 54 under the implantation condition of 0 keV
Ions are implanted into the substrate 51 to p-type the drain formation region.
The first high concentration impurity layer 56 is formed. The second time is the first
So that the junction depth is shallower than the high-concentration impurity layer 56 of
And the implantation dose is 0.5 × 10¹³cm^-2~ 1 x 10¹⁴
cm^-2The injection energy is about 15 keV.
Depending on the conditions, a p-type second
The high concentration impurity layer 71 is formed.

Next, as shown in FIG. 16C, after the second resist pattern 92 is removed, the source formation region and the end portion of the high concentration impurity layer 56 on the source formation region side are formed on the semiconductor substrate 51. Resist pattern 9 for masking
3 is formed, and the semiconductor substrate 51 is dry-etched using the formed third resist pattern 93 as a mask to form a recess 51a in the drain formation region of the semiconductor substrate 51. At this time, the first high-concentration impurity layer 5
By adjusting the mask amount of the end portion on the source formation region side of 6, the dimension of the depletion control layer 56a formed from the high concentration impurity layer 56 in the gate length direction can be optimized.

Next, as shown in FIG. 16D, using the third resist pattern 93 as a mask, for example, with an implantation dose of about 0.5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁴ cm ⁻² . By implanting arsenic (As) ions having an implantation energy of about 10 keV into the semiconductor substrate 51, an n-type low concentration drain region 58 is formed in the drain formation region.

At this time, the p-type first high-concentration impurity layer 5 is formed.
In the lower part of the side wall 57 in 6, the p-type impurity concentration is reduced by the compensation effect of the n-type impurity implantation when forming the low-concentration drain region 58. As a result, in the step portion 51b on the control gate electrode 55 side of the recess 51a in the semiconductor substrate 51, the step portion 51b below the control gate electrode 55 is spaced apart from the upper corner portion of the step portion 51b. While extending toward the corner,
Low-concentration drain region 58 without reaching the step side surface region
It is possible to form the depletion control layer 56a formed of the p-type first high-concentration impurity layer 56 so as to be adjacent thereto.

At the same time, the high electric field from the p-type second high-concentration impurity layer 71 to a concentration lower than that of the first high-concentration impurity layer 56 by the compensation effect when the low-concentration drain region 58 is formed. The formation layer 71a can be formed between the upper corner of the step portion 51b and the depletion control layer 56a.

Next, as shown in FIG. 17A, by removing the third resist pattern 93 and the protective oxide film 53, the upper surface of the semiconductor substrate 51, that is, the first surface region 59 in the upper step, The step portion 51b including the second surface region 60 that is the lower step and the step side surface region 61 that connects the upper step and the lower step is exposed.

Next, as shown in FIG. 17B, a gate oxide film 54 as a first insulating film is formed on the exposed surface of the semiconductor substrate 51 including the step portion 51b by a thermal oxidation method. After that, the first polysilicon film 63A, the silicon oxide film 67A as the second insulating film, and the second polysilicon film 55A are deposited over the entire surface of the gate oxide film 54 by using, for example, the CVD method. The silicon oxide film 67A
May be formed as a thermal oxide film.

Next, as shown in FIG. 17C, a fourth resist pattern 94 having a gate electrode pattern straddling the step portion 51b is formed on the second polysilicon 55A, and the formed fourth resist pattern 94 is formed. Using the resist pattern 94 as a mask, the second polysilicon film 55A and the silicon oxide film 67 are formed.
A and the first polysilicon film 63A are anisotropically etched to form a floating gate electrode electrode 63B made of the first polysilicon film 63A and a silicon oxide film 67A.
And the second polysilicon film 5 and the capacitive insulating film 67B made of
The floating gate electrode 55B made of 5A is formed.
Here, the gate oxide film 54 between the semiconductor substrate 51 and the floating gate electrode 63B functions as a tunnel film.

Next, as shown in FIG. 17D, the fourth resist pattern 94 is removed, and thereafter, as shown in FIG. 18, a fifth resist pattern 94 having an opening pattern of a source formation region and a drain formation region is formed. By implanting arsenic (As) ions into the semiconductor substrate 51 using the resist pattern 95 and the control gate electrode 55B as a mask, the semiconductor substrate 51
Forming a high-concentration source region 65 on the first surface region 59 of
A high-concentration drain region 66 that is connected to the low-concentration drain region 58 in the second surface region 60 of the semiconductor substrate 51 is formed to complete one memory element of the stack gate type nonvolatile semiconductor memory device.

As described above, according to the method of manufacturing the nonvolatile semiconductor memory device in the fourth embodiment, the p-type first high-concentration impurity layer 56 and the first high-concentration impurity layer 56 are formed in the drain formation region of the semiconductor substrate 51. The second high-concentration impurity layer 71 having a junction shallower than the high-concentration impurity layer 56 is formed in advance. After that, the first and second high-concentration impurity layers 56 and 71
The end portion of the semiconductor substrate 51 on the source region side is masked to form the concave portion 51b in the semiconductor substrate 51, so that the lower portion of the sidewall 57 of the semiconductor substrate 51 serves as the first surface region (upper stage) and the bottom surface of the concave portion 51b is formed. The step portion 51b which is the second surface region 60 (lower stage) is formed. Subsequently, when the n-type low-concentration drain region 58 is formed by implantation in the second surface region 60, a gap is provided from the upper corner of the step portion 51b due to the compensation effect on the first high-concentration impurity layer 56. Thus, it is possible to reliably form the depletion control layer 56a having a desired impurity profile that faces the corner portion and is adjacent to the low-concentration drain region 58. Besides, the step portion 5
2b between the upper corner of 1b and the depletion control layer 56a.
The high electric field forming layer 71a having the desired impurity profile can be formed of the high concentration impurity layer 71.

In the fourth embodiment, the first high concentration impurity layer 56 and the second high concentration impurity layer 71 are continuously ion-implanted using the same second resist pattern 92. Although the desired impurity profiles were respectively formed by performing the same, the first high-concentration impurity layer can be obtained even if, for example, the first and second ion implantations are performed with different mask patterns instead. 56
It goes without saying that a desired impurity profile can be obtained in the second high-concentration impurity layer 71.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

In the above-described first to fourth embodiments, the depletion control layer 33 is provided on the step portion 16 of the semiconductor substrate 11 so as to be spaced from the step portion 16 and face the step portion 16.
By providing, for example, the carrier path of the channel region formed below the floating gate electrode 23 during the write operation is formed along the step side surface region 15, and the electron temperature high temperature region generated below the step portion 16 is formed. The carrier floating gate electrode 2
We are trying to improve the efficiency of injection into No. 3.

On the other hand, in the fifth embodiment, instead of providing the depletion control layer 33 having the conductivity type opposite to that of the drain region, the substrate voltage whose polarity is opposite to that of the drain voltage with respect to the semiconductor substrate during the write operation. Is applied to form a carrier path in the channel region along the step side surface region 15.

The split gate type and stack gate type non-volatile semiconductor memory devices shown in FIGS. 19A and 19B will be described below.

19 (a) and 19 (b) are sectional views of a memory element of the nonvolatile semiconductor memory device according to the present embodiment, where (a) shows a split gate type and (b) a stack gate. Shows the type. Here, in FIG. 19A, the same components as those shown in FIG. 1 are designated by the same reference numerals, and in FIG. 19B, the same components as those shown in FIG. The same reference numerals are given to the and the description thereof is omitted.

First, as shown in FIG. 19A, in the nonvolatile semiconductor memory device according to the fifth embodiment, a high concentration impurity region 35 having a p-type impurity concentration higher than that of the semiconductor substrate 11 is formed. Is formed in the upper corner of the step portion 16, and a negative voltage is applied to the substrate during the writing operation.

The high-concentration impurity region 35 has the effect of increasing the electron temperature in the step side surface region 15 and the effect of controlling the threshold voltage of the memory element.

When the high-concentration impurity region 35 is formed, the high-concentration impurity region 35 is less likely to be depleted, so that a channel is less likely to be formed, and electrons are generated in the semiconductor substrate 1.
It becomes easy to flow near the interface of the high concentration impurity region 35 of No. 1. In this way, the electrons flow in a path away from the upper and lower corners of the step, so that the electron does not pass through the high temperature region of the electron temperature generated near the lower corner of the step and the drain electrode It directly flows into the floating gate electrode 32 and does not contribute to carrier injection into the floating gate electrode 23.

Therefore, in this embodiment, a negative voltage, for example, -1.0 V is applied to the semiconductor substrate 11 during the write operation.
By applying a voltage of about -5.0 V, the electrons spread and flow toward the step side surface region 15, and carriers of the electron temperature high temperature region generated near the lower corner of the step portion 16 are generated. A path can be formed.

This is because when a negative substrate voltage is applied to the semiconductor substrate 11, the semiconductor substrate 11 provided with the step portion 16 is provided.
In this case, the same effect as when the potential of the floating gate electrode 23 is relatively increased near the upper corner of the step 16 is obtained, and electrons are attracted to the surface of the semiconductor substrate 11. Is. As a result, even if the depletion control layer 33 is not provided, the step portion 16 as shown in FIG.
Carrier paths can be formed in the region surrounded by the upper corners of the.

Further, in the nonvolatile semiconductor memory device according to the present embodiment, the current density increases only when the substrate potential is applied, so that the power consumption when the write operation is not performed can be greatly reduced.

Further, as shown in FIG. 19B, even in the stack gate type nonvolatile semiconductor memory device, the high concentration impurity region 35 having the p type impurity concentration higher than the impurity concentration of the semiconductor substrate 11 is formed. Are formed in the upper corners of the step portion 16 and a negative voltage is applied to the substrate during the write operation, thereby obtaining the same effect as that of the split gate nonvolatile semiconductor memory device shown in FIG. You can

Further, even in the nonvolatile semiconductor memory device provided with the depletion control layer 33 as shown in the first to fourth embodiments, carrier injection is performed by applying the substrate voltage during the write operation. The efficiency can be further improved.

Furthermore, even in a nonvolatile semiconductor memory device having a structure in which the high-concentration impurity region 35 is not provided in the upper corner of the step portion 16, the carrier of the carrier is not applied by applying the negative substrate voltage during the write operation. The injection efficiency can be improved.

Although the memory elements in the first to fifth embodiments are all described as n-channel type elements, p-channel type elements in which the conductivity type of each source region and drain region is p-type. In the case of, the same effect is achieved.
In this case, the conductivity type of the depletion control layer is the n-type opposite to the drain region, and the polarity of the substrate voltage at the time of writing is a positive voltage.

Further, in the present embodiment, the effect in the case of applying the substrate voltage during the write operation has been described, but the similar effect can be produced by appropriately changing the drain voltage and the control gate voltage. .

(Sixth Embodiment) A sixth embodiment of the present invention will be described below with reference to the drawings.

FIG. 20 shows a sectional structure of one memory element of the split gate type nonvolatile semiconductor memory device according to the sixth embodiment. In FIG. 20, the same members as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 20, in the nonvolatile semiconductor memory device according to the sixth embodiment, the source region 31 has the medium concentration layer 31a formed at the end portion on the channel region side and the medium concentration layer 31a formed outside thereof. The drain region 32 is formed of a high-concentration layer 31b having a higher impurity concentration than the layer 31a, and the drain region 32 is formed such that the impurity concentration is sequentially increased from the channel region side to the outer side. It is characterized by comprising a concentration layer 32c. An end of the low concentration layer 32a on the channel region side is formed so as to be in contact with the depletion control layer 33.

Here, with respect to the device of this embodiment, an example of the data write operation, erase operation and read operation will be described with reference to FIGS. 21 (a) and 21 (b).

First, as shown in FIG. 21A, 4.0 V is applied to the control gate electrode 21 during the data write operation.
Apply a voltage of about 7.0V to the source region (not shown)
Voltage of 0 V is applied to the drain region 32 of 4.0 V to
A voltage of about 6.0V is applied. As a result, hot electrons are generated around the corners of the step side surface region 15, and the generated hot electrons are injected into the floating gate electrode 23 through the step side surface region 15.

Next, as shown in FIG. 21B, in the data erasing operation, a voltage of -5.0 V is applied to the control gate electrode 21 and 4.0 V to 7.0 V is applied to the drain region 32.
A voltage of about 0V is applied to the source region (not shown). As a result, the electrons accumulated in the floating gate electrode 23 are drained by the FN type tunnel phenomenon through the third insulating film 25, which is a tunnel oxide film, to the drain region 32.
Pull out in the direction of the arrow.

When reading data, a voltage of about 1.0 V to 3.0 V is applied to the source region, a voltage of 0 V is applied to the drain region 32, and 2.0 V to 4.0 V is applied to the control gate electrode 21. Or a voltage of about 1.0 V to 3.0 V is applied to the drain region 32, a voltage of 0 V is applied to the source region, and a voltage of about 2.0 V to 4.0 V is applied to the control gate electrode 21. Voltage is applied. As a result, a read current having a different current value depending on the amount of charge accumulated in the floating gate electrode 23 is read out to the source region or the drain region.

As described above, in the nonvolatile semiconductor memory device according to the sixth embodiment, the source region 31 is formed in the upper first surface region 13 and the lower second surface region 14 is formed.
Has the step portion 16 in which the drain region 32 is formed. Further, in the vicinity of the step portion 16 in the semiconductor substrate 11, the p-type depletion control layer 33 is formed at a position that does not reach the first surface region 14 and the step side surface region 15. In addition, since the end portion of the depletion control layer 33 on the drain region 32 side is in contact with the low concentration layer 32a of the drain region 32, as described above, the corner portion on the lower side of the step side surface region 15 during the writing operation. A current path is generated that flows toward the high electron temperature region that is generated in the vicinity. Therefore, the electrons that have become hot electrons in the vicinity of the step side surface region 15 are injected into the floating gate electrode 23 through the step side surface region 15, and as a result, high injection efficiency of channel electrons into the floating gate electrode 23 can be obtained. You can

Further, in the sixth embodiment, the drain region 32 is formed from the channel region side to the low concentration layer 32a,
The impurity concentrations of the medium-concentration layer 32b and the high-concentration layer 32c are increased stepwise, in other words, the drain region 32 is set so that the n-type impurity concentration decreases as it approaches the channel region side. Thus, the high concentration layer 32c
Since the intermediate concentration layer 32b having an impurity concentration lower than that of the floating gate electrode 23 is provided in the region 32d below the floating gate electrode 23, the electric field near the region 32d is relaxed during the erase operation, so that the pn junction surface of the region 32d is generated. The number of hot holes is reduced. As a result, it is possible to prevent the reliability of the third insulating film 25, which is the tunnel film, from decreasing.

In the sixth embodiment, FIG.
As shown in FIG.
1a and the high concentration layer 31b are formed, the source region 31
May be formed to have a uniform concentration.

Needless to say, the same effect can be obtained as a split gate flash memory having no step portion 16.

Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

22 to 24 show sectional structures in the order of steps of the method for manufacturing a nonvolatile semiconductor memory device according to the sixth embodiment of the present invention.

First, as shown in FIG. 22A, an element isolation layer 52 having, for example, a trench isolation structure is formed on a semiconductor substrate 51 made of p-type silicon. Then, a first resist pattern 91 having a p-type well region forming pattern of the active region 10 is formed on the semiconductor substrate 51. Then, using the first resist pattern 91 as a mask, boron (B) ions are implanted, for example, at an implantation dose of 0.
Ions are implanted into the semiconductor substrate 51 under an implantation condition of about 5 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² and an implantation energy of about 300 keV, whereby the impurity concentration near the surface of the active region 10 is 5 ×. A p-type well region of about 10 ¹³ cm ⁻³ to 1 × 10 ¹⁴ cm ⁻³ is formed. Further, the implantation dose amount is 0.5 × 10 ¹³ cm ⁻² to 1 × 1 over the entire surface of the active region 10.
Boron (B) ions for controlling the threshold voltage having an implantation energy of about 30 keV are implanted at about 0 ¹³ cm ^-2 .

Next, as shown in FIG. 22B, after removing the first resist pattern 91, a gate oxide film 54 as a first insulating film is formed on the active region 10 by a CVD method or a thermal oxidation method. Form. After that, for example, a first polysilicon film is deposited on the entire surface of the semiconductor substrate 51 by the CVD method, and the deposited first polysilicon film is patterned by the photolithography method to control the polysilicon. The gate electrode 55 is formed. Then, a second resist pattern 92 having an opening in the drain formation region of the active region 10 is formed on the semiconductor substrate 51, and the formed second resist pattern 92 and the gate electrode 55 are used as a mask, for example, implantation dose. 0.5 ×
Boron (B) ions having an implantation energy of about 15 keV at a pressure of about 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² are applied to the semiconductor substrate 5.
1 is ion-implanted through the gate oxide film 54, thereby forming a p-type high-concentration impurity layer 56 in the drain formation region.

Next, as shown in FIG. 22C, after removing the second resist pattern 92, the BPSG is entirely covered on the semiconductor substrate 51 by using, for example, the CVD method.
Deposit the film. Then, anisotropic etching is performed on the deposited BPSG film to form the control gate electrode 5
A side wall 57 made of a BPSG film is formed on the side surface of No. 5. Here, by adjusting the deposited film thickness of BPSG, the distance between the side surface of the control gate electrode 55 and the stepped portion formed on the semiconductor substrate 51 in a later step can be determined in a self-aligned manner.

Next, as shown in FIG. 22D, a third resist pattern 93 having an opening in the drain formation region is formed on the semiconductor substrate 51, and the formed third resist pattern 93 and gate electrode. 55 and sidewall 57
Using as a mask, the semiconductor substrate 51 is dry-etched to form a recess 51a in the drain formation region of the semiconductor substrate 51.

Next, as shown in FIG. 23A, using the third resist pattern 93, the gate electrode 55 and the sidewall 57 as a mask, boron (B) ions which are p-type impurities and n-type impurities are used. Arsenic (As) ions are continuously ion-implanted. Thereby, the semiconductor substrate 5
In the vicinity of the stepped portion in No. 1, the boron ions and the arsenic ions compensate each other, so that the stepped portion 51b on the control gate electrode 55 side of the recess 51a in the semiconductor substrate 51 is located above the stepped portion 51b below the control gate electrode 55. Of the p-type high-concentration impurity formed so as to extend from a position spaced apart from the corner of the step toward the lower corner of the step 51b and contact the low-concentration drain region 58 without reaching the step side surface region. The depletion control layer 56a including the layer 56 can be formed. The boron ion implantation conditions at this time are, for example, an implantation dose amount of 0.5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁴ cm 2.
^The implantation energy is about 25 keV and the implantation angle is about 30 ° with respect to the normal to the substrate surface. The implantation conditions of arsenic ions are, for example, an implantation dose of about 0.5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁴ cm ⁻² , an implantation energy of about 10 keV, and an implantation angle of 0 °.

Next, as shown in FIG. 23B, after removing the third resist pattern 93, the sidewall 5 is removed.
7 and the exposed portion of the gate oxide film 54 are removed by wet etching to form a step portion including an upper first surface region 59, a lower second surface region 60, and a step side surface region 61 connecting the upper and lower steps. 51b and the side surface of the control gate electrode 55 are exposed.

Next, as shown in FIG. 23C, a second insulating film and a third insulating film are formed on the exposed surface including the step portion 51b of the semiconductor substrate 51 and the surface of the control gate electrode 55 by the thermal oxidation method. Forming a thermal oxide film 62. The thermal oxide film 62 may be a silicon oxide film formed by the CVD method or the like.

Next, as shown in FIG. 23D, a second polysilicon film is deposited over the entire surface including the control gate electrode 55 on the semiconductor substrate 51 by using, for example, the CVD method, and the deposited second polysilicon film is deposited. By anisotropically etching the polysilicon film of, the step portion 51b is straddled, and the side surface of the control gate electrode 55 on the step portion 51b side is capacitively coupled via the thermal oxide film 62. Area 60
A floating gate electrode 63 made of polysilicon is formed in a self-aligned manner so as to oppose to the thermal oxide film 62. Here, the floating gate electrode 63 of the thermal oxide film 62 and the semiconductor substrate 5 are
The region sandwiched between 1 and 1 functions as a tunnel film.

Subsequently, phosphorus (P) is applied to the semiconductor substrate 51 using the control gate electrode 55 and the floating gate electrode 63 as a mask.
By implanting ions, a medium concentration source region 68 is formed in a region of the semiconductor substrate 51 opposite to the floating gate electrode 63 with respect to the control gate electrode 55, and at the same time, in the region of the semiconductor substrate 51 on the floating gate electrode 63 side. A medium concentration drain region 69 is formed. The phosphorus ion implantation conditions at this time are, for example, an implantation dose amount of 5 × 10 ¹² cm ^{−2 to} 5 × 10 5.
^The implantation energy is about ¹³ cm ⁻² and the implantation energy is about 20 keV.

Next, as shown in FIG. 24A, an insulating film of silicon oxide or the like is formed on the entire surface of the semiconductor substrate 51, and then the formed insulating film is etched to control the control gate electrode 55 and floating. The insulating film sidewall 72 is formed on the side surface of the gate electrode 63.

Next, as shown in FIG. 24B, arsenic (A) is deposited on the semiconductor substrate 51 using the control gate electrode 55, the floating gate electrode 63 and the insulating film sidewall 72 as a mask.
s) by implanting ions, a high concentration source region 65 is formed in a region of the semiconductor substrate 51 opposite to the floating gate electrode 63 with respect to the control gate electrode 55.
A high-concentration drain region 66 that is connected to the medium-concentration drain region 69 in a region on the side of the floating gate electrode 63 with respect to one control gate electrode 55 is formed to complete one memory element of the nonvolatile semiconductor memory device. The arsenic ion implantation conditions here are, for example, an implantation dose amount of 1 × 10 ¹⁵ cm ^{−2 to} 5 × 1.
The implantation energy is about ¹⁵ cm ⁻² and the implantation energy is about 40 keV.

As described above, according to the manufacturing method of the sixth embodiment, the p-type depletion limiting layer 56a can be formed in the p-type semiconductor substrate 51 in the vicinity of the step portion 51b. Further, it is possible to reliably form the drain region including the low-concentration drain region 58, the medium-concentration drain region 69, and the high-concentration drain region 66 in which the n-type impurity concentration is gradually increased from the channel region side.

(Modification of Sixth Embodiment) Hereinafter, a modification of the sixth embodiment of the present invention will be described with reference to the drawings.

FIG. 25 shows a sectional structure of a memory element of a split gate type nonvolatile semiconductor memory device according to a modification of the sixth embodiment. In FIG. 25, FIG.
The same components as those of the sixth embodiment shown in FIG.

As shown in FIG. 25, in the nonvolatile semiconductor memory device according to the present modification, a high level formed by diffusing p-type impurities formed in the upper corner of the step portion 16 instead of the depletion control layer. It is characterized by having an electric field forming layer 34. Here, the p-type impurity concentration of the high electric field forming layer 34 is set to be higher than the p-type impurity concentration of the semiconductor substrate 11. The end portion of the high electric field forming layer 34 on the drain region 32 side is in contact with the low concentration layer 32a.

By providing the p-type high electric field formation layer 34 between the upper corner of the step portion 16 and the low concentration layer 32a of the drain region 32, the high electric field formation layer 34 and the drain are formed in the step side surface region 15. The gradient of the energy level due to the pn junction composed of the interface with the region 32 becomes steeper. As a result, a high electric field is generated at the interface between the high electric field forming layer 34 and the low concentration layer 32a, and the electron temperature in the vicinity of the lower corner of the step 16 rises. As a result, the amount of hot electrons generated by electrons in the channel increases, and the floating gate electrode 2
The electron injection efficiency with respect to 3 is further improved.

In this modification, the boron (B) ion implantation shown in FIG. 22B and the boron (B) ion and arsenic (As) ion implantation shown in FIG. 23A are performed. It can be realized by adjusting the implantation acceleration voltage and the dose amount in and, for example, by increasing the dose amount of boron ions by the angle implantation in FIG. Further, even if the boron (B) ion implantation shown in FIG. 22B is not performed and only the boron (B) ion and arsenic (As) ion implantation step shown in FIG. 23A is performed. good.

Also in this modification, the source region 3
Although 1 is divided into the medium concentration layer 31a and the high concentration layer 31b, it may be formed with a uniform concentration.

Further, the same effect can be obtained as a split gate type flash memory having no step portion 16.

(Seventh Embodiment) Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings.

FIG. 26 shows a sectional structure of one memory element of the split gate type nonvolatile semiconductor memory device according to the seventh embodiment. 26, the sixth shown in FIG.
The same components as those of the embodiment will be designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 26, in the nonvolatile semiconductor memory device according to the seventh embodiment, the source region 31 in the first surface region 13 is covered so as to cover the junction surface of the source region 31 with the semiconductor substrate 11. It is characterized in that it has a short channel effect suppressing region 36 formed of a p-type impurity region and formed in the lower outer peripheral portion. in this way,
Since the p-type short channel effect suppression region 36 is provided between the n-type source region 31 and the channel region, the electric field between the source region 31 and the drain region 32 is relaxed, so that the short channel effect is suppressed. Therefore, the device size can be reduced.

Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device configured as described above will be described with reference to the drawings.

27 to 29 show sectional structures in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the seventh embodiment of the present invention.

First, as shown in FIG. 27A, an element isolation layer 52 having, for example, a trench isolation structure is formed on a semiconductor substrate 51 made of p-type silicon. Then, a first resist pattern 91 having a p-type well region forming pattern of the active region 10 is formed on the semiconductor substrate 51. Then, using the first resist pattern 91 as a mask, boron (B) ions are implanted, for example, at an implantation dose of 0.
Ions are implanted into the semiconductor substrate 51 under an implantation condition of about 5 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² and an implantation energy of about 300 keV, whereby the impurity concentration near the surface of the active region 10 is 5 ×. A p-type well region of about 10 ¹³ cm ⁻³ to 1 × 10 ¹⁴ cm ⁻³ is formed. Further, the implantation dose amount is 0.5 × 10 ¹³ cm ⁻² to 1 × 1 over the entire surface of the active region 10.
Boron (B) ions for controlling the threshold voltage having an implantation energy of about 30 keV are implanted at about 0 ¹³ cm ^-2 .

Next, as shown in FIG. 27B, after removing the first resist pattern 91, a gate oxide film 54 as a first insulating film is formed on the active region 10 by a CVD method or a thermal oxidation method. Form. After that, for example, a first polysilicon film is deposited on the entire surface of the semiconductor substrate 51 by the CVD method, and the deposited first polysilicon film is patterned by the photolithography method to control the polysilicon. The gate electrode 55 is formed. Then, a second resist pattern 92 having an opening in the drain formation region of the active region 10 is formed on the semiconductor substrate 51, and the formed second resist pattern 92 and the gate electrode 55 are used as a mask, for example, implantation dose. 0.5 ×
Boron (B) ions having an implantation energy of about 15 keV at a pressure of about 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² are applied to the semiconductor substrate 5.
1 is ion-implanted through the gate oxide film 54, thereby forming a p-type high-concentration impurity layer 56 in the drain formation region.

Next, as shown in FIG. 27C, after removing the second resist pattern 92, the BPSG is entirely over the semiconductor substrate 51 by using, for example, the CVD method.
Deposit the film. Then, anisotropic etching is performed on the deposited BPSG film to form the control gate electrode 5
A side wall 57 made of a BPSG film is formed on the side surface of No. 5. Here, by adjusting the deposited film thickness of BPSG, the distance between the side surface of the control gate electrode 55 and the stepped portion formed on the semiconductor substrate 51 in a later step can be determined in a self-aligned manner.

Next, as shown in FIG. 27D, a third resist pattern 93 having an opening in the drain formation region is formed on the semiconductor substrate 51, and the formed third resist pattern 93 and gate electrode. 55 and sidewall 57
Using as a mask, the semiconductor substrate 51 is dry-etched to form a recess 51a in the drain formation region of the semiconductor substrate 51.

Next, as shown in FIG. 28A, using the third resist pattern 93, the gate electrode 55, and the sidewall 57 as a mask, boron (B) ions that are p-type impurities and n-type impurities are used. Arsenic (As) ions are continuously ion-implanted. Thereby, the semiconductor substrate 5
In the vicinity of the stepped portion in No. 1, the boron ions and the arsenic ions compensate each other, so that the stepped portion 51b on the control gate electrode 55 side of the recess 51a in the semiconductor substrate 51 is located above the stepped portion 51b below the control gate electrode 55. Of the p-type high-concentration impurity formed so as to extend from a position spaced apart from the corner of the step toward the lower corner of the step 51b and contact the low-concentration drain region 58 without reaching the step side surface region. The depletion control layer 56a including the layer 56 can be formed. The boron ion implantation conditions at this time are, for example, an implantation dose amount of 0.5 × 10 ¹⁴ cm ^{−2 to} 5 × 10 ¹⁴ cm 2.
^The implantation energy is about 25 keV and the implantation angle is 30 ° with respect to the normal to the substrate surface. Also,
Arsenic ion implantation conditions are, for example, an implantation dose amount of 0.5.
× and ^{10 14 cm -2 ~5 × 10 14} cm -2 order, an implantation energy of about 10 keV, the implantation angle is set to 0 °.

Next, as shown in FIG. 28B, after removing the third resist pattern 93, the sidewall 5 is removed.
7 and the exposed portion of the gate oxide film 54 are removed by wet etching to form a step portion including an upper first surface region 59, a lower second surface region 60, and a step side surface region 61 connecting the upper and lower steps. 51b and the side surface of the control gate electrode 55 are exposed. Subsequently, a fourth resist pattern 94 having an opening in the source formation region of the active region 10 is formed on the semiconductor substrate 51, and the formed fourth resist pattern 94 and the gate electrode 55 are used as a mask, for example, implantation dose. The amount is 0.5 × 10 ¹³ cm ^-2 ~
The implantation energy is about 30 ke at about 5 × 10 ¹³ cm ^-2.
Boron (B) ion of V is about 30 ° with respect to the normal to the substrate
Are ion-implanted into the semiconductor substrate 51 at a certain angle, thereby forming the p-type short channel effect suppression layer 70 in the source formation region.

Next, as shown in FIG. 28C, after removing the fourth resist pattern 94, a thermal oxidation method is used.
A thermal oxide film 62 as a second insulating film and a third insulating film is formed on the exposed surface of the semiconductor substrate 51 including the step portion 51b and the surface of the control gate electrode 55. The thermal oxide film 62 is CV.
It may be a silicon oxide film formed by the D method or the like.

Next, as shown in FIG. 28D, a second polysilicon film is deposited over the entire surface including the control gate electrode 55 on the semiconductor substrate 51 by using, for example, the CVD method, and the deposited second polysilicon film is deposited. By anisotropically etching the polysilicon film of, the step portion 51b is straddled, and the side surface of the control gate electrode 55 on the step portion 51b side is capacitively coupled via the thermal oxide film 62. Area 60
A floating gate electrode 63 made of polysilicon is formed in a self-aligned manner so as to oppose to the thermal oxide film 62. Here, the floating gate electrode 63 of the thermal oxide film 62 and the semiconductor substrate 5 are
The region sandwiched between 1 and 1 functions as a tunnel film.

Next, as shown in FIG. 29, a fifth resist pattern 95 having an opening pattern in the source formation region and the drain formation region is formed, and the formed fifth resist pattern 95, control gate electrode 55 and floating pattern are formed. By implanting arsenic (As) ions into the semiconductor substrate 51 using the gate electrode 63 as a mask, the short channel effect suppressing layer 70 is formed in a region of the semiconductor substrate 51 opposite to the floating gate electrode 63 with respect to the control gate electrode 55. A high-concentration source region 65 is formed inside the high-concentration drain region 6 which is connected to the low-concentration drain region 58 on the floating gate electrode 63 side of the control gate electrode 55 of the semiconductor substrate 51.
6 is formed, and one memory element of the nonvolatile semiconductor memory device is completed.

As described above, according to the manufacturing method of the seventh embodiment, the p-type depletion limiting layer 56a can be formed in the p-type semiconductor substrate 51 in the vicinity of the step portion 51b. In addition, the n-type high-concentration source region 65
It is possible to reliably form the p-type short channel effect suppression layer 70 that covers the junction surface from below.

Needless to say, even a split gate type flash memory having no step portion 16 has the effect of suppressing the short channel effect.

(Modification of Seventh Embodiment) A modification of the seventh embodiment of the present invention will be described below with reference to the drawings.

FIG. 30 shows a sectional structure of one memory element of a split gate type nonvolatile semiconductor memory device according to a modification of the seventh embodiment. In FIG. 30, FIG.
The same members as those of the seventh embodiment shown in FIG.

As shown in FIG. 30, in the nonvolatile semiconductor memory device according to the present modification, a high level formed by diffusing p-type impurities formed in the upper corners of the step portion 16 instead of the depletion control layer. It is characterized by having an electric field forming layer 34. Here, the p-type impurity concentration of the high electric field forming layer 34 is set to be higher than the p-type impurity concentration of the semiconductor substrate 11. The end of the high electric field forming layer 34 on the drain region 32 side is in contact with the low concentration layer 32a.

By providing the p-type high electric field forming layer 34 between the upper corner of the step portion 16 and the low concentration layer 32a of the drain region 32, the high electric field forming layer 34 and the drain are formed in the step side surface region 15. The gradient of the energy level due to the pn junction composed of the interface with the region 32 becomes steeper. As a result, a high electric field is generated at the interface between the high electric field forming layer 34 and the low concentration layer 32a, and the electron temperature in the vicinity of the lower corner of the step 16 rises. As a result, the amount of hot electrons generated by electrons in the channel increases, and the floating gate electrode 2
The electron injection efficiency with respect to 3 is further improved.

In this modification, the boron (B) ion implantation shown in FIG. 27B and the boron (B) ion and arsenic (As) ion implantation shown in FIG. 28A are performed. It can be realized by adjusting the injection accelerating voltage and the dose amount. Furthermore, FIG. 27 (b)
Without performing the boron (B) ion implantation shown in
The boron (B) ion and arsenic (A) shown in FIG.
s) Only the ion implantation step may be performed.

(Eighth Embodiment) An eighth embodiment of the present invention will be described below with reference to the drawings.

FIG. 31 shows a sectional structure of one memory element of the stack gate type nonvolatile semiconductor memory device according to the eighth embodiment. In FIG. 31, the same members as those of the third embodiment shown in FIG. 11 are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 31, in the nonvolatile semiconductor memory device according to the eighth embodiment, the source region 31 has a medium-concentration layer 31a formed at the end on the channel region side and a medium-concentration layer formed outside thereof. The drain region 32 is formed of a high-concentration layer 31b having a higher impurity concentration than the layer 31a, and the drain region 32 is formed such that the impurity concentration is sequentially increased from the channel region side to the outer side. It is characterized by comprising a concentration layer 32c. Here, the low concentration layer 3
The end of 2a on the channel region side is formed so as to be in contact with the depletion control layer 33.

With this structure, as in the third embodiment, during the write operation, the p-type impurity concentration of the depletion control layer 33 is high, so that depletion does not occur and the first surface region 13 and the step side surface of the semiconductor substrate 11 are not depleted. A portion surrounded by the region 15 and the depletion control layer 33 is depleted and functions as a channel. As a result, the electrons in the channel are transferred to the step side surface region 15
As a result, the carriers flow toward the floating gate electrode 23A in an expanded manner, and the efficiency of carrier injection into the floating gate electrode 23A can be improved.

Moreover, as in the sixth embodiment, since the medium concentration layer 32b having a lower impurity concentration than the high concentration layer 32c is provided in the region below the floating gate electrode 23A, the lower concentration layer 32b is formed during the erase operation. Since the electric field in the vicinity of the side region is relaxed, the number of hot holes generated in the pn junction surface in the vicinity thereof is reduced. As a result, it is possible to prevent the reliability of the first insulating film 22, which is the tunnel film, from decreasing.

Note that, in the eighth embodiment, FIG.
As shown in FIG.
1a and the high concentration layer 31b are formed, the source region 31
May be formed with a uniform concentration.

Needless to say, the same effect can be obtained even with a split gate type flash memory having no step portion 16.

Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device having the above structure will be described with reference to the drawings.

32 to 34 show sectional structures in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the eighth embodiment of the present invention.

First, as shown in FIG. 32A, an element isolation layer 52 having, for example, a trench isolation structure is formed on a semiconductor substrate 51 made of p-type silicon. Then, a first resist pattern 91 having a p-type well region forming pattern of the active region 10 is formed on the semiconductor substrate 51. Then, using the first resist pattern 91 as a mask, boron (B) ions are implanted, for example, at an implantation dose of 0.
Ions are implanted into the semiconductor substrate 51 under an implantation condition of about 5 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² and an implantation energy of about 300 keV, whereby the impurity concentration near the surface of the active region 10 is 5 ×. A p-type well region of about 10 ¹³ cm ⁻³ to 1 × 10 ¹⁴ cm ⁻³ is formed. Further, the implantation dose amount is 0.5 × 10 ¹³ cm ⁻² to 1 × 1 over the entire surface of the active region 10.
Boron (B) ions for controlling the threshold voltage having an implantation energy of about 30 keV are implanted at about 0 ¹³ cm ^-2 .

Next, as shown in FIG. 32B, after removing the first resist pattern 91, a second resist pattern having an opening in the drain formation region of the active region 10 is formed on the semiconductor substrate 51. 92 is formed, and using the formed second resist pattern 92 as a mask, for example, the implantation dose is about 0.5 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² ,
Boron (B) ions having an implantation energy of about 15 keV are ion-implanted into the semiconductor substrate 51 through the protective insulating film 53, thereby forming the p-type high-concentration impurity layer 56 in the drain formation region.

Next, as shown in FIG. 32C, after the second resist pattern 92 is removed, the source formation region and the end portion of the high-concentration impurity layer 56 on the source formation region side are formed on the semiconductor substrate 51. Resist pattern 9 for masking
3 is formed, and the semiconductor substrate 51 is dry-etched using the formed third resist pattern 93 as a mask to form a recess 51a in the drain formation region of the semiconductor substrate 51. At this time, the mask amount (overlap amount) of the end portion of the high concentration impurity layer 56 on the source formation region side
Can be adjusted to optimize the dimension in the gate length direction of the depletion control layer 56a formed from the high-concentration impurity layer 56 in a later step.

Next, as shown in FIG. 32D, using the third resist pattern 93 as a mask, boron (B) ions that are p-type impurities and arsenic (As) that is n-type impurities are used.
Ions are continuously ion-implanted. As a result, in the vicinity of the step portion of the semiconductor substrate 51, the boron ions and the arsenic ions compensate each other, and the step portion 51b of the recess 51a of the semiconductor substrate 51 on the control gate electrode 55 side.
Of the low-concentration drain region without reaching the step side surface region while extending from a position spaced from the upper corner of the step 51b below the control gate electrode 55 toward the lower corner of the step 51b. Depletion control layer 56 formed of p-type high concentration impurity layer 56 formed in contact with 58
a can be formed. At this time, the boron ion and arsenic ion implantation conditions are such that the implantation dose amount is 0.5 × 1.
The implantation angle is about 0 ¹⁴ cm ^{-2 to} 5 × 10 ¹⁴ cm ^-2 , the implantation energy is about 10 keV, and only boron ions are implanted at an angle of about 30 °.

Next, as shown in FIG. 33A, by removing the third resist pattern 93, the upper surface of the semiconductor substrate 51, that is, the upper surface of the first surface region 5 is formed.
9. The step portion 51b including the second surface area 60 which is the lower step and the step side surface area 61 which connects the upper step and the lower step is exposed.

Next, as shown in FIG. 33B, a gate oxide film 54 as a first insulating film is formed on the exposed surface of the semiconductor substrate 51 including the step portion 51b by a thermal oxidation method. After that, the first polysilicon film 63A, the silicon oxide film 67A as the second insulating film, and the second polysilicon film 55A are deposited over the entire surface of the gate oxide film 54 by using, for example, the CVD method. The silicon oxide film 67A
May be formed as a thermal oxide film.

Next, as shown in FIG. 33C, a fourth resist pattern 94 having a gate electrode pattern straddling the step portion 51b is formed on the second polysilicon 55A, and the formed fourth resist pattern 94 is formed. Using the resist pattern 94 as a mask, the second polysilicon film 55A and the silicon oxide film 67 are formed.
A and the first polysilicon film 63A are anisotropically etched to form a floating gate electrode electrode 63B made of the first polysilicon film 63A and a silicon oxide film 67A.
And the second polysilicon film 5 and the capacitive insulating film 67B made of
The floating gate electrode 55B made of 5A is formed.
Here, the gate oxide film 54 between the semiconductor substrate 51 and the floating gate electrode 63B functions as a tunnel film.

Next, as shown in FIG. 33D, the fourth resist pattern 94 is removed, and then a fifth resist pattern 95 having an opening pattern in the source formation region and the drain formation region is formed. By using the formed fifth resist pattern 95 and control gate electrode 55B as a mask, arsenic (As) ions are implanted into the semiconductor substrate 51 to form a medium concentration source region 68 in the first surface region 59 of the semiconductor substrate 51. A medium-concentration drain region 69 that is connected to the low-concentration drain region 58 in the second surface region 60 of the semiconductor substrate 51 is formed.

Next, as shown in FIG. 34A, an insulating film such as silicon oxide is formed on the entire surface of the semiconductor substrate 51, and then the formed insulating film is etched to form the floating gate electrode 63B and control. The insulating film sidewall 72 is formed on each side surface of the gate electrode 55B.

Next, as shown in FIG. 34B, a sixth resist pattern 96 having an opening pattern in the source formation region and the drain formation region is formed, and the formed sixth resist pattern 96 and control gate electrode. By implanting arsenic (As) ions into the semiconductor substrate 51 using the 55B and the insulating film sidewall 72 as a mask, the high concentration source region 65 connected to the medium concentration source region 68 is formed in the first surface region 59 of the semiconductor substrate 51. Then, a high-concentration drain region 66 that is connected to the second surface region 60 of the semiconductor substrate 51 and the medium-concentration drain region 69 is formed to complete one memory element of the stack gate type nonvolatile semiconductor memory device.

As described above, according to the manufacturing method of the eighth embodiment, the p-type depletion control layer 56a can be formed in the p-type semiconductor substrate 51 in the vicinity of the step portion 51b. Further, it is possible to reliably form the drain region including the low-concentration drain region 58, the medium-concentration drain region 69, and the high-concentration drain region 66 in which the n-type impurity concentration is gradually increased from the channel region side.

(Modification of Eighth Embodiment) A modification of the eighth embodiment of the present invention will be described below with reference to the drawings.

FIG. 35 shows a cross-sectional structure of a memory element of a stack gate type non-volatile semiconductor memory device according to a modification of the eighth embodiment. In FIG. 35, the same components as those of the eighth embodiment shown in FIG. 31 are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 35, in the nonvolatile semiconductor memory device according to the present modification, a high level formed by diffusing p-type impurities formed in the upper corners of the step portion 16 instead of the depletion control layer. It is characterized by having an electric field forming layer 34. Here, the p-type impurity concentration of the high electric field forming layer 34 is set to be higher than the p-type impurity concentration of the semiconductor substrate 11. The end portion of the high electric field forming layer 34 on the drain region 32 side is in contact with the low concentration layer 32a.

By providing the p-type high electric field forming layer 34 between the upper corner of the step portion 16 and the low concentration layer 32a of the drain region 32, the high electric field forming layer 34 and the drain are formed in the step side surface region 15. The gradient of the energy level due to the pn junction composed of the interface with the region 32 becomes steeper. As a result, a high electric field is generated at the interface between the high electric field forming layer 34 and the low concentration layer 32a, and the electron temperature in the vicinity of the lower corner of the step 16 rises. As a result, the amount of hot electrons generated by electrons in the channel increases, and the floating gate electrode 2
The efficiency of injecting electrons into 3A is further improved.

In this modification, the boron (B) ion implantation shown in FIG. 32B and the boron (B) ion and arsenic (As) ion implantation shown in FIG. 32D are performed. It can be realized by adjusting the implantation acceleration voltage and the dose amount in and. Furthermore, without performing the boron (B) ion implantation shown in FIG.
Boron (B) ion and arsenic (As) shown in 2 (d)
Only the ion implantation step may be performed.

Further, also in this modification, the source region 3
Although 1 is divided into the medium concentration layer 31a and the high concentration layer 31b, it may be formed with a uniform concentration.

Further, the same effect can be obtained as a split gate type flash memory having no step portion 16.

(Ninth Embodiment) A ninth embodiment of the present invention will be described below with reference to the drawings.

FIG. 36 shows a sectional structure of one memory element of the stack gate type nonvolatile semiconductor memory device according to the ninth embodiment. In FIG. 36, the same components as those of the eighth embodiment shown in FIG. 31 are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 36, in the nonvolatile semiconductor memory device according to the ninth embodiment, the source region 31 in the first surface region 13 is covered so as to cover the junction surface of the source region 31 with the semiconductor substrate 11. It is characterized in that it has a short channel effect suppressing region 36 formed of a p-type impurity region and formed in the lower outer peripheral portion. in this way,
Since the p-type short channel effect suppression region 36 is provided between the n-type source region 31 and the channel region, the electric field between the source region 31 and the drain region 32 is relaxed, so that the short channel effect is suppressed. Therefore, the device size can be reduced.

Hereinafter, a method of manufacturing the nonvolatile semiconductor memory device having the above structure will be described with reference to the drawings.

37 to 39 show sectional structures in the order of steps of the method for manufacturing the nonvolatile semiconductor memory device according to the ninth embodiment of the present invention.

First, as shown in FIG. 37A, an element isolation layer 52 having, for example, a trench isolation structure is formed on a semiconductor substrate 51 made of p-type silicon. Then, a first resist pattern 91 having a p-type well region forming pattern of the active region 10 is formed on the semiconductor substrate 51. Then, using the first resist pattern 91 as a mask, boron (B) ions are implanted, for example, at an implantation dose of 0.
Ions are implanted into the semiconductor substrate 51 under an implantation condition of about 5 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² and an implantation energy of about 300 keV, whereby the impurity concentration near the surface of the active region 10 is 5 ×. A p-type well region of about 10 ¹³ cm ⁻³ to 1 × 10 ¹⁴ cm ⁻³ is formed. Further, the implantation dose amount is 0.5 × 10 ¹³ cm ⁻² to 1 × 1 over the entire surface of the active region 10.
Boron (B) ions for controlling the threshold voltage having an implantation energy of about 30 keV are implanted at about 0 ¹³ cm ^-2 .

Next, as shown in FIG. 37B, after removing the first resist pattern 91, a second resist pattern having an opening in the drain formation region of the active region 10 is formed on the semiconductor substrate 51. 92 is formed, and using the formed second resist pattern 92 as a mask, for example, the implantation dose is about 0.5 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² ,
Boron (B) ions having an implantation energy of about 15 keV are ion-implanted into the semiconductor substrate 51 through the protective insulating film 53, thereby forming the p-type high-concentration impurity layer 56 in the drain formation region.

Next, as shown in FIG. 37C, after the second resist pattern 92 is removed, the source formation region and the end portion of the high-concentration impurity layer 56 on the source formation region side are formed on the semiconductor substrate 51. Resist pattern 9 for masking
3 is formed, and the semiconductor substrate 51 is dry-etched using the formed third resist pattern 93 as a mask to form a recess 51a in the drain formation region of the semiconductor substrate 51. At this time, the mask amount (overlap amount) of the end portion of the high concentration impurity layer 56 on the source formation region side
Can be adjusted to optimize the dimension in the gate length direction of the depletion control layer 56a formed from the high-concentration impurity layer 56 in a later step.

Next, as shown in FIG. 37D, using the third resist pattern 93 as a mask, boron (B) ions that are p-type impurities and arsenic (As) that is n-type impurities are used.
Ions are continuously ion-implanted. As a result, in the vicinity of the step portion of the semiconductor substrate 51, the boron ions and the arsenic ions compensate each other, and the step portion 51b of the recess 51a of the semiconductor substrate 51 on the control gate electrode 55 side.
In addition, the low-concentration drain region extends from the position below the control gate electrode 55 and spaced from the upper corner of the step 51b toward the lower corner of the step 51b, without reaching the step side surface region. Depletion control layer 56 formed of p-type high concentration impurity layer 56 formed in contact with 58
a can be formed. At this time, the boron ion and arsenic ion implantation conditions are such that the implantation dose amount is 0.5 × 1.
The implantation angle is about 0 ¹⁴ cm ^{-2 to} 5 × 10 ¹⁴ cm ^-2 , the implantation energy is about 10 keV, and only boron ions are implanted at an angle of about 30 °.

Next, as shown in FIG. 38A, by removing the third resist pattern 93, the upper surface of the semiconductor substrate 51, that is, the first surface region 5 which is the upper step is formed.
9. The step portion 51b including the second surface area 60 which is the lower step and the step side surface area 61 which connects the upper step and the lower step is exposed.

Next, as shown in FIG. 38B, a gate oxide film 54 as a first insulating film is formed on the exposed surface of the semiconductor substrate 51 including the step portion 51b by a thermal oxidation method. After that, the first polysilicon film 63A, the silicon oxide film 67A as the second insulating film, and the second polysilicon film 55A are deposited over the entire surface of the gate oxide film 54 by using, for example, the CVD method. The silicon oxide film 67A
May be formed as a thermal oxide film.

Next, as shown in FIG. 38C, a fourth resist pattern 94 having a gate electrode pattern straddling the step portion 51b is formed on the second polysilicon 55A, and a fourth resist pattern 94 is formed. Using the resist pattern 94 as a mask, the second polysilicon film 55A and the silicon oxide film 67 are formed.
A and the first polysilicon film 63A are anisotropically etched to form a floating gate electrode electrode 63B made of the first polysilicon film 63A and a silicon oxide film 67A.
And the second polysilicon film 5 and the capacitive insulating film 67B made of
The floating gate electrode 55B made of 5A is formed.
Here, the gate oxide film 54 between the semiconductor substrate 51 and the floating gate electrode 63B functions as a tunnel film.

Next, as shown in FIG. 38D, a fifth resist pattern 95 having an opening in the source formation region of the active region 10 is formed on the semiconductor substrate 51, and the formed fifth resist is formed. Using the pattern 95 and the gate electrode 55B as a mask, for example, the implantation dose is 0.5 × 10 ¹³ cm.
^{-2 to} 5 × 10 ¹³ cm ^-2 , the implantation energy is about 30
Boron (B) ions of keV are ion-implanted into the semiconductor substrate 51, thereby forming the p-type short channel effect suppression layer 70 in the source formation region.

Next, as shown in FIG. 39, after removing the fifth resist pattern 95, a sixth resist pattern 96 having an opening pattern of the source formation region and the drain formation region is formed, and the formed sixth resist pattern 96 is formed. Resist pattern 9
By implanting arsenic (As) ions into the semiconductor substrate 51 using the control gate electrode 6 and the control gate electrode 55B as a mask, the high-concentration source region 65 is formed in the first surface region 59 of the semiconductor substrate 51 and inside the short channel effect suppression layer 70. And a high-concentration drain region 66 that is connected to the low-concentration drain region 58 in the second surface region 60 of the semiconductor substrate 51 is formed to complete one memory element of the stack gate type nonvolatile semiconductor memory device.

As described above, according to the manufacturing method of the ninth embodiment, the p-type depletion control layer 56a can be formed in the p-type semiconductor substrate 51 near the step portion 51b. In addition, the n-type high-concentration source region 65
P-type short channel effect suppression layer 70 covering the junction surface of
Can be reliably formed.

Needless to say, even a split gate type flash memory having no step portion 16 has the effect of suppressing the short channel effect.

(Modification of Ninth Embodiment) A modification of the ninth embodiment of the present invention will be described below with reference to the drawings.

FIG. 40 shows a cross-sectional structure of one memory element in a stack gate type non-volatile semiconductor memory device according to a modification of the ninth embodiment. 40, the same components as those of the ninth embodiment shown in FIG. 36 are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 40, in the nonvolatile semiconductor memory device according to this modification, a high level formed by diffusing p-type impurities formed in the upper corners of the step portion 16 instead of the depletion control layer. It is characterized by having an electric field forming layer 34. Here, the p-type impurity concentration of the high electric field forming layer 34 is set to be higher than the p-type impurity concentration of the semiconductor substrate 11. The end of the high electric field forming layer 34 on the drain region 32 side is in contact with the low concentration layer 32a.

By providing the p-type high electric field formation layer 34 between the upper corner of the step portion 16 and the low concentration layer 32a of the drain region 32, the high electric field formation layer 34 and the drain are formed in the step side surface region 15. The gradient of the energy level due to the pn junction composed of the interface with the region 32 becomes steeper. As a result, a high electric field is generated at the interface between the high electric field forming layer 34 and the low concentration layer 32a, and the electron temperature in the vicinity of the lower corner of the step 16 rises. As a result, the amount of hot electrons generated by electrons in the channel increases, and the floating gate electrode 2
The efficiency of injecting electrons into 3A is further improved.

This modification is based on the boron (B) ion implantation shown in FIG. 37 (b) and the boron (B) ion and arsenic (As) ion implantation shown in FIG. 37 (d). It can be realized by adjusting the injection accelerating voltage and the dose amount. Furthermore, FIG. 37 (b)
Without performing the boron (B) ion implantation shown in
Boron (B) ions and arsenic (A) shown in FIG.
s) Only the ion implantation step may be performed.

(Tenth Embodiment) The first embodiment of the present invention will be described below.
Embodiment No. 0 will be described with reference to the drawings.

The tenth embodiment is a method for controlling a nonvolatile semiconductor memory device according to the present invention, which is a bias applying method when electrons stored in a floating gate electrode are extracted (erasing operation).

41 (a) and 41 (b) show an enlarged cross-sectional structure in the vicinity of the step portion 16 in the split gate type nonvolatile semiconductor memory device according to the seventh embodiment, for example. 41 (a) and 41 (b), the same components as those shown in FIG. 26 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 41A, as the erase bias condition, for example, the applied voltage to the control gate electrode 21 is -6V to -8V and the applied voltage to the drain region 32 is 5V to 6V. In this way, FIG.
As shown in FIG. 1A, hot holes are generated in the region 11a of the drain region 32 of the semiconductor substrate 11 below the low-concentration layer 32a.

Further, under the erase bias condition described above, the hot holes generated under the drain region 32 travel in the direction of arrow A, and the first insulating film 2 as the gate insulating film is formed.
2. There is a possibility that the second insulating film 24 serving as the capacitive insulating film or the third insulating film 25 serving as the tunnel insulating film may be captured by the end portion on the control gate electrode 21 side. When hot holes are captured at these locations, they are close to the channel region,
The current value of the read current will decrease.

Therefore, in the tenth embodiment, in FIG. 41 (b), as the erase bias condition, for example, the applied voltage to the control gate electrode 21 is −4V to −.
5V, the applied voltage to the drain region 32 is 6V ~
It is set to 7V. That is, the control gate bias is reduced and the drain bias is increased. By doing this, as shown in FIG. 41B, the hot holes generated in the region 11a below the low concentration layer 32a of the drain region 32 are in the direction of arrow B, that is, the third insulating film (tunnel film). ) 25, it travels to the lower side of the floating gate electrode 23 and is captured in a portion of the third insulating film 25 distant from the channel region. In this way, the hot holes are captured in the portion distant from the channel region, so that the influence on the read current value can be reduced.

The bias condition according to the tenth embodiment greatly varies depending on the device design rule, and is not limited to the above voltage range.

Further, although the split gate type flash memory having the step portion 16 has been described in the present embodiment, it goes without saying that the split gate type flash memory having no step portion 16 has the same effect.

[0273]

According to the first or second non-volatile semiconductor memory device of the present invention, the path of carriers flowing toward the high electron temperature region generated near the lower corner of the step portion during the write operation. Therefore, electrons that have become hot electrons near and below the step side surface region can be efficiently injected into the floating gate electrode from the step side surface region.

Further, in the third or fifth nonvolatile semiconductor memory device according to the present invention, since the electric field in the peripheral portion of the drain region on the channel side is relaxed, the generation of hot holes generated in the peripheral portion of the channel is suppressed. Therefore, it is possible to prevent a decrease in reliability of the tunnel film. In addition, the short channel effect can be suppressed.

In the fourth or sixth nonvolatile semiconductor memory device according to the present invention, the electric field between the source and the drain is relaxed and the short channel effect is suppressed, so that the device size can be reduced. .

[Brief description of drawings]

FIG. 1 is a configuration cross-sectional view showing one memory element of a split gate nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is an enlarged view of the vicinity of a step in the split gate type nonvolatile semiconductor memory device according to the first embodiment of the present invention, in which electrons are generated near the lower corner of the step and the electron temperature is high. It is sectional drawing which shows a mode that flows toward an area.

FIG. 3A is an enlarged view of the vicinity of a step portion of the split gate type nonvolatile semiconductor memory device according to the first embodiment of the present invention, showing a simulation result of a current density during a write operation by a computer. FIG. FIG. 6B is an enlarged view of the vicinity of the step portion of the conventional split gate nonvolatile semiconductor memory device, and is a cross-sectional view showing the simulation result of the current density during the write operation by the computer.

4A to 4D are cross-sectional views in order of the steps, showing the method for manufacturing the split gate nonvolatile semiconductor memory device according to the first embodiment of the present invention.

5A to 5D are cross-sectional views in order of the steps, showing a method for manufacturing the split gate nonvolatile semiconductor memory device according to the first embodiment of the present invention.

6A and 6B are cross-sectional views in order of the steps, showing the method for manufacturing the split gate nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a configuration cross-sectional view showing one memory element of a split gate type nonvolatile semiconductor memory device according to a second embodiment of the present invention.

8A to 8D are cross-sectional views in order of the processes, showing a method for manufacturing a split gate nonvolatile semiconductor memory device according to a second embodiment of the present invention.

9A to 9D are cross-sectional views in order of the steps, showing a method for manufacturing a split gate type nonvolatile semiconductor memory device according to a second embodiment of the present invention.

10A and 10B are cross-sectional views in order of the processes, showing a method for manufacturing a split gate nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a configuration cross-sectional view showing one memory element of a stack gate type nonvolatile semiconductor memory device according to a third embodiment of the present invention.

12A to 12D are cross-sectional views in order of the steps, showing a method for manufacturing the stack gate type nonvolatile semiconductor memory device according to the third embodiment of the present invention.

13A to 13D are cross-sectional views in order of the steps, showing the method for manufacturing the stack gate nonvolatile semiconductor memory device according to the third embodiment of the present invention.

FIG. 14 is a cross-sectional view in order of the steps, showing a method of manufacturing a stack gate type nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 15 is a configuration cross-sectional view showing one memory element of a stack gate type nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

16A to 16D are cross-sectional views in order of the processes, showing the method for manufacturing the stack gate nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

17A to 17D are cross-sectional views in order of the steps, showing the method for manufacturing the stack gate type nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 18 is a cross-sectional view in order of the steps, showing a method for manufacturing the stack gate nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 19A is a configuration cross-sectional view showing one memory element of a split gate type nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. FIG. 9B is a configuration cross-sectional view showing one memory element of the stack gate type nonvolatile semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 20 is a configuration cross-sectional view showing one memory element of a split gate type nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

21A and 21B are enlarged views in the vicinity of a step in a split gate nonvolatile semiconductor memory device according to a sixth embodiment of the present invention, and FIG. 3B is a cross-sectional view showing the flow of electrons, and FIG. 3B is a cross-sectional view showing the flow of electrons during the erase operation.

22A to 22D are cross-sectional views in order of the steps, showing a method for manufacturing a split gate nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

23A to 23D are cross-sectional views in order of the steps, showing a method for manufacturing a split gate nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

24A and 24B are cross-sectional views in order of the steps, showing the method for manufacturing the split gate nonvolatile semiconductor memory device according to the sixth embodiment of the present invention.

FIG. 25 is a configuration cross-sectional view showing one memory element of a split gate type nonvolatile semiconductor memory device according to a modification of the sixth embodiment of the present invention.

FIG. 26 is a configuration cross-sectional view showing one memory element of a split gate nonvolatile semiconductor memory device according to the seventh embodiment of the present invention.

27A to 27D are cross-sectional views in order of the steps, showing a method for manufacturing a split gate nonvolatile semiconductor memory device according to a seventh embodiment of the present invention.

28A to 28D are cross-sectional views in order of the steps, showing a method for manufacturing a split gate nonvolatile semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 29 is a cross-sectional view in order of the steps, showing a method of manufacturing a split gate nonvolatile semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 30 is a configuration cross-sectional view showing one memory element of a split gate type nonvolatile semiconductor memory device according to a modification of the seventh embodiment of the present invention.

FIG. 31 is a configuration cross-sectional view showing one storage element of a stack gate type nonvolatile semiconductor memory device according to an eighth embodiment of the present invention.

32A to 32D are cross-sectional views in order of the processes, showing the method for manufacturing the stack gate type nonvolatile semiconductor memory device according to the eighth embodiment of the present invention.

33A to 33D are cross-sectional views in order of the steps, showing the method for manufacturing the stack gate type nonvolatile semiconductor memory device according to the eighth embodiment of the present invention.

34A and 34B are cross-sectional views in order of the steps, showing the method for manufacturing the stack gate nonvolatile semiconductor memory device according to the eighth embodiment of the present invention.

FIG. 35 is a configuration cross-sectional view showing one memory element of a stack gate type nonvolatile semiconductor memory device according to a modification of the eighth embodiment of the present invention.

FIG. 36 is a configuration cross-sectional view showing one memory element of a stack gate type nonvolatile semiconductor memory device according to the ninth embodiment of the present invention.

37A to 37D are cross-sectional views in order of the processes, showing the method for manufacturing the stack gate nonvolatile semiconductor memory device according to the ninth embodiment of the present invention.

38A to 38D are cross-sectional views in order of the processes, showing the method for manufacturing the stack gate nonvolatile semiconductor memory device according to the ninth embodiment of the present invention.

FIG. 39 is a cross-sectional view in order of the steps, showing a method of manufacturing a stack gate type nonvolatile semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 40 is a configuration cross-sectional view showing a memory element of a stack gate type nonvolatile semiconductor memory device according to a modification of the ninth embodiment of the present invention.

41 (a) and 41 (b) show flows of hot holes in the vicinity of a step portion during an erase operation in a split gate type nonvolatile semiconductor memory device, and FIG. 41 (a) shows a bias application method for comparison. FIG. 13B is a cross-sectional view of the case, and FIG. 13B is a cross-sectional view when the bias applying method according to the tenth embodiment of the present invention is used.

FIG. 42 is a configuration cross-sectional view showing one memory element of a conventional split gate nonvolatile semiconductor memory device.

[Explanation of symbols]

1 Electron temperature High temperature range 2 Maximum electron temperature range 10 Active area 11 Semiconductor substrate 12 element isolation layer 13 First surface area 14 Second surface area 15 Step side area 16 step 21 Control gate electrode 21A Control gate electrode 22 First insulating film 23 Floating gate electrode 23A floating gate electrode 24 Second insulating film 25 Third insulating film 31 Source Area 31a Medium density layer 31b High concentration layer 32 drain region 32a low concentration layer 32b Medium density layer 32c high concentration layer 33 Depletion control layer 34 High electric field forming layer 35 High-concentration impurity region 36 Short channel effect suppression region 51 Semiconductor substrate 51a recess 51b Step portion 52 element isolation layer 53 Protective oxide film 54 Gate oxide film (first insulating film) 55 Control gate electrode 55A Second polysilicon film 55B Control gate electrode 56 high-concentration impurity layer (first high-concentration impurity layer) 56a Depletion control layer 57 Sidewall 58 Low concentration drain region 59 First surface area 60 Second surface area 61 Step Side Area 62 Thermal oxide film (second insulating film and third insulating film) 63 Floating gate electrode 63A First polysilicon film 63B floating gate electrode 64 insulating film 65 High concentration source area 66 High-concentration drain region 67A Silicon oxide film 67B Capacitance insulating film (second insulating film) 68 Medium concentration source area 69 Medium concentration drain region 70 Short channel effect suppression layer 71 Second high-concentration impurity layer 71a High electric field forming layer 72 Insulating film sidewall 91 First resist pattern 92 Second resist pattern 93 Third resist pattern 94 Fourth resist pattern 95 Fifth resist pattern 96 sixth resist pattern

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Masaaki Ogura 12590, New York, United States, Wappingers Falls, Old Hopewell Road 140, Halo LSI Design and Device Technology Incorporated (72) Inventor Shinji Odanaka Osaka 1-11 Machikaneyamacho, Toyonaka City, Fuchu, Osaka University Graduate School of Science Mathematics Class 5F Cyber Media Center (72) Inventor ▲ Sugi ▼ Nobuyo Yama, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-11-260944 (JP, A) JP-A-9-321155 (JP, A) JP-A-11-260942 (JP, A) JP-A-8-78541 (JP, A) Kaihei 9-22598 (JP, A) JP-A-7-115142 (J (P, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/788

Claims (25)

(57) [Claims] 1. A first upper layer formed on a semiconductor substrate
A step portion having a surface area, a second surface area which is a lower step, and a step side surface area which connects the upper step and the lower step; a first insulating film formed on the first surface area; and a step on the first surface area. A control gate electrode formed near the step portion via the first insulating film, and formed on the semiconductor substrate so as to straddle the step portion,
A floating gate electrode that is capacitively coupled to a side surface of the control gate electrode on the stepped portion side via a second insulating film, and faces the second surface region via a third insulating film; and the control in the first surface region. A source region formed in a region opposite to the floating gate electrode with respect to a gate electrode, a drain region formed in a region below the floating gate electrode in the second surface region, and the semiconductor substrate, It extends from a position spaced apart from the upper corner of the step below the first surface region toward the lower corner of the step and is adjacent to the drain region without reaching the step side surface region. And a depletion control layer formed of a high-concentration impurity region of a conductivity type opposite to the drain region. 2. A high electric field forming layer formed between an upper corner of the step and the depletion limiting layer and formed of an impurity region having the same conductivity type as the depletion limiting layer. The non-volatile semiconductor memory device according to claim 1. 3. The non-volatile semiconductor according to claim 2, wherein an impurity concentration of the high electric field forming layer is lower than an impurity concentration of the depletion control layer and higher than an impurity concentration of the semiconductor substrate. Storage device. 4. A first upper layer formed on a semiconductor substrate
A step portion including a surface area, a second surface area as a lower step, and a step side surface area connecting the upper step and the lower step; a first insulating film formed on the semiconductor substrate so as to straddle the step section; A floating gate electrode formed on the insulating film so as to straddle the step portion, and formed on the floating gate electrode via a second insulating film,
A control gate electrode capacitively coupled to the floating gate electrode; a source region formed in a region of the first surface region opposite to the step portion with respect to the floating gate electrode; and a floating region in the second surface region. A drain region formed in a region below the gate electrode; and a semiconductor substrate on a lower side of the step portion from a position spaced apart from an upper corner of the step portion below the first surface region. A depletion control layer formed of a high-concentration impurity region of a conductivity type opposite to the drain region, the depletion control layer extending toward the corner portion and adjoining the drain region without reaching the step side surface region. A non-volatile semiconductor memory device characterized by the above. 5. A high electric field forming layer formed between an upper corner of the step and the depletion limiting layer, the high electric field forming layer including an impurity region of the same conductivity type as the depletion limiting layer. The non-volatile semiconductor memory device according to claim 4. 6. The non-volatile semiconductor according to claim 5, wherein an impurity concentration of the high electric field forming layer is lower than an impurity concentration of the depletion control layer and higher than an impurity concentration of the semiconductor substrate. Storage device. 7. The source region side end of the drain region is located in the step side surface region without reaching the first surface region.
7. The nonvolatile semiconductor memory device according to any one of items 1 to 6. 8. The drain region has at least three impurity regions formed in a plane direction of the second surface region and in such a manner that an impurity concentration is sequentially increased from the source region side. The non-volatile semiconductor memory device according to claim 1, wherein 9. The semiconductor device further comprises an impurity region formed in the first surface region so as to cover the junction surface of the source region and having a conductivity type opposite to that of the source region and suppressing a short channel effect. The nonvolatile semiconductor memory device according to claim 1, wherein 10. A step portion formed on a semiconductor substrate, the step portion including an upper first surface area, a lower second surface area, and a step side surface area connecting the upper step and the lower step, and formed on the first surface area. A first insulating film, a control gate electrode formed on the first surface region in the vicinity of the step portion via the first insulating film, and formed on the semiconductor substrate so as to straddle the step portion. Is
A floating gate electrode that is capacitively coupled to a side surface of the control gate electrode on the stepped portion side via a second insulating film, and faces the second surface region via a third insulating film; and the control in the first surface region. A source region formed in a region opposite to the floating gate electrode with respect to a gate electrode; a drain region formed in a region below the floating gate electrode in the second surface region; An impurity region formed near a corner between the first surface region and the step side surface region and having a conductivity type higher than that of the semiconductor substrate and opposite to that of the drain region; And at least three impurity diffusion regions formed so that the impurity concentration is higher in the surface direction of the second surface region and from the source region side. Nonvolatile semiconductor memory device. 11. A step portion formed on a semiconductor substrate, comprising a first surface region as an upper step, a second surface area as a lower step, and a step side surface area connecting the upper step and the lower step, and a step portion formed on the first surface area. A first insulating film, a control gate electrode formed on the first surface region in the vicinity of the step portion via the first insulating film, and formed on the semiconductor substrate so as to straddle the step portion. Is
A floating gate electrode that is capacitively coupled to a side surface of the control gate electrode on the stepped portion side via a second insulating film, and faces the second surface region via a third insulating film; and the control in the first surface region. A source region formed in a region opposite to the floating gate electrode with respect to a gate electrode; a drain region formed in a region below the floating gate electrode in the second surface region; A first impurity region formed near a corner between the first surface region and the step side surface region, the first impurity region having a conductivity type higher than that of the semiconductor substrate and opposite to that of the drain region; A second impurity region formed in the surface region so as to cover the junction surface of the source region and having a conductivity type opposite to that of the source region and suppressing a short channel effect. And a non-volatile semiconductor memory device. 12. A step portion formed on a semiconductor substrate, the step portion including an upper first surface region, a lower second surface region, and a step side surface region connecting the upper and lower steps, and the step portion on the semiconductor substrate. A first insulating film formed to extend over the floating gate electrode, a floating gate electrode formed on the first insulating film so as to extend over the step, and a second insulating film formed on the floating gate electrode. ,
A control gate electrode capacitively coupled to the floating gate electrode; a source region formed in a region of the first surface region opposite to the step portion with respect to the floating gate electrode; and a floating region in the second surface region. The drain region is formed in a region below the gate electrode, and is formed in the vicinity of a corner between the first surface region and the step side surface region in the semiconductor substrate, and has a higher impurity concentration than the semiconductor substrate. An impurity region having a conductivity type opposite to that of the drain region, the drain region having at least three impurity concentrations formed in a plane direction of the second surface region and sequentially increasing in impurity concentration from the source region side. A nonvolatile semiconductor memory device having an impurity diffusion region. 13. A step portion formed on a semiconductor substrate, the step portion including an upper first surface region, a lower second surface region, and a step side surface region connecting the upper and lower steps, and the step portion on the semiconductor substrate. A first insulating film formed to extend over the floating gate electrode, a floating gate electrode formed on the first insulating film so as to extend over the step, and a second insulating film formed on the floating gate electrode. ,
A control gate electrode capacitively coupled to the floating gate electrode; a source region formed in a region of the first surface region opposite to the step portion with respect to the floating gate electrode; and a floating region in the second surface region. The drain region is formed in a region below the gate electrode, and is formed in the vicinity of a corner between the first surface region and the step side surface region in the semiconductor substrate, and has a higher impurity concentration than the semiconductor substrate. A first impurity region having a conductivity type opposite to that of the drain region; and a short channel effect having a conductivity type opposite to that of the source region and formed on the first surface region so as to cover the junction surface of the source region. A non-volatile semiconductor memory device comprising: a second impurity region for suppressing. 14. A channel region is formed by applying a substrate voltage to the semiconductor substrate so that carriers flow from a lower portion of the floating gate electrode in the first surface region toward the step side surface region. 14. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device comprises: 15. A step is applied from a lower portion of the floating gate electrode in the first surface region by applying a predetermined drain voltage and a predetermined control gate voltage to the drain region and the control gate electrode. 14. The nonvolatile semiconductor memory device according to claim 1, wherein a channel region in which carriers flow toward the side surface region is formed. 16. A step portion formed on a semiconductor substrate, the step portion including an upper first surface area, a lower second surface area, and a step side surface area connecting the upper step and the lower step, and formed on the first surface area. A first insulating film, a control gate electrode formed on the first surface region in the vicinity of the step portion via the first insulating film, and formed on the semiconductor substrate so as to straddle the step portion. Is
A floating gate electrode that is capacitively coupled to a side surface of the control gate electrode on the stepped portion side via a second insulating film, and faces the second surface region via a third insulating film; and the control in the first surface region. A source region formed in a region opposite to the floating gate electrode with respect to a gate electrode; a drain region formed in a region below the floating gate electrode in the second surface region; A nonvolatile semiconductor memory device comprising: a first surface region and an impurity region having a conductivity type opposite to that of the drain region, the impurity region being formed in the step side surface region and having a higher impurity concentration than the semiconductor substrate; By applying a substrate voltage to the first surface region, a carry is carried out from the lower portion of the floating gate electrode in the first surface region toward the step side surface region. A non-volatile semiconductor memory device characterized in that a channel region through which an electric current flows is formed. 17. A step portion formed on a semiconductor substrate, the step portion including an upper first surface region, a lower second surface region, and a step side surface region connecting the upper and lower steps, and the step portion on the semiconductor substrate. A first insulating film formed to extend over the floating gate electrode, a floating gate electrode formed on the first insulating film so as to extend over the step, and a second insulating film formed on the floating gate electrode. ,
A control gate electrode capacitively coupled to the floating gate electrode; a source region formed in a region of the first surface region opposite to the step portion with respect to the floating gate electrode; and a floating region in the second surface region. A drain region formed in a region below the gate electrode, a first surface region of the semiconductor substrate and the step side surface region, and a conductivity higher than an impurity concentration of the semiconductor substrate and opposite to the drain region. A non-volatile semiconductor memory device including an impurity region having a mold, a substrate voltage is applied to the semiconductor substrate to move from a lower portion of the floating gate electrode in the first surface region to the step side surface region. A non-volatile semiconductor memory device, wherein a channel region in which carriers flow toward is formed. 18. A first step of forming a control gate electrode on a semiconductor substrate via a first insulating film; masking a source formation region of the semiconductor substrate;
By implanting a high-concentration impurity of the first conductivity type into the semiconductor substrate using the control gate electrode as a mask,
A second step of forming a high-concentration impurity region, forming a sidewall made of an insulating film on a side surface of the gate electrode, using the formed sidewall, the control gate electrode as a mask, and the source formation region as a mask. By etching the semiconductor substrate,
A recess is formed in the semiconductor substrate, and a first surface region in which the lower side of the sidewall is an upper stage, a second surface region in which the bottom surface of the recess is a lower stage, and a step side surface connecting the upper stage and the lower stage are formed on the semiconductor substrate. A third step of forming a step portion formed of a region, and a step of selectively ion-implanting a second conductivity type low-concentration impurity into the second surface region of the semiconductor substrate to perform the second step.
A second-conductivity-type low-concentration drain region is formed in the surface region, and a conductivity type near the first surface region in the high-concentration impurity region, an upper corner of the step portion, and the step-side surface region is formed. A fourth step of forming a depletion control layer which is formed of the high-concentration impurity region and is localized by being inverted from the first surface region and the step side surface region and is adjacent to the low-concentration drain region. And a fifth step of forming a second insulating film on the side surface of the control gate electrode on the side of the step portion, the first surface region, the step side surface region, and the second surface region after removing the sidewall. By depositing a conductor film over the entire surface of the second insulating film and etching the deposited conductor film,
While straddling the step portion, the side surface of the control gate electrode on the step portion side is capacitively coupled via a second insulating film and the second
A sixth step of forming a floating gate electrode facing the surface region via a second insulating film in a self-aligned manner; and using the control gate electrode and the floating gate electrode as a mask, a second conductivity type with respect to the semiconductor substrate. Forming a second-conductivity-type source region in the first surface region and forming a second-conductivity-type drain region in the second surface region by ion-implanting the second impurity region. A method of manufacturing a nonvolatile semiconductor memory device, comprising: 19. In the second step, after the high-concentration impurity region is formed, an impurity of a first conductivity type is ion-implanted into the high-concentration impurity region again to remove the impurity from the high-concentration impurity region. Also includes a step of forming another impurity region of the first conductivity type having a shallow diffusion depth, and the fourth step includes the step of forming the impurity region between the upper corner of the step and the depletion control layer. 2. A step of forming a high electric field forming layer made of another impurity region is included.
8. The method for manufacturing a nonvolatile semiconductor memory device according to item 8. 20. After the seventh step, a third insulating film is deposited on the floating gate electrode, and the deposited third insulating film and the floating gate electrode are used as a mask,
An eighth step of forming a second-conductivity-type high-concentration drain region having an impurity concentration higher than that of the drain region in the second surface region by ion-implanting a second-conductivity-type impurity into the semiconductor substrate. 20. The method for manufacturing a nonvolatile semiconductor memory device according to claim 18, further comprising: 21. After the fourth step, a region from the control gate electrode to the second surface region is masked, and a diffusion depth in the source formation region is deeper than that in the source region. The method according to claim 18, further comprising the step of forming the impurity region of.
The method for manufacturing a nonvolatile semiconductor memory device according to any one of 0. 22. A first step of forming a high-concentration impurity region of the first conductivity type by selectively ion-implanting a high-concentration impurity of the first conductivity type into a drain formation region of a semiconductor substrate, By selectively etching a region of the high-concentration impurity region other than the end portion on the source formation region side, a recess is formed in the semiconductor substrate and the high-concentration impurity region of the semiconductor substrate is formed. A second step of forming a step portion including a first surface area having an upper end at an end, a second surface area having a bottom surface of the recess as a lower step, and a step side surface area connecting the upper step and the lower step; The second conductivity type low-concentration impurity is selectively ion-implanted into the second surface region to remove the second impurity.
A second-conductivity-type low-concentration drain region is formed in the surface region, and a conductivity type near the first surface region in the high-concentration impurity region, an upper corner of the step portion, and the step-side surface region is formed. By inversion, a third step of forming a depletion control layer composed of the high-concentration impurity region, localized at a distance from the first surface region and the step side surface region, and adjacent to the low-concentration drain region. And a fourth step of sequentially forming a first insulating film, a floating gate electrode, a second insulating film and a control gate electrode on the semiconductor substrate so as to straddle the step portion, and using the control gate electrode as a mask, By implanting a second conductivity type impurity into the semiconductor substrate, a second conductivity type source region is formed in the source formation region and a second conductivity type is formed in the drain formation region. Method of manufacturing a nonvolatile semiconductor memory device characterized by and a fifth step of forming a drain region. 23. In the first step, after the high-concentration impurity region is formed, an impurity of a first conductivity type is ion-implanted again into the high-concentration impurity region to remove the high-concentration impurity region from the high-concentration impurity region. Also includes a step of forming another impurity region of the first conductivity type having a shallow diffusion depth, and the third step includes the step of forming the impurity region between the upper corner of the step and the depletion control layer. 3. The method according to claim 2, further comprising the step of forming a high electric field forming layer made of another impurity region.
2. The method for manufacturing a nonvolatile semiconductor memory device according to 2. 24. After the fifth step, a third insulating film is deposited on the control gate electrode, the deposited third insulating film insulating film is etched, and the floating gate electrode and the control gate electrode are formed. A sixth step of forming a side wall on the side surface of the semiconductor substrate, and ion-implanting a second conductivity type impurity into the semiconductor substrate using the control gate electrode and the side wall as a mask to form a second surface region on the second surface region. 24. The non-volatile semiconductor memory device according to claim 22, further comprising a seventh step of forming a second-conductivity-type high-concentration drain region having a higher impurity concentration than the drain region. Production method. 25. After the third step, a region from the control gate electrode to the second surface region is masked, and a diffusion depth in the source formation region is deeper than that in the source region. 22. The method according to claim 22, further comprising the step of forming the impurity region of FIG.
5. The method for manufacturing a nonvolatile semiconductor memory device according to any one of items 4 to 4.