CN101593682A - The manufacture method of ion injection method and semiconductor device - Google Patents
The manufacture method of ion injection method and semiconductor device Download PDFInfo
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- CN101593682A CN101593682A CNA200810112805XA CN200810112805A CN101593682A CN 101593682 A CN101593682 A CN 101593682A CN A200810112805X A CNA200810112805X A CN A200810112805XA CN 200810112805 A CN200810112805 A CN 200810112805A CN 101593682 A CN101593682 A CN 101593682A
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Abstract
A kind of ion injection method comprises: Semiconductor substrate is provided; On described Semiconductor substrate, form photoresist layer; Graphical described photoresist layer, formation has opening angled side walls, that be used to define Semiconductor substrate intermediate ion injection zone; Semiconductor substrate to described open bottom is carried out ion implantation technology; Wherein, described sidewall and describedly treat that the angle on injection zone surface is the obtuse angle.The present invention also provides a kind of manufacture method of semiconductor device.The present invention can reduce or eliminate that the scattering of ion implantation technology ion photoresist layer causes is injected into ion in the Semiconductor substrate.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the manufacture method of particularly a kind of ion injection method and semiconductor device.
Background technology
Metal oxide semiconductor device is widely used in fields such as computer, communication, storage owing to its low-power consumption, fast response characteristic.Typical metal oxide semiconductor device comprises grid, source electrode and drain electrode.For improving the performance of metal oxide semiconductor device electricity aspect, the metal oxide semiconductor transistor that has also has drain electrode elongated area (Drain extend region).
Source electrode, drain electrode and above-mentioned drain electrode elongated area generally form by ion implantation technology, thereby, the electrology characteristic of the source electrode that the process conditions decision of ion injection forms, drain electrode and drain electrode elongated area, and then the electric property of the metal oxide semiconductor device of decision formation.Can adjust the performance of the metal oxide semiconductor device of formation by the process conditions of adjusting the ion injection.For example, in the patent No. is US 6,767, in the United States Patent (USP) of 778B2, the source electrode in a kind of metal oxide semiconductor device and the formation method of drain electrode are disclosed, form source electrode and drain electrode by two step ion implantation technologies, the energy of the second step ion implantation technology is big than the first step, and dosage is less, reduces the ion concentration gradient of source-drain electrode and Semiconductor substrate intersection with this, thereby reduce the junction capacitance of source electrode and drain electrode, improve the performance of the semiconductor device that forms.
Existing ion implantation technology generally need form litho pattern by photoetching process on semiconductor device, go out to treat injection zone with definition (or qualification), carries out ion implantation technology then in ion implantation device, injects object ion in treating injection zone.Fig. 1 to Fig. 3 is the profile of each step corresponding structure of existing a kind of ion implantation technology.
Please refer to Fig. 1, on Semiconductor substrate 10, form photoresist layer 12.
Please refer to Fig. 2, form opening 14 by photoetching process in described photoresist layer 12, described opening 14 bottoms are for treating injection zone, and this zone can be used to form source electrode, drain electrode or well region etc.
Please refer to Fig. 3, described Semiconductor substrate 10 is placed ion implantation device, carry out ion implantation technology, in the Semiconductor substrate 10 of described open bottom, inject object ion, form doped region.And described Semiconductor substrate 10 other zones can not be injected into ion owing to covered by photoresist layer.
In the described ion implantation technology, define earlier and treat injection zone, and then carry out ion and inject by photoresist layer 12, the ion of injection with the fixing angle (for example 90 degree) in the surface of Semiconductor substrate 10 in implanted.Yet, in described ion implantation technology, scattering can take place and change angle in the part ion that bombards in the described opening 14 zone photoresist layers 12 in addition, and pass described photoresist layer 12 along the sidewall of described opening 14, and then be implanted in the described Semiconductor substrate 10, this not only makes the ion dose of the injection in the Semiconductor substrate 10 that variation has taken place, and because the uncertainty of scattering angle, make the ion that is injected in the Semiconductor substrate 10 no longer be limited to the zone of opening 14 bottoms, and then influence the characteristic of the metal oxide semiconductor device that forms.
For example, to metal oxide semiconductor device, when carrying out source electrode and drain electrode and inject, have part ion and enter into photoresist layer 20, and produce scattering with molecular action in the photoresist layer 20, the ion that is scattered can pass after the described photoresist layer 20, enter into the Semiconductor substrate 10 of described grid below 22, make the zone of source electrode and drain electrode enlarge, the conducting channel zone diminishes, the threshold voltage and the saturation current of the semiconductor device that influence forms are shown in the schematic diagram of Fig. 4.
Summary of the invention
The invention provides the manufacture method of a kind of ion injection method and semiconductor device, to improve in the existing ion implantation technology scattering of photoresist layer intermediate ion to influence to ion implantation technology.
A kind of ion injection method provided by the invention comprises: Semiconductor substrate is provided; On described Semiconductor substrate, form photoresist layer; Graphical described photoresist layer is formed for defining the opening of Semiconductor substrate intermediate ion injection zone, and the sidewall of described opening tilts; Semiconductor substrate to described open bottom is carried out ion implantation technology; Wherein, described sidewall and describedly treat that the angle on injection zone surface is the obtuse angle.
Optionally, graphical described photoresist layer, the step that forms described opening is as follows:
The Semiconductor substrate that will have described photoresist layer places exposure sources; Select the focal length that departs from the optimum exposure focal length for use, described photoresist layer is exposed by mask plate with patterns of openings; The photoresist layer of finishing exposure is carried out developing process; After executing described developing process, described photoresist layer is carried out baking process.
Optionally,, make described photoresist layer surface carry out exposure technology, make the described opening of formation have angled side walls towards the imaging len deviation in driction focussing plane of exposure sources by adjusting the exposure focal length.
Optionally, by adjusting the temperature of baking process, the temperature of the baking of the temperature that makes described baking process when forming vertical sidewall is carried out baking process, makes the described opening of formation have angled side walls.
Optionally, make the imaging len deviation in driction focussing plane of described photoresist layer surface by adjusting exposure equipment focal distance towards exposure sources, the method that the temperature of the baking of the temperature that makes described baking process with the temperature of adjusting baking process when forming vertical sidewall combines makes described opening have angled side walls.
Optionally, before described formation photoresist layer, on described Semiconductor substrate, form anti-reflecting layer earlier.
Optionally, before described formation photoresist layer, on described Semiconductor substrate, form resilient coating earlier.
Optionally, described angle greater than 90 ℃ less than 120 ℃.
Optionally, described ion implantation technology is source electrode and drain ion injection technology, trap ion implantation technology, lightly doped drain ion implantation technology, adjusts the ion implantation technology of threshold voltage or improve the ion implantation technology of breakdown characteristics.
The present invention also provides a kind of manufacture method of semiconductor device, comprises ion implantation technology, and at least one ion implantation technology is the described ion injection method of above-mentioned arbitrary technical scheme.
Compared with prior art, one of them of technique scheme has the following advantages:
Before carrying out ion implantation technology, has opening sloped sidewall, that be used to define injection zone by photoetching process formation, when carrying out ion implantation technology, can increase the ion scattering probability that enters into described photoresist layer, ion towards described opening sidewalls scattering can be taken place twice or repeatedly scattering, this can reduce to be scattered ion energy on the one hand, its speed of moving in photoresist layer is descended, to such an extent as to some ion can not pass this photoresist layer; Can change the ion scattering angle on the other hand, it can not passed by described opening sidewalls; Thereby can reduce or eliminate in the ion implantation technology and to pass by described opening sidewalls and be injected into ion in the Semiconductor substrate of open bottom, make the dosage of the ion that injects in the Semiconductor substrate and the regional controllability of injection improve, and then the electric property of the feasible semiconductor device that forms improves the electrical stability increase;
In addition, also make this ion implantation technology repeatability improve, the yield of the semiconductor device of formation promotes.
Description of drawings
Fig. 1 to Fig. 3 is the profile of each step corresponding structure of existing a kind of ion implantation technology;
Fig. 4 passes the schematic diagram that photoresist layer enters into the following Semiconductor substrate of grid afterwards for the ion that is scattered in the existing ion implantation technology;
Fig. 5 is the flow chart of the embodiment of ion implantation technology of the present invention;
Fig. 6 to Fig. 9 is the generalized section of each step corresponding structure of the embodiment of application ion implantation technology formation source electrode of the present invention and drain electrode.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
In the manufacture method of metal oxide semiconductor device, need the multistep ion implantation technology, for example well region (N trap or P trap) formation, source-drain electrode formation, lightly doped region formation etc. all need to realize by ion implantation technology.Ion implantation technology has critical role in the manufacturing process of metal oxide semiconductor device.
The process conditions of ion implantation technology have bigger influence to the electric property of the metal oxide semiconductor device of formation, how to pass through control, adjust and change the ion implantation technology condition, make the ion that injects after the ion implantation technology can reach target dose, and be positioned at the target area, so that the electrology characteristic in the ion implanted region territory that forms satisfies the needs of the metal oxide semiconductor device that forms, be the problem that those skilled in the art have to face.
The invention provides a kind of ion injection method, by on Semiconductor substrate, forming photoresist layer, then described photoresist is carried out graphically, formation has opening sloped sidewall, that be used to define Semiconductor substrate intermediate ion injection zone, carries out corresponding ion implantation technology again; Wherein, described sidewall and describedly treat that the angle on injection zone surface is the obtuse angle.
Because described opening has angled side walls, when carrying out ion implantation technology, can increase the ion scattering probability that enters into described photoresist layer, ion towards described opening sidewalls scattering can be taken place twice or repeatedly scattering, this can reduce to be scattered ion energy on the one hand, some ion its speed of moving in photoresist layer descended, to such an extent as to can not pass this photoresist layer; Can change the ion scattering angle on the other hand, it can not passed by described opening sidewalls.That is to say, core of the present invention is when carrying out ion implantation technology, the opening that is used to define the ion implanted region territory has sloped sidewall, thereby can reduce or eliminate in the ion implantation technology and to pass by described opening sidewalls and be injected into ion in the Semiconductor substrate of open bottom, make the dosage of the ion that injects in the Semiconductor substrate and the regional controllability of injection improve, and then the electric property of the feasible semiconductor device that forms improves the electrical stability increase.
Below in conjunction with flow chart and profile ion injection method of the present invention is described in detail.
Fig. 5 is the flow chart of the embodiment of ion injection method of the present invention.
Please refer to Fig. 5, step S100 provides Semiconductor substrate.Step S110 forms photoresist layer on described Semiconductor substrate.Step S120, graphical described photoresist layer, formation has opening angled side walls, that be used to define Semiconductor substrate intermediate ion injection zone; Wherein, described sidewall and describedly treat that the angle on injection zone surface is the obtuse angle.Step S130 carries out ion implantation technology to the Semiconductor substrate of described open bottom.
Be that example illustrates ion injection method of the present invention with the source electrode of NMOS and the ion implantation technology of drain electrode below.Should be noted that, ion injection method of the present invention is not limited to nmos source described below and drain ion injection technology, can also be applied to the ion implantation technology of pmos source and drain electrode, or in other the ion implantation technology that needs photoresist pattern definition injection zone in the manufacturing process of metal oxide semiconductor device, for example, trap ion implantation technology, lightly doped drain ion implantation technology, adjust the ion implantation technology of threshold voltage or improve the ion implantation technology etc. of breakdown characteristics; Those skilled in the art can instruction according to the present invention be applied to the step of other ion injection, and make corresponding change, and these all should be included among protection scope of the present invention.
Please refer to Fig. 6, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon or amorphous silicon; Described Semiconductor substrate 100 also can be silicon, germanium, GaAs or silicon Germanium compound; This Semiconductor substrate 100 can also have epitaxial loayer or insulating barrier silicon-on.Described Semiconductor substrate 100 can also be other semi-conducting material, enumerates no longer one by one here.
In described Semiconductor substrate 100, has P trap 102, described P trap 102 can form with those skilled in the art's method known, for example, on Semiconductor substrate 100, define the zone that forms P trap 102 by photoetching process earlier, carrying out ion then injects, form P trap 102, the ion of injection is P type ion, for example boron;
Optionally, can also in described P trap 102, improve the ion implantation technology of breakdown characteristics; The ion that the ion of its injection injects when forming described P trap 102 is identical, but energy that injects and dosage are all less than the energy and the dosage of the ion implantation technology that forms described P trap 102.
Optionally, can also in described P trap 102, adjust the ion implantation technology of threshold voltage.The ion implantation technology of this adjustment threshold voltage is used to adjust the threshold voltage of the nmos pass transistor of formation, and the ion of its injection is identical with the ion that preceding twice ion implantation technology injected; Or the ionic type identical (being all the P type) of the ion that injects and preceding twice ion implantation technology injection, and can be ion of the same race, for example boron; The ion that injects in the ion implantation technology of this adjustment threshold voltage also can be the bigger ion of quality, for example indium.
After finishing above-mentioned ion implantation technology, remove the photoresist layer (figure does not show) that on described Semiconductor substrate 100, forms in the photoetching process by ashing and wet-cleaned.
In addition, the formation technology of described P trap 102 also can adopt ion implantation technology of the present invention, promptly forms photoresist layer on described Semiconductor substrate 100, and graphical formation has opening sloped sidewall, definition P well area 102; And then execution P trap ion implantation technology.Wherein, the method that forms beveled realizes that by adjusting the focal length that exposes in the photoetching process and hard roasting (hard bake) technology behind the developing process concrete description is referring to the follow-up source electrode and the ion implantation technology of drain electrode, and its principle is identical.
In described Semiconductor substrate 100, also have fleet plough groove isolation structure 104, can adopt the described fleet plough groove isolation structure 104 of those skilled in the art's technology known, repeat no more here.
On described Semiconductor substrate 100, has gate dielectric layer 106a, described gate dielectric layer 106a can be silica or silicon oxynitride, its formation method can adopt those skilled in the art's oxidation technology known, for example high temperature furnace pipe oxidation, rapid thermal oxidation or original position steam produce (In-Situ Stream Generation, ISSG) oxidation technology; Can form silicon oxynitride by described silica is carried out nitrogen treatment, described nitrogenation treatment technology can be a kind of in boiler tube nitrogenize, Rapid Thermal Nitrided, the pecvd nitride (for example DPN).Here no longer launch.
On described gate dielectric layer 106a, have polysilicon gate 108a, be the resistivity of the grid of the metal oxide semiconductor device that reduce to form, can mix to described polysilicon gate 108a by ion injection or diffusion or original position ion implantation technology.In addition, the grid on the described gate dielectric layer 106a can be not limited to polycrystalline silicon material, also can be other material, for example metal material or metal silicide materials etc.
Have lightly doped region 110 in the Semiconductor substrate 100 of described grid 108a both sides, described lightly doped region 110 can (Light Doped Drain, LDD) injection technology forms by known lightly doped drain.Also can form by ion implantation technology of the present invention, also promptly before carrying out the light dope injection, form by photoetching process earlier and have opening sloped sidewall, that be used to define lightly doped region 110, here no longer launch to describe, wherein, the method that formation has a sloped sidewall opening please refer to the manufacture method of the opening in the ion injection method of follow-up source electrode and drain electrode, and its principle is identical.
Has side wall layer 116 at described gate lateral wall, this side wall layer 116 can be silicon nitride, silica, silica-silicon nitride (O-N) lamination or silica-silicon-nitride and silicon oxide (ONO) lamination, can adopt those skilled in the art's technology known to form described side wall layer 116, no longer launch here.
Then, please refer to Fig. 7, on Semiconductor substrate shown in Figure 6 100, form photoresist layer 200.Described photoresist layer 200 can be chemically-amplified resist or other photoresist, can adopt those skilled in the art's spin coating method known in spin-coating equipment, to form photoresist layer 200, and after spin coating, remove solvent in the photoresist layer 200 by baking process, increase the adhesion property of described photoresist layer 200 on described Semiconductor substrate 200 surfaces.
Then, please refer to Fig. 8, form opening 204 by exposure and developing process, wherein said opening 204 (in the present embodiment in conjunction with described grid 108a and side wall layer 116) is used to define the zone of formation source electrode and drain electrode.Wherein, described opening 204 has angled side walls 205, and described sidewall 205 is the obtuse angle with the described angle 206 of ion implanted region field surface 101 (being the surface of source electrode to be formed and drain region) for the treatment of.For example, described angle greater than 90 ℃ less than 120 ℃.
Among the embodiment therein, the concrete steps of described exposure and developing process are as follows: the Semiconductor substrate 100 that will have described photoresist layer 200 places exposure sources; Select suitable exposure focal length for use, described photoresist layer 200 is exposed by mask plate with patterns of openings; The photoresist layer 200 of finishing exposure is carried out developing process; After executing described developing process, described photoresist layer 200 is carried out baking process.
Because in exposure technology, the focal length of exposure sources can influence the side wall profile that forms opening, places optimum exposure position (focussing plane) to expose on the surface of photoresist layer and the opening that forms has vertical or subvertical side wall profile (with the Surface Vertical of described Semiconductor substrate 100).And expose when departing from described optimum exposure position in the surface of photoresist layer and the opening that forms can have the angled side walls profile, and upwards depart from different from the angle of the side wall profile that forms with downward bias.Thereby, among the embodiment therein, can utilize this principle to form to have the opening 204 of sloped sidewall 205 profiles, concrete, when exposure, adjust the exposure focal length, exposed towards imaging len (Lens) the deviation in driction focussing plane of exposure sources in described photoresist layer 200 surfaces, and can form the opening with sloped sidewall 205 204 that meets the demands by developing, and far away more at this deviation in driction focussing plane, described angle 206 is big more, thereby, can control the size of described angle 206 by the distance that departs from focussing plane, form the opening 204 of different sloped sidewalls 205.
In addition, after the developing process, also have baking (or being called hard roasting Hard bake) technology, and the temperature of baking can influence side wall profile 205 inclinations angle (being described angle 206) of described opening 204.Thereby, in a further embodiment, can utilize this principle, adjust the temperature of baking, make described opening 204 have sloped sidewall 205, concrete, the temperature of the baking of the temperature that makes described baking process when forming vertical sidewall.Make the sidewall of described opening 204 have sloped sidewall 205.
In addition, in other enforcement, can make the imaging len deviation in driction focussing plane of described photoresist layer surface by adjusting exposure equipment focal distance towards exposure sources, the method that the temperature of the baking of the temperature that makes described baking process with the temperature of adjusting baking process when forming vertical sidewall combines, make described opening 204 have angled side walls 205, repeat no more here.
Form after the described opening 204, please refer to Fig. 9, the Semiconductor substrate 101 of described open bottom is carried out ion implantation technology, in the Semiconductor substrate 100 of described grid 108a both sides, form source electrode 118a and drain electrode 118b.
Because described opening 204 has angled side walls, when carrying out described ion implantation technology, can increase the scattering probability of the ion that enters into described photoresist layer 200, please refer to Fig. 9, ion towards 205 scatterings of described opening 204 sidewalls can take place twice or repeatedly scattering, this can reduce to be scattered ion energy on the one hand, its speed of moving in photoresist layer is descended, to such an extent as to some ion can not pass this photoresist layer 200; Can change the ion scattering angle on the other hand, it can not passed by described opening 204 sidewalls 205.Thereby can reduce or eliminate in the ion implantation technology and to pass by described opening 204 sidewalls 205 and be injected into ion in the Semiconductor substrate 100 of opening 204 bottoms, the dosage of the ion that injects in the Semiconductor substrate 100 and the regional controllability of injection are improved, make source electrode 118a that forms and the electrology characteristic that drains 118b improve, and then the electric property of the feasible semiconductor device that forms improves the electrical stability increase.In addition, also make this ion implantation technology repeatability improve, the yield of the semiconductor device of formation promotes.
After finishing described ion implantation technology, remove described photoresist layer 200, repeat no more here.
In a further embodiment, can also be before forming photoresist layer 200, on described Semiconductor substrate 100, form anti-reflecting layer (not shown), after forming described opening 204, described anti-reflecting layer is positioned at the bottom of described opening 204, the ion that also can stop the sidewall 205 that passes described opening 204 enters into Semiconductor substrate 100, no longer gives unnecessary details here.
In a further embodiment, before forming described photoresist layer, can form resilient coating (not shown) at described semiconductor substrate surface earlier, for example described resilient coating can be a silicon oxide layer, after forming described opening 204, described resilient coating is positioned at described opening 204 bottoms, can stop that the ion of the sidewall 205 that passes described opening 204 enters into Semiconductor substrate 100, no longer gives unnecessary details here.
In a further embodiment, before forming described photoresist, form resilient coating at described semiconductor substrate surface earlier, form anti-reflecting layer at described buffer-layer surface again, form described photoresist layer 200 then.Here no longer launch to discuss.
Ion implantation technology of the present invention can be applicable to have in the manufacture method of semiconductor device of ion implantation technology, no longer launches here to discuss.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1, a kind of ion injection method is characterized in that, comprising:
Semiconductor substrate is provided;
On described Semiconductor substrate, form photoresist layer;
Graphical described photoresist layer is formed for defining the opening of Semiconductor substrate intermediate ion injection zone, and the sidewall of described opening tilts;
Semiconductor substrate to described open bottom is carried out ion implantation technology;
Wherein, described sidewall and describedly treat that the angle on injection zone surface is the obtuse angle.
2, ion injection method as claimed in claim 1 is characterized in that, graphical described photoresist layer, and the step that forms described opening is as follows:
The Semiconductor substrate that will have described photoresist layer places exposure sources;
Select the focal length that departs from the optimum exposure focal length for use, described photoresist layer is exposed by mask plate with patterns of openings;
The photoresist layer of finishing exposure is carried out developing process;
After executing described developing process, described photoresist layer is carried out baking process.
3, ion injection method as claimed in claim 2, it is characterized in that, by adjusting the exposure focal length, make described photoresist layer surface carry out exposure technology towards the imaging len deviation in driction focussing plane of exposure sources, make the described opening of formation have angled side walls.
4, ion injection method as claimed in claim 2, it is characterized in that, by adjusting the temperature of baking process, the temperature of the baking of the temperature that makes described baking process when forming vertical sidewall is carried out baking process, makes the described opening of formation have angled side walls.
5, ion injection method as claimed in claim 2, it is characterized in that, make the imaging len deviation in driction focussing plane of described photoresist layer surface by adjusting exposure equipment focal distance towards exposure sources, the method that the temperature of the baking of the temperature that makes described baking process with the temperature of adjusting baking process when forming vertical sidewall combines makes described opening have angled side walls.
6, as the described ion injection method of the arbitrary claim of claim 1 to 5, it is characterized in that: before described formation photoresist layer, on described Semiconductor substrate, form anti-reflecting layer earlier.
7, as the described ion injection method of the arbitrary claim of claim 1 to 5, it is characterized in that: before described formation photoresist layer, on described Semiconductor substrate, form resilient coating earlier.
8, as the described ion injection method of the arbitrary claim of claim 1 to 5, it is characterized in that: described angle greater than 90 ℃ less than 120 ℃.
9, ion injection method as claimed in claim 1 is characterized in that: described ion implantation technology is source electrode and drain ion injection technology, trap ion implantation technology, lightly doped drain ion implantation technology, adjust the ion implantation technology of threshold voltage or improve the ion implantation technology of breakdown characteristics.
10, a kind of manufacture method of semiconductor device comprises ion implantation technology, it is characterized in that, at least one ion implantation technology is the described ion injection method of the arbitrary claim of claim 1 to 9.
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| CN200810112805A CN101593682B (en) | 2008-05-26 | 2008-05-26 | Ion implantation method and manufacturing method of semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117742B (en) * | 2010-01-05 | 2013-03-13 | 上海华虹Nec电子有限公司 | Method for reinforcing capability of blocking tilt angle ion injection |
| CN103337482A (en) * | 2013-06-17 | 2013-10-02 | 上海集成电路研发中心有限公司 | Static random access memory transistor unit manufacturing method capable of adjusting threshold voltage |
| CN107683521A (en) * | 2015-04-30 | 2018-02-09 | 德克萨斯仪器股份有限公司 | Method for manufacturing the particular terminal angle in titanium tungsten layer |
| CN107949904A (en) * | 2015-04-09 | 2018-04-20 | 德克萨斯仪器股份有限公司 | Inclination terminal in molybdenum layer and preparation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6106995A (en) * | 1999-08-12 | 2000-08-22 | Clariant Finance (Bvi) Limited | Antireflective coating material for photoresists |
| JP3730947B2 (en) * | 2002-10-08 | 2006-01-05 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
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2008
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117742B (en) * | 2010-01-05 | 2013-03-13 | 上海华虹Nec电子有限公司 | Method for reinforcing capability of blocking tilt angle ion injection |
| CN103337482A (en) * | 2013-06-17 | 2013-10-02 | 上海集成电路研发中心有限公司 | Static random access memory transistor unit manufacturing method capable of adjusting threshold voltage |
| CN107949904A (en) * | 2015-04-09 | 2018-04-20 | 德克萨斯仪器股份有限公司 | Inclination terminal in molybdenum layer and preparation method thereof |
| CN107683521A (en) * | 2015-04-30 | 2018-02-09 | 德克萨斯仪器股份有限公司 | Method for manufacturing the particular terminal angle in titanium tungsten layer |
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