CN102468237B - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN102468237B CN102468237B CN201010532048.9A CN201010532048A CN102468237B CN 102468237 B CN102468237 B CN 102468237B CN 201010532048 A CN201010532048 A CN 201010532048A CN 102468237 B CN102468237 B CN 102468237B
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Abstract
The invention discloses a manufacturing method for a semiconductor device, and belongs to the technical field of semiconductors. The method comprises the following steps of: providing a semiconductor substrate; forming a gate dielectric layer and a gate positioned on the gate dielectric layer on the semiconductor substrate; forming source/drain areas in the semiconductor substrate of two sides of the gate, and injecting fluorine ions during forming of the source/drain areas; and sequentially performing fast peak annealing and laser pulse annealing after the source/drain areas are formed. The fluorine ions enter the gate dielectric layer, and replace a part of oxygen ions in the gate dielectric layer to form fluorine and silicon groups, so the hot carrier injection (HCI) effect of an N-channel metal oxide semiconductor (NMOS) transistor and a negative bias temperature instability (NBTI) effect of a P-channel metal oxide semiconductor (PMOS) are improved.
Description
Technical field
What the present invention relates to is a kind of manufacture method of technical field of semiconductors, particularly be a kind of manufacture method that comprises nmos pass transistor and the transistorized semiconductor device of PMOS.
Background technology
Development along with technique, the size of semiconductor device constantly reduces, the HCI of nmos pass transistor (HotCarrier Injection, hot carrier is injected) effect and the transistorized NBTI of PMOS (Negative BiasTemperature Instability, back bias voltage unsteadiness) effect is all thereupon more and more serious, becomes the subject matter that affects semiconductor device reliability.
Along with dwindling of semiconductor device channel length, in order to obtain required drive current and to suppress short-channel effect, conventionally adopt Semiconductor substrate and the source-drain electrode of higher concentration doping, thereby produce high electric field in the depleted region of source-drain electrode.When high voltage input/output device moves under saturation current state, inversion layer charge under the effect of channel surface transverse electric field accelerated and with the lattice ionization that bumps, can produce a large amount of hot carriers (electron hole pair).Hot electron and hot hole can be crossed interface potential barrier and launch to gate oxide, form hot carrier injection effect (HCI).The hot carrier that enters gate oxide has following impact: or penetrate oxide layer or cause in time and the interfacial state that increases or cause carrier traps; Meanwhile, hot electron and hot hole can also be subject to the effect of node field and enter substrate, form substrate leakage current, and the above results that hot carrier causes can have a strong impact on device operating characteristic and reliability.
The conduction carrier of nmos pass transistor is electronics, and the transistorized conduction carrier of PMOS is hole, and the mobility ratio hole of electronics is much larger, therefore under same electric field, electronics can obtain larger energy, under high electric field, electronics is accelerated as " hot electron ", and hot hole is difficult to occur.What therefore, should mainly overcome is the HCI effect of nmos pass transistor.
Current, industry is to improve the HCI of nmos pass transistor, conventionally adopt LDD (Lightly DopedDrain, lightly doped drain injection) optimization method of Implantation, utilization reduces the dosage of LDD Implantation and increases LDD Implantation Energy, obtain darker LDD knot, reduce transverse electric field intensity, thereby improve HCI.But increase LDD ion implantation energy, along with the increasing of junction depth, the length of effective channel of device also will reduce, will increase like this short-channel effect (Short Channel Effect is called for short SCE), cause the decline of device DC characteristic.Therefore, merely by changing the dosage of LDD Implantation and energy, to improve HCI be inadequate.
In order to overcome above-mentioned shortcoming, Chinese Patent Application No. is: 200410089222.1, name is called: reduce the method that I/O nmos device hot carrier is injected, first this technology carries out polysilicon gate etching, then carries out polysilicon gate and reoxidize, and then carries out LDD rapid thermal annealing, after annealing, first in LDD, adopt arsenic ion to inject, then in LDD, adopt phosphonium ion to inject, finally carry out polysilicon side wall deposit and etching.But this technology has changed existing technique, poor with the compatibility of existing technique.
In order to improve the HCI effect of nmos pass transistor, prior art also discloses a kind of technical scheme, anneals, so that the foreign ion that low doping source/drain region is injected fully activates and spreads after source/leakage extended structure of nmos pass transistor forms.But in above-mentioned technology, along with dimensions of semiconductor devices continue dwindle, in the semiconductor device in 65nm and following size, technique scheme is not enough to suppress hot carrier injection effect, thereby inapplicable.
Described NBTI refers at high temperature, and under effect of stress, the transistorized threshold voltage of PMOS drifts about.In the manufacturing technology of existing MOS transistor, conventionally first in Semiconductor substrate, form gate oxide, on gate oxide, form grid conductive layer, then by etching grid conductive layer and gate oxide, form grid, then the substrate intermediate ion in grid both sides injects and forms source area and drain region, thereby forms metal-oxide-semiconductor.Wherein, described gate oxide utilizes oxide to form conventionally, for example the silicon dioxide of silicon dioxide or doping.In the manufacture process of MOS transistor, in order to reduce the resistance of grid, conventionally after grid conductive layer forms, grid conductive layer is adulterated, for example utilize the mode of Implantation in the grid conductive layer of PMOS device, to inject the boron ion of P type.Then by applying cut-in voltage to the grid of MOS transistor, can between source area and drain region, form conducting channel, by the electrical potential difference between source area and drain region, in conducting channel, produce drain current.Along with variations in temperature, the electric charge and the electronics that between the interface between Semiconductor substrate and gate oxide, exist change, and drain current is worsened, thereby produce NBTI effect.
Chinese Patent Application No. is: 200810224805.9, and name is called: the transistorized manufacture method of PMOS and PMOS transistor, provided a kind of transistorized manufacture method of PMOS of the NBTI of overcoming effect, comprise step: provide semi-conductive substrate; In Semiconductor substrate, form grid oxide layer; On grid oxide layer, form grid conductive layer; By grid conductive layer to grid oxide layer doped F ion; Etching grid conductive layer and grid oxide layer, form grid; In the Semiconductor substrate of grid both sides, form source area and drain region.But the method is only applicable to PMOS transistor.When preparing semiconductor device, in order to overcome the transistorized NBTI effect of PMOS, also need nmos pass transistor device wherein to cover up a pair pmos transistor operation.Further, in order to overcome the HCI effect of nmos pass transistor, PMOS transistor need to be covered up, adopt the operation of different measure pair nmos transistor.
Summary of the invention
The technical problem to be solved in the present invention is: in the manufacture process of semiconductor device, how by simple, effectively step overcomes HCI effect and the transistorized NBTI effect of PMOS of nmos pass transistor simultaneously.
For addressing the above problem, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided; In described Semiconductor substrate, form gate dielectric and be positioned at the grid on gate dielectric; Formation source/drain region in the Semiconductor substrate of grid both sides, and during formation source/drain region, in described grid, inject fluorine ion; Carry out successively fast peak annealing and laser pulse annealing.
Alternatively, described formation source/drain region comprises successively: light dope Implantation; In described grid, inject fluorine ion; Heavy doping ion is injected.
Alternatively, described formation source/drain region comprises successively: light dope Implantation; Heavy doping ion is injected; In described grid, inject fluorine ion.
Alternatively, described formation source/drain region comprises successively: in described grid, inject fluorine ion; Light dope Implantation; Heavy doping ion is injected.
Alternatively, the Implantation Energy scope of described fluorine ion is 2KeV to 20KeV, and ion implantation dosage scope is 1E14/cm
2to 3E15/cm
2.
Alternatively, the temperature peak scope of described fast peak annealing is 900 ℃ to 1070 ℃, and annealing time is 5 seconds to 60 seconds.
Alternatively, the temperature peak scope of described laser pulse annealing is 1200 ℃ to 1300 ℃.
Compared with prior art, the present invention has the following advantages:
1, improve the HCI effect of nmos pass transistor: in grid, inject fluorine ion, and make part fluorine ion diffuse into gate dielectric by fast peak annealing process, by laser pulse, anneal and activated the fluorine ion in gate dielectric again, make fluorine ion replace the partial oxygen ion in gate dielectric, thereby form fluorine silicon group, due to fluorine ion, repair the function of chemical bond simultaneously, and then the interface that makes gate dielectric and Semiconductor substrate becomes finer and close, improved the interface quality between gate dielectric and Semiconductor substrate, nmos pass transistor, stop and form charge trap, prevent lightly-doped source under making alive/drain region gathering electric charge, thereby greatly improved the HCI effect of nmos pass transistor,
2, improve the transistorized NBTI effect of PMOS: in grid, inject fluorine ion, and make part fluorine ion diffuse into gate dielectric by fast peak annealing process, by laser pulse, anneal and activated the fluorine ion in gate dielectric again, make fluorine ion replace the partial oxygen ion in gate dielectric, thereby form fluorine silicon group, because fluorine silicon key is more more firm than si-h bond, prevent at high temperature, generate silicon dangling bonds, thereby alleviate due to the impact of NBTI effect on MOS transistor;
3, technique is simple, cost is low: the inventive method can be used for generating simultaneously containing nmos pass transistor and the transistorized semiconductor of PMOS, directly in the process in formation source/drain region, in grid, inject fluorine ion, and needn't block respectively nmos pass transistor or PMOS transistor, to adopt different measure to overcome HCI effect and the transistorized NBTI effect of PMOS of nmos pass transistor.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of embodiment 1 semiconductor device;
Fig. 2 to Fig. 9 forms the schematic diagram of semiconductor device according to the flow process shown in Fig. 1;
Figure 10 is the schematic flow sheet of the manufacture method of embodiment 2 semiconductor device;
Figure 11 is the schematic flow sheet of the manufacture method of embodiment 3 semiconductor device.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.
Just as described in the background section, in existing semiconductor fabrication process, there is serious HCI effect in nmos pass transistor, and PMOS transistor exists serious NBTI effect, and these become the subject matter that affects semiconductor device reliability.
Therefore,, when manufacturing semiconductor device, for preventing the generation of above-mentioned defect, the manufacture method of semiconductor device provided by the invention comprises: Semiconductor substrate is provided; In described Semiconductor substrate, form gate dielectric and be positioned at the grid on gate dielectric; Formation source/drain region in the Semiconductor substrate of grid both sides, and during formation source/drain region, in described grid, inject fluorine ion; Carry out successively fast peak annealing and laser pulse annealing.The present invention contains in nmos pass transistor and the transistorized semiconductor device process of PMOS in preparation, has both improved the HCI effect of nmos pass transistor, improved again the transistorized NBTI effect of PMOS, and technique is simple, cost is low.
Below the relational language relating in embodiment is illustrated in advance, described N-type dopant well is the low-doped p-type substrate of nmos pass transistor, and described P type dopant well is the transistorized low-doped N-shaped substrate of PMOS; Described N-type gate dielectric is the gate dielectric of nmos pass transistor, and described P type gate dielectric is the transistorized gate dielectric of PMOS; Described N-type grid is the grid of nmos pass transistor, and described P type grid is the transistorized grid of PMOS; Described N-type isolated side wall is the isolated side wall of nmos pass transistor, and described P type isolated side wall is the transistorized isolated side wall of PMOS; Described N-type bag-like region is the bag-like region on nmos pass transistor, and described P type bag-like region is the bag-like region on PMOS transistor; Described N-type lightly-doped source/drain region is the N-shaped lightly-doped source/drain region of nmos pass transistor, and described P type lightly-doped source/drain region is the transistorized p-type of PMOS lightly-doped source/drain region; Described N-type heavy-doped source/drain region is the N-shaped heavy-doped source/drain region of nmos pass transistor, and described P type heavy-doped source/drain region is the transistorized p-type of PMOS heavy-doped source/drain region.
Embodiment 1
As shown in Figure 1, in the present embodiment, the manufacture method of semiconductor device comprises the following steps:
S100, provides Semiconductor substrate;
S101 forms gate dielectric and is positioned at the grid on gate dielectric in described Semiconductor substrate;
S102 carries out light dope Implantation in the Semiconductor substrate of grid both sides, forms lightly-doped source/drain region;
S103 injects fluorine ion in described grid;
S104 carries out heavy doping ion injection in the Semiconductor substrate of grid both sides, forms heavy-doped source/drain region;
S105, carries out fast peak annealing and laser pulse annealing successively.
With reference to figure 2, first perform step S100, Semiconductor substrate 200 is provided.Wherein, described Semiconductor substrate 200 comprises: N-type dopant well 200-N, P type dopant well 200-P and isolation structure 210.Described Semiconductor substrate 200 is silicon, the silicon-on-insulator (SOI) that is formed with semiconductor device that is formed with semiconductor device or is body silicon.The a small amount of boron ion of doping or indium ion etc. in described N-type dopant well 200-N, a small amount of phosphonium ion of doping or arsenic ion etc. in described P type dopant well 200-P.
Then perform step S101, form N-type gate dielectric 201-N and be positioned at the N-type grid 202-N on N-type gate dielectric 201-N on described N-type dopant well 200-N, N-type gate dielectric 201-N and N-type grid 202-N form grid structure; On described P type dopant well 200-P, form P type gate dielectric 201-P and be positioned at the P type grid 202-P on P type gate dielectric 201-P, P type gate dielectric 201-P and P type grid 202-P form grid structure, form structure as shown in Figure 3.
Described N-type gate dielectric 201-N and P type gate dielectric 201-P are silicon dioxide or silicon oxynitride, and it forms technique can be chemical vapor deposition method.
Described N-type grid 202-N and P type grid 202-P are polysilicon or multicrystalline silicon compounds, it forms technique can adopt any prior art well known to those skilled in the art, as while adopting chemical vapour deposition technique, can be low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition.
Then perform step S102, in the N-type dopant well 200-N of N-type grid 202-N both sides, carry out N-shaped light dope Implantation, form N-type lightly-doped source/drain region 203-N; In the P type dopant well 200-P of P type grid 202-P both sides, carry out p-type light dope Implantation, form P type lightly-doped source/drain region 203-P.In the prior art, the light dope Implantation of nmos pass transistor is that to take N-type gate dielectric 201-N and N-type grid 202-N be mask, in N-type dopant well 200-N, carry out N-shaped light dope Implantation, in N-type dopant well 200-N, form unactivated N-type lightly-doped source/drain region 203-N; The transistorized light dope Implantation of PMOS is that to take P type gate dielectric 201-P and P type grid 202-P be mask, in P type dopant well 200-P, carry out p-type light dope Implantation, in P type dopant well 200-P, form unactivated P type lightly-doped source/drain region 203-P.
The doping ion of described N-shaped light dope Implantation can be phosphonium ion or arsenic ion etc.: when the ion of light dope Implantation is phosphonium ion, the energy range of Implantation is 1KeV to 20KeV, and the dosage range of Implantation is 1E14/cm
2to 1E15/cm
2; When the ion of light dope Implantation is arsenic ion, the energy range of Implantation is 2KeV to 35KeV, and the dosage range of Implantation is 1E14/cm
2to 1E15/cm
2.
The doping ion of described p-type light dope Implantation can be boron ion or indium ion etc.: when the ion of light dope Implantation is boron ion, the energy range of Implantation is 2KeV to 15KeV, and the dosage range of Implantation is 1E14/cm
2to 1E15/cm
2; When the ion of light dope Implantation is indium ion, the energy range of Implantation is 40KeV to 120KeV, and the dosage range of Implantation is 1E14/cm
2to 1E15/cm
2.
Further, in step S102, before or after carrying out N-shaped light dope Implantation, can also carry out N-shaped bag-like region Implantation and form unactivated N-type bag-like region 204a-N, correspondingly, before or after carrying out p-type light dope Implantation, also can carry out p-type bag-like region Implantation and form unactivated P type bag-like region 204a-P, form structure as shown in Figure 4.It should be noted that the ionic conduction type opposite of the ion of described N-shaped bag-like region Implantation and N-shaped light dope Implantation, the ionic conduction type opposite of the ion of described p-type bag-like region Implantation and p-type light dope Implantation.Accordingly, when form the technique of unactivated N-type bag-like region 204a-N and unactivated P type bag-like region 204a-P in step S102 after, in step S102, also comprise by spike annealing at a slow speed and form N-type bag-like region 204-N, P type bag-like region 204-P, N-type lightly-doped source/drain region 203-N of activation and P type lightly-doped source/drain region 203-P of activation, form structure as shown in Figure 5.
In addition; in the embodiment of above-mentioned manufacture semiconductor device; spike annealing technique is to carry out after light dope Implantation and bag-like region Implantation step at a slow speed; but not as limit; in other embodiments; spike annealing technique also can divide secondary to carry out at a slow speed; after light dope Implantation step, carry out for the first time at a slow speed spike annealing step and after bag-like region Implantation step, carry out for the second time spike annealing step at a slow speed, at this, should too much not limit the scope of the invention.
Then perform step S103; in described N-type grid 202-N and P type grid 202-P, inject fluorine ion 207 simultaneously; form structure as shown in Figure 6; ★ wherein represents fluorine ion 207; it is schematic diagram herein; can not represent the actual implantation dosage of fluorine ion 207 and inject the degree of depth, should be not too much at this limit the scope of the invention.
The Implantation Energy scope of described fluorine ion 207 is 2KeV to 20KeV, and implantation dosage scope is 1E14/cm
2to 3E15/cm
2.
As a specific embodiment of the present invention, can also after injecting fluorine ion or before injection fluorine ion, inject phosphonium ion by the grid at nmos pass transistor, the Implantation Energy scope of this phosphonium ion is 3KeV to 10KeV, implantation dosage scope is 1E15/cm
2to 5E15/cm
2, to reduce the loss of described N-type grid 202-N.
Then perform step S104, in the Semiconductor substrate 200 of described grid 202 both sides, carry out heavy doping ion injection, form heavy-doped source/drain region 206.
Further, the described heavy doping ion of carrying out is injected and to be comprised: in the relative both sides of described N-type gate dielectric 201-N and described N-type grid 202-N, form N-type isolated side wall 205-N, in the relative both sides of described P type gate dielectric 201-P and described P type grid 202-P, form P type isolated side wall 205-P, form structure (N-type isolated side wall 205-N and P type isolated side wall 205-P can be a kind of in silica, silicon nitride, silicon oxynitride or they combine arbitrarily) as shown in Figure 7; Take described N-type grid 202-N and described N-type isolated side wall 205-N is mask, in N-type dopant well 200-N, carry out the injection of N-shaped heavy doping ion, to form N-type heavy-doped source/drain region 206-N, take described P type grid 202-P and described P type isolated side wall 205-P is mask, in P type dopant well 200-P, carry out the injection of p-type heavy doping ion, to form P type heavy-doped source/drain region 206-P, form structure as shown in Figure 8.
Described N-shaped heavy doping ion is injected to be included in and in N-type dopant well 200-N, is injected phosphonium ion or arsenic ion to form N-type heavy-doped source/drain region 206-N.
Described p-type heavy doping ion is injected and is included in P type dopant well 200-P B Implanted ion or indium ion to form P type heavy-doped source/drain region 206-P.
Finally perform step S105, carry out successively fast peak annealing and laser pulse annealing.
The temperature peak scope of described fast peak annealing is 900 ℃ to 1070 ℃, annealing time is 5 seconds to 60 seconds, fast peak annealing now can make wherein part fluorine ion 207 diffuse into N-type gate dielectric 201-N and P type gate dielectric 201-P, shown in figure 9.
The temperature peak scope of described laser pulse annealing is 1200 ℃ to 1300 ℃, laser pulse annealing now can make the fluorine ion 207 that enters N-type gate dielectric 201-N and P type gate dielectric 201-P be activated, and the partial oxygen ion that the fluorine ion 207 being activated replaces in N-type gate dielectric 201-N and P type gate dielectric 201-P, thereby form fluorine silicon group.
The present embodiment by adding after the technique of injecting fluorine ion 207 in N-type grid 202-N and P type grid 202-P, and the nmos pass transistor of preparing can be by the system performance testing of HCI, and PMOS transistor can be by the system performance testing of NBTI; And the nmos pass transistor that adopts prior art to prepare can not be by the system performance testing of HCI, PMOS transistor can not be by the system performance testing of NBTI.
Embodiment 2
As shown in figure 10, in the present embodiment, the manufacture method of semiconductor device comprises the following steps:
S300, provides Semiconductor substrate;
S301 forms gate dielectric and is positioned at the grid on gate dielectric in described Semiconductor substrate;
S302 carries out light dope Implantation in the Semiconductor substrate of grid both sides, forms lightly-doped source/drain region;
S303 carries out heavy doping ion injection in the Semiconductor substrate of grid both sides, forms heavy-doped source/drain region;
S304 injects fluorine ion in described grid;
S305, carries out fast peak annealing and laser pulse annealing successively.
The difference of the present embodiment and embodiment 1 is only that " carrying out heavy doping ion injection in the Semiconductor substrate of grid both sides; form heavy-doped source/drain region " step is different with the execution sequence of " injecting fluorine ion in described grid " step, and carrying into execution a plan that each step is concrete is identical with embodiment 1.
The present embodiment by add injecting after the technique of fluorine ion in grid, and the nmos pass transistor of preparing can be by the system performance testing of HCI, and PMOS transistor can be by the system performance testing of NBTI, and effect is with embodiment 1; And the nmos pass transistor that adopts prior art to prepare can not be by the system performance testing of HCI, PMOS transistor can not be by the system performance testing of NBTI.
Embodiment 3
As shown in figure 11, in the present embodiment, the manufacture method of semiconductor device comprises the following steps:
S400, provides Semiconductor substrate;
S401 forms gate dielectric and is positioned at the grid on gate dielectric in described Semiconductor substrate;
S402 injects fluorine ion in described grid;
S403 carries out light dope Implantation in the Semiconductor substrate of grid both sides, forms lightly-doped source/drain region;
S404 carries out heavy doping ion injection in the Semiconductor substrate of grid both sides, forms heavy-doped source/drain region;
S405, carries out fast peak annealing and laser pulse annealing successively.
The difference of the present embodiment and embodiment 1 is only that " carrying out light dope Implantation in the Semiconductor substrate of grid both sides; form lightly-doped source/drain region " step is different with the execution sequence of " injecting fluorine ion in described grid " step, and carrying into execution a plan that each step is concrete is identical with embodiment 1.
The present embodiment by add injecting after the technique of fluorine ion in grid, and the nmos pass transistor of preparing can be by the system performance testing of HCI, and PMOS transistor can be by the system performance testing of NBTI, and effect is with embodiment 1; And the nmos pass transistor that adopts prior art to prepare can not be by the system performance testing of HCI, PMOS transistor can not be by the system performance testing of NBTI.
The present invention injects fluorine ion in grid, and make part fluorine ion diffuse into gate dielectric by fast peak annealing process, by laser pulse, anneal and activated the fluorine ion in gate dielectric again, make fluorine ion replace the partial oxygen ion in gate dielectric, form fluorine silicon group, thereby improved HCI effect and the transistorized NBTI effect of PMOS of nmos pass transistor simultaneously; And technique is simple, cost is low, can be used for preparation simultaneously containing nmos pass transistor and the transistorized semiconductor of PMOS, directly in the process in formation source/drain region, in grid, inject fluorine ion, and needn't block respectively nmos pass transistor or PMOS transistor, to adopt different measure to overcome HCI effect and the transistorized NBTI effect of PMOS of nmos pass transistor.
Although oneself discloses the present invention as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (9)
1. a manufacture method for semiconductor device, described semiconductor device comprises: nmos pass transistor and PMOS transistor, described manufacture method comprises: Semiconductor substrate is provided; In described Semiconductor substrate, form the transistorized gate dielectric of nmos pass transistor and PMOS and be positioned at the grid on gate dielectric; Formation source/drain region in the Semiconductor substrate of nmos pass transistor and the transistorized grid of PMOS both sides; It is characterized in that,
During formation source/drain region, in nmos pass transistor and the transistorized described grid of PMOS, inject fluorine ion simultaneously;
Also comprise: behind formation source/drain region, carry out successively fast peak annealing and laser pulse annealing.
2. the manufacture method of semiconductor device according to claim 1, is characterized in that, described formation source/drain region comprises successively: light dope Implantation; In described grid, inject fluorine ion; Heavy doping ion is injected.
3. the manufacture method of semiconductor device according to claim 1, is characterized in that, described formation source/drain region comprises successively: light dope Implantation; Heavy doping ion is injected; In described grid, inject fluorine ion.
4. the manufacture method of semiconductor device according to claim 1, is characterized in that, described formation source/drain region comprises successively: in described grid, inject fluorine ion; Light dope Implantation; Heavy doping ion is injected.
5. according to the manufacture method of the semiconductor device described in any one in claim 1 to 4, it is characterized in that, the Implantation Energy scope of described fluorine ion is 2KeV to 20KeV, and ion implantation dosage scope is 1E14/cm
2to 3E15/cm
2.
6. the manufacture method of semiconductor device according to claim 1, is characterized in that, the temperature peak scope of described fast peak annealing is 900 ℃ to 1070 ℃, and annealing time is 5 seconds to 60 seconds.
7. the manufacture method of semiconductor device according to claim 1, is characterized in that, the temperature peak scope of described laser pulse annealing is 1200 ℃ to 1300 ℃.
8. according to the manufacture method of the semiconductor device described in any one in claim 2 to 4, it is characterized in that, described Semiconductor substrate comprises: N-type dopant well and P type dopant well, described light dope Implantation comprises: take grid as mask, in described N-type dopant well, inject phosphonium ion or arsenic ion to form lightly-doped source/drain region, in described P type dopant well, B Implanted ion or indium ion are to form lightly-doped source/drain region.
9. according to the manufacture method of the semiconductor device described in any one in claim 2 to 4, it is characterized in that, described Semiconductor substrate comprises: N-type dopant well and P type dopant well, and described heavy doping ion is injected and is comprised: the relative both sides at described gate dielectric and described grid form isolated side wall; Take described grid and described isolated side wall is mask, injects phosphonium ion or arsenic ion to form heavy-doped source/drain region in described N-type dopant well, and in described P type dopant well, B Implanted ion or indium ion are to form heavy-doped source/drain region.
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| Analysis of Dopant Diffusion and Defect Evolution during sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach;T. Noda等;《2006 INTERNATIONAL ELECTRON DEVICES MEETING》;20061213;第1-2卷;第112-115页 * |
| T. Noda等.Analysis of Dopant Diffusion and Defect Evolution during sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach.《2006 INTERNATIONAL ELECTRON DEVICES MEETING》.2006,第1-2卷 |
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| CN102468237A (en) | 2012-05-23 |
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