CN109427887A - A kind of manufacturing method and semiconductor devices of semiconductor devices - Google Patents
A kind of manufacturing method and semiconductor devices of semiconductor devices Download PDFInfo
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- 238000005468 ion implantation Methods 0.000 claims abstract description 29
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- 238000002513 implantation Methods 0.000 claims description 9
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- 229910052738 indium Inorganic materials 0.000 claims description 7
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- 239000004020 conductor Substances 0.000 claims 3
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- 229910052785 arsenic Inorganic materials 0.000 description 1
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- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
Abstract
The present invention provides the manufacturing method and semiconductor devices of a kind of semiconductor devices, which comprises provides semiconductor substrate, forms gate stack structure on the semiconductor substrate；To closed in the semiconductor substrate gate stack structure wherein side region execute the first ion implantation technology, to form the first ion implanted region；LDD injection is executed to the region for closing on the gate stack structure two sides in the semiconductor substrate, to form LDD region.Using method of the invention, the first ion implanted region for being located at gate stack structure wherein side is formed before LDD injection, on the one hand can inhibit the impurity for the LDD region being subsequently formed that short-channel effect caused by horizontal proliferation occurs；On the other hand, can to avoid the component failure caused by hot carrier's effect, inhibiting to be weighed between short-channel effect and hot carrier's effect.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to the manufacturing method and semiconductor of a kind of semiconductor devices
Device.
Background technique
With semiconductor devices integrated level continue to increase and the lasting reduction of critical dimension relevant to these devices,
It especially is to proceed to 28nm and its following technology node, semiconductor devices has highlighted various unfavorable physics due to extremely short channel
Effect, especially short-channel effect (Short Channel Effect, SCE), so that device performance and reliable sexual involution, limitation
The further reducing of characteristic size.
Currently, load can be improved by injecting carbon while (Lightly Doped Drain, LDD) injection is lightly doped
Transport factor and operating current are flowed, to improve the short-channel effect of device, so that the performance of device is improved, the quiescent current of device
(IDDQ) characteristic and drain induced barrier reduce effect (DIBL) and are improved.However, for high tension apparatus, it is sufficiently large in voltage
When, strong electrical field can be formed in vicinity, carrier obtains higher energy in this strong electrical field, becomes hot carrier, shape
At thermocurrent, high tension apparatus is caused to burn, referred to as hot carrier's effect.And as the dosage of carbon injection increases, LDD will lead to
The field distribution gradient of the PN junction in area increases, and leakage current increases, hot carrier's effect enhancing.
The purpose of the present invention is to provide a kind of manufacturing method of semiconductor devices and semiconductor devices, to solve above-mentioned skill
Art problem.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
The present invention provides a kind of manufacturing method of semiconductor devices, which comprises semiconductor substrate is provided, described
Gate stack structure is formed in semiconductor substrate；To closing on the gate stack structure wherein side in the semiconductor substrate
Region executes the first ion implantation technology, to form the first ion implanted region；To closing on the grid in the semiconductor substrate
The region of stacked structure two sides executes LDD injection, to form LDD region.
Further, first ion implanted region is formed in the source electrode side of the gate stack structure.
Further, first ion implantation technology includes favouring the ion implantation technology of the semiconductor substrate.
Further, the injection ion of first ion implantation technology includes carbon and nitrogen.
Further, the LDD injection includes that ion implantation technology is lightly doped perpendicular to the semiconductor substrate.
Further, the injection ion of the LDD injection includes boron or indium.
Further, after first ion implantation technology the step of, the LDD injection the step of before, it is described
Method further includes executing the second ion implanting work to the two side areas for closing on the gate stack structure in the semiconductor substrate
Skill, to form the second ion implanted region.
Further, second ion implantation technology includes the ion implantation technology perpendicular to the semiconductor substrate.
Further, the injection ion of second ion implantation technology includes carbon.
Further, the implantation dosage of second ion implantation technology is less than the injectant of first ion implantation technology
Amount.
The present invention also provides a kind of semiconductor devices, comprising: semiconductor substrate；Form grid on the semiconductor substrate
Pole stacked structure；Close in the semiconductor substrate the gate stack structure wherein side region formed the first ion
Injection region；The LDD region that the region of the gate stack structure two sides is formed is closed in the semiconductor substrate.
Further, first ion implanted region is formed in the source electrode side of the gate stack structure.
Further, the injection ion of first ion implanted region includes carbon and nitrogen.
Further, the injection ion of the LDD region includes boron or indium.
Further, the semiconductor devices further includes close on the gate stack structure in the semiconductor substrate two
The second ion implanted region that side region is formed.
Further, the injection ion of second ion implanted region includes carbon.
Further, the implantation dosage of second ion implanted region is less than the implantation dosage of first ion implanted region.
In conclusion according to the method for the present invention, is formed before LDD injection and to be located at gate stack structure wherein side
On the one hand first ion implanted region can inhibit the impurity for the LDD region being subsequently formed that short channel caused by horizontal proliferation occurs
Effect；On the other hand, can to avoid the component failure caused by hot carrier's effect, inhibit short-channel effect
Weighed between hot carrier's effect.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 is the technical process schematic diagram of semiconductor devices of the invention；
Fig. 2A -2H is schematically cuing open for the semiconductor devices that the step of method according to the present invention is successively implemented obtains respectively
Face figure.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Semiconductor devices manufacturing method.Obviously, the technical staff that execution of the invention is not limited to semiconductor field is familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or their combination.
Currently, carrier mobility and operating current can be improved by injecting carbon while LDD injects, to improve
The short-channel effect of device, to improve the performance of device, the IDDQ characteristic and DIBL of device are improved.However, for height
For voltage device, when voltage is sufficiently large, strong electrical field can be formed in vicinity, carrier obtains higher in this strong electrical field
Energy, become hot carrier, form thermocurrent, cause high tension apparatus to burn, referred to as hot carrier's effect.And as carbon is infused
The dosage entered increases, and the field distribution gradient that will lead to the PN junction of LDD region increases, and leakage current increases, hot carrier's effect enhancing.
Presence in view of the above problems, the invention proposes a kind of manufacturing methods of semiconductor devices, as shown in Figure 1, its
Including following key step:
In step s101, semiconductor substrate is provided, forms gate stack structure on the semiconductor substrate；
In step s 102, to closed in the semiconductor substrate gate stack structure wherein side region execute
First ion implantation technology, to form the first ion implanted region；
In step s 103, LDD is executed to the region for closing on the gate stack structure two sides in the semiconductor substrate
Injection, to form LDD region.
According to the method for the present invention, the first ion for being located at gate stack structure wherein side is formed before LDD injection
On the one hand injection region can inhibit the impurity for the LDD region being subsequently formed that short-channel effect caused by horizontal proliferation occurs；It is another
Aspect, can to avoid the component failure caused by hot carrier's effect, inhibiting short-channel effect and hot carrier
Weighed between effect.
With p-type Metal-Oxide Semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-
Effect Transistor, MOSFET) for, referring to Fig. 2A-Fig. 2 H, it is shown according to the method for the embodiment of the present invention
The schematic cross sectional view for the semiconductor devices that the step of successively implementing obtains respectively.
Firstly, as shown in Figure 2 A, providing semiconductor substrate 201, being formed with gate stack knot in the semiconductor substrate 201
Structure 202.
Specifically, the constituent material of the semiconductor substrate 201 can use undoped monocrystalline silicon, doped with impurity
Silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator for monocrystalline silicon, silicon-on-insulator (SOI)
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body can also use gallium nitride (GaN), aluminium nitride (AlN), nitrogen
Change indium (InN), GaAs (GaAS), zinc oxide (ZnO), silicon carbide (SiC) etc., in the present invention, the semiconductor substrate choosing
It is constituted with single crystal silicon material.Isolation structure and various traps (well) structure are formed in the semiconductor substrate 201, in order to
Simplify, is not shown in diagram.
As an example, the gate stack structure 202 includes gate oxide 202a, grid 202b and grid low resistance
Layer 202c, the gate oxide 202a cover the portion of upper surface of the semiconductor substrate 201, described in the grid 202b covering
The upper surface of gate oxide 202a, the grid conductive formation 202c cover the upper surface of the grid 202b.
Next, as shown in Figure 2 B, inclined first ion implantation technology is executed, in the gate stack structure 202
202 lower section of source electrode side and the part gate stack structure semiconductor substrate 201 in form the first ion implanted region
203。
Wherein, the injection ion of the first ion implanting includes for carbon (C) and nitrogen (N).Illustratively, the energy of ion carbon is injected
Amount is 1KeV-5KeV, dosage e14-e15atom/cm2；The energy for injecting ionic nitrogen is 1KeV-5KeV, dosage e14-
e15atom/cm2.Further, the direction of ion beam and semiconductor substrate surface normal direction are in 0-30 ° of angle, are ion beam
Angle between direction and the semiconductor substrate surface normal direction, i.e. ion beam can be with semiconductor substrate surface normal sides
It is injected centered on to the direction of gate stack structure side.Further, the injection number of the ion implanting can be primary,
Or it is multiple.
Further, the method for forming first ion implanted region 203 includes: in gate stack structure drain electrode side
The semiconductor substrate and part the gate stack structure surface form patterned photoresist layer；With the photoresist layer
For exposure mask, angled ion implantation process is executed, in the source electrode side of the gate stack structure and the part gate stack
Ion implanted region is formed in semiconductor substrate below structure；Remove the photoresist layer.
Only source electrode side formed the first ion implanted region 203 can inhibit the lightly doped drain (LDD) being subsequently formed from
Horizontal proliferation occurs for the impurity of sub- injection region, leads to Punchthrough and short-channel effect, while can inhibit the loss of impurity；Together
When, since the first ion implanted region 203 is only formed in source electrode side, do not formed in drain electrode side, thus can be to avoid draining
Side occurs the high tension apparatus as caused by hot carrier's effect and burns failure；And use that angled ion implantation process formed the
The inhibiting effect to short-channel effect can be enhanced in one ion implanted region.
It should be noted that the first ion implanted region exists if the strong electrical field of high tension apparatus is when source electrode side is formed
It is formed in semiconductor substrate below drain electrode side and the part gate stack structure of gate stack structure.
Then, optionally, as shown in Figure 2 C, the second ion implantation technology perpendicular to the semiconductor substrate 201 is executed,
To form the second ion implanted region 204 in the semiconductor substrate 201 of 202 two sides of gate stack structure.
Wherein, the injection ion of the second ion implanting include be carbon (C) or nitrogen (N), injection ion in the present invention is
Carbon.The dosage of second ion implanting is less than the dosage of the first ion implanting, and the dose requirements of the second ion implanting are so that second
Ion implanted region will not influence the strong electrical field of drain electrode side, and then cause subject to hot carrier's effect.Illustratively, ion is injected
The dosage of carbon or nitrogen is 1e12-e13atom/cm2.Further, the injection number of the ion implanting can be primary, or
Repeatedly.
It can inhibit to be subsequently formed to a certain extent in the second ion implanted region that gate stack structure two sides are formed
Horizontal proliferation occurs for the impurity of LDD region, leads to Punchthrough and short-channel effect, while can inhibit the loss of impurity, that is, exists
In the case where the strong electrical field for not influencing drain electrode side, improve short-channel effect as far as possible.
Then, as shown in Figure 2 D, the two sides of the gate stack structure 202 formed cover the gate oxide 202a,
The side wall 205 of the side wall of grid 202b and grid conductive formation 202c, then in 201 surface of semiconductor substrate and side wall
Two sides formed oxide skin(coating) 206.
Wherein, the material of the side wall 205 includes nitride, such as silicon nitride, and effect is to reinforce source/drain and grid pile
Buffer action between stack structure.Illustratively, the material of the oxide skin(coating) 206 includes oxide, such as silica.The oxygen
The forming method of compound layer 205 is depositing operation, and depositing operation includes but is not limited to physical gas-phase deposition, chemical vapor deposition
The techniques such as product technique, rapid thermal nitridation process.
Then, as shown in Figure 2 E, the nitridation of the covering oxide skin(coating) 206 is formed on the surface of the oxide skin(coating) 206
Then nitride layer 207 etches the oxide skin(coating) 206 and the nitride layer 207 using side wall etching technics, until exposing source electrode one
First ion implanted region 203 of side and the second ion implanted region 204 of drain electrode side.
Remaining oxide skin(coating) 206 and nitride layer 207 constitute offset side wall together, and effect is the protection grid pile
Stack structure 202 is injury-free in subsequent lightly doped technique, and prevents in lightly doped technique due to PMOS short channel length
Reduction and a possibility that increase charge break-through between source and drain；The diffusion that the foreign ion of LDD region can additionally be inhibited, avoid by
The loss of impurity caused by the hydrogen bond of nitride layer surface, and then improve carrier mobility and mentioned so as to improve short-channel effect
High semiconductor devices yield and performance.
Wherein, the nitride layer 207 is silicon nitride (SiN).Further, the method for nitride layer is formed as deposition work
Skill.Depositing operation includes but is not limited to the works such as physical gas-phase deposition, chemical vapor deposition process, rapid thermal nitridation process
Skill.It is performed etching using isotropic dry method etch technology, dry method etch technology includes but is not limited to: reactive ion etching
(RIE), ion beam milling, plasma etching or laser cutting carry out.
Then, as shown in Figure 2 F, the semiconductor is served as a contrast using lightly doped technique (Lightly Doped Drain, LDD)
The region that 202 two sides of gate stack structure are closed in bottom 201 carries out ion implanting, with closing in semiconductor substrate 201
Lightly doped drain (LDD) ion implanted region (not shown) is formed in the region of the gate stack structure 202.It is described to be lightly doped
The injection depth of technique can greater than, equal to or be less than first ion implanted region 203 or second ion implanted region 204
Injection depth.Further, after completing the ion implanting, the device is annealed at a certain temperature, such as
Laser annealing to activate the foreign ion of LDD region, and eliminates defect.
Specifically, the ion implanting of the lightly doped technique is the ion implanting perpendicular to semiconductor substrate.The LDD note
The ionic type entered determines that in the present invention, the device of formation is PMOSFET according to by the electrical property of semiconductor devices to be formed
Device, the foreign ion of injection are boron or indium.Illustratively, the energy of the injected ion of the lightly doped technique is 5KeV-
12KeV, dosage are 5 × 1014atom/cm2To 2 × 1015atom/cm2.According to the concentration of required foreign ion, ion implanting
Technique can be completed with one or more steps.If the device formed is NMOSFET device, the impurity mixed in LDD injection technology
Ion is one of phosphorus, arsenic, antimony, bismuth or combination.
The offset side wall formed before can inhibit the diffusion of the foreign ion in LDD region, and then improve carrier mobility
Rate can also prevent from increasing source and drain due to the reduction of PMOS short channel length in LDD technique so as to improve short-channel effect
Between charge break-through a possibility that.
Then, as shown in Figure 2 G, side wall layer 208 is formed in the offset side wall two sides.The side wall layer 208 can protect
First ion implanted region 203, the second ion implanted region 204 and LDD region subsequent etching formed groove during not by
Etching.
Illustratively, the side wall layer is silica.Further, the method for forming side wall layer includes: in the semiconductor
The side wall layer of the deposition covering offset side wall, the first ion implanted region, the second ion implanted region and LDD region on substrate 201, so
It is performed etching afterwards using side wall etching technics, to expose first ion implanted region 203, the second ion implanted region 204 and LDD
Area.Depositing operation includes but is not limited to the works such as physical gas-phase deposition, chemical vapor deposition process, rapid thermal nitridation process
Skill.It is performed etching using isotropic dry method etch technology, dry method etch technology includes but is not limited to: reactive ion etching
(RIE), ion beam milling, plasma etching or laser cutting carry out.
Finally, as illustrated in figure 2h, the region that 201 two sides of semiconductor substrate will form p-type source-drain area performs etching, with
Laterally V-shaped groove 209 is formed in the semiconductor substrate 201.
It should be noted that the side wall layer 208 can be etched away during etching semiconductor substrate 201
A part, as illustrated in figure 2h.As shown, the bosom of V-structure is located at the lower section of the gate stack structure 202.Into one
Step, performed etching using wet-etching technology, illustratively, etching liquid include potassium hydroxide, nitric acid, tetramethylammonium hydroxide or
Person's acetic acid etc..
Then, source electrode and drain electrode can be formed by epitaxial growth Ge-Si (SiGe) layer in the groove 209 of the semiconductor substrate,
The source electrode and drain electrode is as heavy-doped source drain region.Wherein, the surface of the source electrode and drain electrode is higher than semiconductor substrate surface.This
Outside, suitable boron element (such as B or BF2) can also be adulterated, in germanium silicon to improve performance of semiconductor device.Further, described
Epitaxial growth method can also include annealing process.Further, the germanium silicon layer is embedded germanium silicon layer.Utilize the SiGe layer pair
The channel of PMOS applies stress, to improve the mobility of carrier.For NMOS, the material as source electrode and drain electrode is carbon
Silicon layer (SiC).
Relative to injecting carbon while LDD injects, it is this formed before LDD injection be only located at source electrode side
On the one hand first ion implanted region can inhibit the impurity of lightly doped drain (LDD) ion implanted region being subsequently formed to occur laterally
Diffusion, leads to Punchthrough and short-channel effect, while can inhibit the loss of impurity；On the other hand, since the first ion is infused
Enter area not formed in drain electrode side, so that the case carbon of drain electrode side is substantially reduced, thus can be to avoid in drain electrode side
The high tension apparatus as caused by hot carrier's effect occurs and burns failure, have in the first ion implanted region to short channel
The inhibiting effect of effect, but can bring between the negative effect of hot carrier's effect weighed simultaneously.And use inclination from
The inhibiting effect to short-channel effect can be enhanced in the first ion implanted region that sub- injection technology is formed.In addition, in gate stack
The second ion implanted region that structure two sides are formed can inhibit short-channel effect to a certain extent, not influence the side that drains
In the case where strong electrical field, short-channel effect is improved.
In conclusion according to the method for the present invention, is formed before LDD injection and to be located at gate stack structure wherein side
On the one hand first ion implanted region can inhibit the impurity for the LDD region being subsequently formed that short channel caused by horizontal proliferation occurs
Effect；On the other hand, can to avoid the component failure caused by hot carrier's effect, inhibit short-channel effect
Weighed between hot carrier's effect.
The present invention also provides a kind of semiconductor devices, as illustrated in figure 2h, comprising: semiconductor substrate 201；In the semiconductor
The gate stack structure 202 formed on substrate 201；The gate stack structure 202 is closed in the semiconductor substrate wherein
The first ion implanted region 203 that the region of side is formed；The gate stack structure is closed on in the semiconductor substrate 201
The LDD region (not shown) that the region of 202 two sides is formed.
Wherein, first ion implanted region 203 is formed in the source electrode side of the gate stack structure 202.Institute
The injection ion for stating the first ion implanted region includes carbon and nitrogen.The injection ion of the LDD region includes boron or indium.
As an example, the gate stack structure 202 includes gate oxide 202a, grid 202b and grid low resistance
Layer 202c, the gate oxide 202a cover the portion of upper surface of the semiconductor substrate 201, described in the grid 202b covering
The upper surface of gate oxide 202a, the grid conductive formation 202c cover the upper surface of the grid 202b.In the grid
The two sides of stacked structure 202 are formed with the side wall for covering the gate oxide 202a, grid 202b and grid conductive formation 202c
Side wall 205.
Further, the semiconductor devices further includes closing on the gate stack structure in the semiconductor substrate 201
The second ion implanted region 204 that 202 two side areas is formed.The injection ion of second ion implanted region 204 includes carbon.Institute
The implantation dosage for stating the second ion implanted region 204 is less than the implantation dosage of first ion implanted region 203.
The semiconductor devices further includes the semiconductor substrate 201 below the gate stack structure 202 of part
The ion implanted region 203 of middle formation, formed in the semiconductor substrate 201 of 202 two sides of gate stack structure it is inclined
The side wall layer 208 moving side wall, being formed in the offset side wall two sides, and described in 202 two sides of gate stack structure
The source electrode and drain electrode formed in semiconductor substrate 201.Wherein, the injection ion of the ion implanted region 203 includes carbon, described inclined
Moving side wall includes the oxide skin(coating) 206 and nitride layer 207 sequentially formed.
In conclusion semiconductor device according to the invention, in gate stack structure the first ion that wherein side is formed
On the one hand injection region can inhibit the impurity of LDD region that short-channel effect caused by horizontal proliferation occurs；It on the other hand, can be with
The component failure caused by hot carrier's effect is avoided, inhibiting between short-channel effect and hot carrier's effect
Weighed.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (17)
1. a kind of manufacturing method of semiconductor devices, which comprises the following steps:
Semiconductor substrate is provided, forms gate stack structure on the semiconductor substrate；
To closed in the semiconductor substrate gate stack structure wherein side region execute the first ion implantation technology,
To form the first ion implanted region；
LDD injection is executed to the region for closing on the gate stack structure two sides in the semiconductor substrate, to form LDD region.
2. the method according to claim 1, wherein first ion implanted region is in the gate stack knot
What the source electrode side of structure was formed.
3. the method according to claim 1, wherein first ion implantation technology includes favouring described half
The ion implantation technology of conductor substrate.
4. the method according to claim 1, wherein the injection ion of first ion implantation technology includes carbon
And nitrogen.
5. the method according to claim 1, wherein LDD injection includes perpendicular to the semiconductor substrate
Ion implantation technology is lightly doped.
6. the method according to claim 1, wherein the injection ion of LDD injection includes boron or indium.
7. the method according to claim 1, wherein after first ion implantation technology the step of,
Before the step of LDD injects, the method also includes to closing on the gate stack structure in the semiconductor substrate
Two side areas executes the second ion implantation technology, to form the second ion implanted region.
8. the method according to the description of claim 7 is characterized in that second ion implantation technology includes perpendicular to described half
The ion implantation technology of conductor substrate.
9. the method according to the description of claim 7 is characterized in that the injection ion of second ion implantation technology includes
Carbon.
10. the method according to the description of claim 7 is characterized in that the implantation dosage of second ion implantation technology is less than
The implantation dosage of first ion implantation technology.
11. a kind of semiconductor devices characterized by comprising
Semiconductor substrate；
Form gate stack structure on the semiconductor substrate；
Close in the semiconductor substrate the gate stack structure wherein side region formed the first ion implanted region；
With
The LDD region that the region of the gate stack structure two sides is formed is closed in the semiconductor substrate.
12. semiconductor devices according to claim 11, which is characterized in that first ion implanted region is in the grid
What the source electrode side of pole stacked structure was formed.
13. semiconductor devices according to claim 11, which is characterized in that the injection ion of first ion implanted region
Including carbon and nitrogen.
14. semiconductor devices according to claim 11, which is characterized in that the injection ion of the LDD region include boron or
Indium.
15. semiconductor devices according to claim 11, which is characterized in that the semiconductor devices further includes described half
The second ion implanted region that the two side areas of the gate stack structure is formed is closed in conductor substrate.
16. semiconductor devices according to claim 15, which is characterized in that the injection ion of second ion implanted region
Including carbon.
17. semiconductor devices according to claim 15, which is characterized in that the implantation dosage of second ion implanted region
Less than the implantation dosage of first ion implanted region.
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