CN106558491A - A kind of semiconductor devices and its manufacture method, electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method, electronic installation Download PDFInfo
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- CN106558491A CN106558491A CN201510623125.4A CN201510623125A CN106558491A CN 106558491 A CN106558491 A CN 106558491A CN 201510623125 A CN201510623125 A CN 201510623125A CN 106558491 A CN106558491 A CN 106558491A
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- Prior art keywords
- ldd
- semiconductor substrate
- ion
- injection
- side wall
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000009434 installation Methods 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 75
- 238000002347 injection Methods 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 48
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims description 58
- 239000000463 material Substances 0.000 claims description 27
- -1 phosphonium ion Chemical class 0.000 claims description 17
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910001449 indium ion Inorganic materials 0.000 claims description 8
- 230000000694 effects Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 45
- 229910052751 metal Inorganic materials 0.000 description 23
- 239000002184 metal Substances 0.000 description 21
- 239000000470 constituent Substances 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- OLBVUFHMDRJKTK-UHFFFAOYSA-N [N].[O] Chemical compound [N].[O] OLBVUFHMDRJKTK-UHFFFAOYSA-N 0.000 description 1
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 description 1
- DBOSVWZVMLOAEU-UHFFFAOYSA-N [O-2].[Hf+4].[La+3] Chemical compound [O-2].[Hf+4].[La+3] DBOSVWZVMLOAEU-UHFFFAOYSA-N 0.000 description 1
- YAIQCYZCSGLAAN-UHFFFAOYSA-N [Si+4].[O-2].[Al+3] Chemical compound [Si+4].[O-2].[Al+3] YAIQCYZCSGLAAN-UHFFFAOYSA-N 0.000 description 1
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- INIGCWGJTZDVRY-UHFFFAOYSA-N hafnium zirconium Chemical compound [Zr].[Hf] INIGCWGJTZDVRY-UHFFFAOYSA-N 0.000 description 1
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method, electronic installation, and methods described includes：Semiconductor substrate is provided, grid structure is formed on a semiconductor substrate；LDD injections and nitrogen injection are performed simultaneously, to form unactivated first LDD region in the semiconductor substrate；The offset side wall against grid structure is formed in the both sides of grid structure；The 2nd LDD injections and carbon injection are performed simultaneously, to form unactivated second LDD region in the semiconductor substrate；Side wall is formed in the outside of offset side wall, source/drain region is performed and is injected and anneal, to form source/drain region in the semiconductor substrate.According to the present invention it is possible to the step of saving enforcement bag-like region ion implanting, will not cause the fluctuation in gate depletion area.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its
Manufacture method, electronic installation.
Background technology
As semiconductor devices develops to high density and small size, Metal-oxide-semicondutor
(MOS) transistor is main driving force.Driving current and hot carrier in jection are MOS
Of paramount importance two parameters in transistor design.Traditional design by control gate dielectric layer,
Channel region, well region, the note of the doping shape, bag-shaped injection region and source/drain region in source drain extension area
Enter shape and heat budget etc. to obtain expected performance.
Perform bag-like region ion implanting purpose be to form bag-shaped injection region will be low below grid
Doping source drain junction is wrapped, and is led by drain induced barrier reduction (DIBL) so as to effectively restrain
The short-channel effect of cause.When implementing the bag-like region ion implanting, the incident direction of ion is injected
Certain angle is offset relative to the direction perpendicular with substrate, the angle is 45 degree to the maximum.
Now, grid both sides only have very thin oxide side walls to protect which, therefore, the note
Enter ion to enter in the grid.Due to into the injection ion pair grid in the grid
Interface charge between dielectric layer and grid plays certain compensating action, therefore, it is described bag-shaped
Area's ion implanting causes the fluctuation in gate depletion area, and this fluctuation effect transfers to cause semiconductor device again
The amplification of the mismatch characteristic of part threshold voltage, the final normal work for affecting semiconductor devices.
It is, therefore, desirable to provide a kind of method, to solve the above problems.
The content of the invention
For the deficiencies in the prior art, the present invention provides a kind of manufacture method of semiconductor devices,
Including：Semiconductor substrate is provided, grid structure is formed on the semiconductor substrate；Hold simultaneously
The first LDD of row injects and nitrogen injection, so that unactivated the is formed in the Semiconductor substrate
One LDD region；Formed against the skew side of the grid structure in the both sides of the grid structure
Wall；The 2nd LDD injections and carbon injection are performed simultaneously, to be formed in the Semiconductor substrate
Unactivated second LDD region；The offset side wall outside formed side wall, perform source/
Drain region is injected and is annealed, to form source/drain region in the Semiconductor substrate.
In one example, LDD injection be with the grid structure as mask,
The low-doped ion implanting carried out in the Semiconductor substrate, when the semiconductor devices is
During nmos pass transistor, the Doped ions of LDD injection be phosphonium ion or arsenic from
Son, when the semiconductor devices is PMOS transistor, what a LDD injected mixes
Heteroion is boron ion or indium ion.
In one example, the energy range of nitrogen injection is 0.5-20keV, ion implanting
Dosage be 1.0 × e14-1.0×e15cm-2, LDD injection and nitrogen injection enter
The relative direction with the perpendicular of the Semiconductor substrate of firing angle degree is spent in 0 degree -40.
In one example, the 2nd LDD injection be with the offset side wall as mask,
The low-doped ion implanting carried out in the Semiconductor substrate, when the semiconductor devices is
During nmos pass transistor, the Doped ions of the 2nd LDD injection be phosphonium ion or arsenic from
Son, when the semiconductor devices is PMOS transistor, what the 2nd LDD injected mixes
Heteroion is boron ion or indium ion.
In one example, the energy range of carbon injection is 0.5-20keV, ion implanting
Dosage be 1.0 × e14-1.0×e15cm-2, the 2nd LDD injection and carbon injection enter
The relative direction with the perpendicular of the Semiconductor substrate of firing angle degree is spent in 0 degree -40.
In one example, the processing step for forming the side wall includes：Serve as a contrast in the semiconductor
The spacer material layer for covering the grid structure and the offset side wall is formed on bottom；Using side wall
Etch process etches the spacer material layer, to form the side wall.
In one example, prior to or while the source/drain region injection is implemented, also include
The step of implementing pre-amorphous injection, to reduce short-channel effect, the pre-amorphous injection
Injection ion includes III race and V race's ion.
In one embodiment, the present invention also provides a kind of semiconductor of employing said method manufacture
Device.
In one embodiment, the present invention also provides a kind of electronic installation, the electronic installation bag
Include the semiconductor devices.
According to the present invention it is possible to the step of saving enforcement bag-like region ion implanting, will not cause grid
The fluctuation of pole depletion region.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 D are the step implemented according to the method for exemplary embodiment of the present one successively
The schematic cross sectional view of the rapid device for obtaining respectively；
Fig. 2 is the stream of the step of being implemented according to the method for exemplary embodiment of the present one successively
Cheng Tu.
Specific embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
Can be carried out without the need for one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, for some technical characteristics well known in the art are not described.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, so as to
Explain semiconductor devices proposed by the present invention and its manufacture method, electronic installation.Obviously, this
Bright execution is not limited to the specific details is familiar with by the technical staff of semiconductor applications.This
Bright preferred embodiment is described in detail as follows, but in addition to these detailed descriptions, the present invention is also
There can be other embodiment.
It should be appreciated that ought in this manual using term "comprising" and/or " including "
When, which indicates there is the feature, entirety, step, operation, element and/or component, but
Do not preclude the presence or addition of one or more other features, entirety, step, operation, element,
Component and/or combinations thereof.
[exemplary embodiment one]
Reference picture 1A- Fig. 1 D, illustrated therein is according to an exemplary embodiment of the present one side
The schematic cross sectional view of the device that the step of method is implemented successively obtains respectively.
First, as shown in Figure 1A, there is provided Semiconductor substrate 100, as an example, semiconductor
The constituent material of substrate 100 can be using unadulterated monocrystalline silicon, doped with the monocrystalline of impurity
Silicon, silicon-on-insulator (SOI) etc..In the present embodiment, Semiconductor substrate 100 is from single
Crystal silicon material is constituted.Isolation structure, the isolation structure are formed with Semiconductor substrate 100
Isolate (STI) structure or selective oxidation silicon (LOCOS) isolation structure for shallow trench, for letter
Change, it is illustrated that not shown in the isolation structure.
Next, implementing well region injection, well region is formed in Semiconductor substrate 100.For
For NMOS, the doping type of the well region is p-type；It is for PMOS, described
The doping type of well region is N-type.
Next, forming grid structure 103, as an example, grid on a semiconductor substrate 100
Pole structure 103 includes the gate dielectric 101 being laminated from bottom to top and gate material layers 102.
Gate dielectric 101 includes oxide skin(coating), such as silica (SiO2) layer.Grid material
Layer 102 includes polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxygen
One or more in compound layer and metal silicide layer, wherein, the constituent material of metal level can
Being tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride layer includes titanium nitride
(TiN) layer；Conductive metal oxide layer includes yttrium oxide (IrO2) layer；Metal silication
Nitride layer includes titanium silicide (TiSi) layer.The shape of gate dielectric 101 and gate material layers 102
Into any prior art that method can be familiar with using those skilled in the art, preferred chemistry gas
Phase sedimentation (CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition
(LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition
(PECVD)。
Then, as shown in Figure 1B, at the same perform a LDD injection and nitrogen injection, with
Unactivated first LDD region 104 is formed in Semiconductor substrate 100.
First LDD injections are with grid structure 103 as mask, in Semiconductor substrate 100
The low-doped ion implanting for carrying out, it is unactivated low-doped to be formed in Semiconductor substrate 100
Source/drain region 104.
When MOS transistor is nmos pass transistor, the Doped ions of LDD injections
Can be phosphonium ion or arsenic ion etc..When the Doped ions of LDD injections are phosphonium ion
When, the energy range of ion implanting is 1-20keV, and the dosage of ion implanting is
1.0×e14-1.0×e15cm-2.When the Doped ions of LDD injections are arsenic ion, ion
The energy range of injection is 2-35keV, and the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2。
When MOS transistor is PMOS transistor, the Doped ions of LDD injections
Can be boron ion or indium ion etc..When the Doped ions of LDD injections are boron ion
When, the energy range of ion implanting is 0.5-10keV, and the dosage of ion implanting is
1.0×e14-1.0×e15cm-2.When the Doped ions of LDD injections are indium ion, ion
The energy range of injection is 10-70keV, and the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2。
The energy range of nitrogen injection is 0.5-20keV, and the dosage of ion implanting is
1.0×e14-1.0×e15cm-2.First LDD inject and nitrogen injection incident angle with respect to partly lead
The direction of the perpendicular of body substrate 100 is spent in 0 degree -40.
Then, as shown in Figure 1 C, formed against grid structure in the both sides of grid structure 103
103 offset side wall 106.Offset side wall 106 is by oxide, nitride or the group of the two
Close and constitute, as an example, in the present embodiment, the constituent material of offset side wall 106 is oxidation
Thing.The technical process for forming offset side wall 106 is familiar with by those skilled in the art, and here is not
It is repeated here again.
Next, inject while performing the 2nd LDD injections and carbon, with Semiconductor substrate 100
It is middle to form unactivated second LDD region 105.
2nd LDD injections are with offset side wall 106 as mask, in Semiconductor substrate 100
The low-doped ion implanting for carrying out, it is unactivated low-doped to be formed in Semiconductor substrate 100
Source/drain region 105.
When MOS transistor is nmos pass transistor, the Doped ions of the 2nd LDD injections
Can be phosphonium ion or arsenic ion etc..When the Doped ions of the 2nd LDD injections are phosphonium ion
When, the energy range of ion implanting is 1-20keV, and the dosage of ion implanting is
1.0×e14-1.0×e15cm-2.When the Doped ions of the 2nd LDD injections are arsenic ion, ion
The energy range of injection is 2-35keV, and the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2。
When MOS transistor is PMOS transistor, the Doped ions of the 2nd LDD injections
Can be boron ion or indium ion etc..When the Doped ions of the 2nd LDD injections are boron ion
When, the energy range of ion implanting is 0.5-10keV, and the dosage of ion implanting is
1.0×e14-1.0×e15cm-2.When the Doped ions of the 2nd LDD injections are indium ion, ion
The energy range of injection is 10-70keV, and the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2。
The energy range of carbon injection is 0.5-20keV, and the dosage of ion implanting is
1.0×e14-1.0×e15cm-2.2nd LDD inject and carbon injection incident angle with respect to partly lead
The direction of the perpendicular of body substrate 100 is spent in 0 degree -40.
Then, as shown in figure ip, side wall 108 is formed in the outside of offset side wall 106.Make
For example, the processing step for forming side wall 108 includes：Formed on a semiconductor substrate 100 and covered
The spacer material layer of lid grid structure 103 and offset side wall 106, its constituent material can be nitrogen
SiClx；(blanket etch) technique etched side walling bed of material is etched using side wall, to form side
Wall 108.
Next, perform source/drain region and inject and anneal, to be formed in Semiconductor substrate 100
Source/drain region 107, and activate previously formed unactivated first LDD region 104 and the 2nd LDD
Area 105.In order to reduce heat budget, the annealing can move to hold during subsequent implementation stress memory
OK.Prior to or while source/drain region injection is implemented, alternatively, implement pre-amorphous injection,
To reduce short-channel effect, the injection ion of the pre-amorphous injection includes III race such as germanium, carbon
With V race's ion.
So far, complete the technique step that according to an exemplary embodiment of the present one method is implemented
Suddenly.According to the present invention it is possible to the step of saving enforcement bag-like region ion implanting, will not cause grid
The fluctuation of pole depletion region.
With reference to Fig. 2, illustrated therein is according to an exemplary embodiment of the present one method it is real successively
The flow chart of the step of applying, for schematically illustrating the flow process of manufacturing process.
In step 201, there is provided Semiconductor substrate, grid structure is formed on a semiconductor substrate；
In step 202., while performing LDD injections and nitrogen injection, with semiconductor
Unactivated first LDD region is formed in substrate；
In step 203, formed against the skew side of grid structure in the both sides of grid structure
Wall；
In step 204, while performing the 2nd LDD injections and carbon injection, with semiconductor
Unactivated second LDD region is formed in substrate；
In step 205, side wall is formed in the outside of offset side wall, perform source/drain region injection
And anneal, to form source/drain region in the semiconductor substrate.
[exemplary embodiment two]
Next, the making of whole semiconductor devices can be completed by subsequent technique, including：
Self-aligned silicide is formed at the top of source/drain region；Interlayer is formed on a semiconductor substrate 100
Dielectric layer, and the contact hole for exposing self-aligned silicide is formed in interlayer dielectric layer, in contact
Contact plug is formed in hole；Form multiple interconnecting metal layers, generally using dual damascene process come
Complete；Form metal pad, wire bonding when encapsulating for subsequent implementation device.
For with the semiconductor devices compared with decimal value node, after forming interlayer dielectric layer
Before the contact hole of self-aligned silicide is exposed in formation in interlayer dielectric layer, grid structure is removed
103, high k- metal gate structures are formed in the groove for being formed.As an example, the high k-
Boundary layer that metal gate structure includes being laminated from bottom to top, high k dielectric layer, coating, resistance
Barrier, workfunction setting metal layer, soakage layer and metal gate material layer.The composition of boundary layer
Material include thermal oxide, nitrogen oxides, chemical oxide etc. can by chemical vapor deposition,
The suitable material that handling process is formed in ald or stove, thickness are 5 angstroms -10 angstroms,
The effect for forming boundary layer be improve the high k dielectric layer that is subsequently formed and Semiconductor substrate 100 it
Between interfacial characteristics.The k values (dielectric constant) of high k dielectric layer are usually more than 3.9, its
Constituent material include hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, hafnium oxide tantalum, hafnium oxide zirconium,
Nitrogen oxidation hafnium zirconium, hafnium oxide lanthanum, lanthana, lanthana silicon, zirconium oxide, zirconium silicon oxide, oxygen
Change titanium, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminum oxide, aluminum oxide
Silicon, silicon nitride, oxynitride etc. can pass through chemical vapor deposition, ald or thing
The suitable material that physical vapor deposition technique is formed, thickness are 10 angstroms -30 angstroms.The structure of coating
Include lanthana, aluminum oxide, gallium oxide, indium oxide, molybdenum oxide ramet, oxygen nitrogen into material
Ramet, tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, platinum, ruthenium, iridium etc. can pass through
The suitable thing that chemical vapor deposition, ald or physical gas-phase deposition are formed
Matter, thickness are 5 angstroms -20 angstroms.The material on barrier layer includes tantalum nitride, forms the work on barrier layer
With being to prevent expansion of the metal material in the metal gate structure that is subsequently formed to high k dielectric layer
Dissipate.For PMOS, workfunction setting metal layer includes one or more layers metal or gold
Category compound, its constituent material is the metal material suitable for PMOS, including titanium, ruthenium,
Palladium, platinum, tungsten and its alloy, carbide, nitride also including above-mentioned metallic element etc. are thick
Spend for 10 angstroms -580 angstroms；For NMOS, workfunction setting metal layer include one layer or
Multiple layer metal or metallic compound, its constituent material are the metal material suitable for NMOS,
Including titanium, tantalum, aluminium, zirconium, hafnium and its alloy, carbide also including above-mentioned metallic element,
Nitride etc., thickness are 10 angstroms -80 angstroms.The material of soakage layer includes titanium or titanium-aluminium alloy, shape
Effect into soakage layer improves between workfunction setting metal layer and metal gate material layer
Interfacial characteristics.The material of metal gate material layer includes that tungsten, aluminium etc. can pass through chemical vapor deposition
The suitable material that product, ald or physical gas-phase deposition are formed.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, and which includes according to an exemplary embodiment of the present two
Method manufacture semiconductor devices.The electronic installation can be mobile phone, panel computer, pen
Remember this computer, net book, game machine, television set, VCD, DVD, navigator, photograph
Any electronic product such as machine, video camera, recording pen, MP3, MP4, PSP or equipment,
Can be any intermediate products including the semiconductor devices.The electronic installation, due to making
With the semiconductor devices, thus there is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office
It is limited to above-described embodiment, teaching of the invention can also be made more kinds of modifications and repair
Change, within these variants and modifications all fall within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (9)
1. a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided, grid structure is formed on the semiconductor substrate；
LDD injections and nitrogen injection are performed simultaneously, to be formed in the Semiconductor substrate
Unactivated first LDD region；
The offset side wall against the grid structure is formed in the both sides of the grid structure；
The 2nd LDD injections and carbon injection are performed simultaneously, to be formed in the Semiconductor substrate
Unactivated second LDD region；
Side wall is formed in the outside of the offset side wall, source/drain region is performed and is injected and anneal, with
Source/drain region is formed in the Semiconductor substrate.
2. method according to claim 1, it is characterised in that the LDD notes
It is the low-mix heteroion carried out in the Semiconductor substrate with the grid structure as mask to enter
Injection, when the semiconductor devices is nmos pass transistor, the LDD injections
Doped ions are phosphonium ion or arsenic ion, when the semiconductor devices is PMOS transistor
When, the Doped ions of the LDD injections are boron ion or indium ion.
3. method according to claim 1, it is characterised in that the energy of the nitrogen injection
Amount scope is 0.5-20keV, and the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2, described
The relative surface with the Semiconductor substrate of incident angle that one LDD injects and the nitrogen injects
Perpendicular direction is spent in 0 degree -40.
4. method according to claim 1, it is characterised in that the 2nd LDD notes
It is the low-mix heteroion carried out in the Semiconductor substrate with the offset side wall as mask to enter
Injection, when the semiconductor devices is nmos pass transistor, the 2nd LDD injections
Doped ions are phosphonium ion or arsenic ion, when the semiconductor devices is PMOS transistor
When, the Doped ions of the 2nd LDD injections are boron ion or indium ion.
5. method according to claim 1, it is characterised in that the energy of the carbon injection
Amount scope is 0.5-20keV, and the dosage of ion implanting is 1.0 × e14-1.0×e15cm-2, described
The relative surface with the Semiconductor substrate of incident angle that two LDD inject and the carbon injects
Perpendicular direction is spent in 0 degree -40.
6. method according to claim 1, it is characterised in that form the side wall
Processing step includes：Formed on the semiconductor substrate cover the grid structure and it is described partially
Move the spacer material layer of side wall；The spacer material layer is etched using side wall etch process, with shape
Into the side wall.
7. method according to claim 1, it is characterised in that implement the source/
It is prior to or while the injection of drain region, also including the step of enforcement pre-amorphous injection, short to reduce
Channelling effect, the injection ion of the pre-amorphous injection include III race and V race's ion.
8. the semiconductor devices that the method described in a kind of one of employing claim 1-7 is manufactured.
9. a kind of electronic installation, the electronic installation include the semiconductor described in claim 8
Device.
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| CN109427887A (en) * | 2017-08-29 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method and semiconductor devices of semiconductor devices |
| US11855183B2 (en) | 2020-08-28 | 2023-12-26 | Changxin Memory Technologies, Inc. | Method for manufacturing semiconductor device |
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