CN102569394B - Transistor and manufacture method thereof - Google Patents

Transistor and manufacture method thereof Download PDF

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Publication number
CN102569394B
CN102569394B CN201010612652.2A CN201010612652A CN102569394B CN 102569394 B CN102569394 B CN 102569394B CN 201010612652 A CN201010612652 A CN 201010612652A CN 102569394 B CN102569394 B CN 102569394B
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semiconductor layer
layer
semiconductor substrate
crystal orientation
gate structure
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CN102569394A (en
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三重野文健
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Semiconductor Manufacturing International Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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Abstract

The invention provides a transistor and a manufacture method thereof. The manufacture method comprises providing a semiconductor substrate where a semiconductor layer is formed, crystal orientation of the semiconductor layer is different from that of the semiconductor substrate, and a fake grid electrode structure is formed on the semiconductor layer. A source region and a drain region are formed in the semiconductor substrate and the semiconductor layer on two sides of the fake grid electrode structure, an interlamination medium layer flushed with the fake grid electrode structure is formed on the semiconductor layer, the fake grid electrode structure is removed, an opening is formed in the interlamination medium layer, and the semiconductor layer on the lower portion is exposed out of the opening. A decrystallizatoin step is carried out on the semiconductor layer exposed out from the opening, and a channel layer is formed. Annealing is carried out on the channel layer to enable the crystal orientation of the channel layer to be same with that of the semiconductor substrate. A metal grid electrode structure is formed in the opening and located above the channel layer. Saturation current of the transistor is improved, and performance of devices is improved.

Description

Transistor and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors, particularly transistor and preparation method thereof.
Background technology
Strain memory technique (Stress Memorization Technique, be called for short SMT) and stress etching barrier layer technology (Stressd-CESL, contact etch stop layer) be two kinds of technology of existing raising transistor carrier mobility.By above-mentioned two kinds of technology, in transistorized channel region, form stable stress, improve the carrier mobility in raceway groove.Described stress is parallel to orientation, can be for extending stress or compression stress.Conventionally tensile stress can be so that the atomic arrangement in channel region be more loose, thereby improves the mobility of electronics, is applicable to nmos pass transistor; And compression stress makes the Atomic Arrangement in channel region tightr, contribute to improve the mobility in hole, be applicable to PMOS transistor.
Please refer to Fig. 1～Fig. 3, is the transistorized manufacture method cross-sectional view of prior art.
First, with reference to figure 1, provide Semiconductor substrate 10, in described Semiconductor substrate 10, be formed with nmos pass transistor and PMOS transistor, between described nmos pass transistor and PMOS transistor, there is isolation structure 11.Described nmos pass transistor comprises P trap (not shown), is formed at the nmos pass transistor source/drain region 12 in P trap, the nmos pass transistor grid 13 in Semiconductor substrate between source/drain region 12; Described PMOS transistor comprises: N trap (not shown), be formed at the transistorized source/drain region 14 of PMOS, the transistorized grid 15 of the PMOS between source/drain region 14 in N trap.
Then, with reference to figure 2, in the stressor layers 16 of described nmos pass transistor and the formation of PMOS transistor surface covering source/drain region 12, grid 13 and Semiconductor substrate 10, the material of described stressor layers 16 can be silicon nitride.Described stressor layers 16 can provide tensile stress or compression.Suppose that described stressor layers 16 provides tensile stress, pair nmos transistor produces beneficial effect.
Then, with reference to figure 3, use mask layer to carry out etching, remove the stressor layers 16 on PMOS transistor surface, retain the stressor layers 16 that is positioned at nmos pass transistor surface.Then, anneal, make the stressor layers 16 on nmos pass transistor surface bring out tensile stress, described tensile stress is retained in nmos pass transistor, has improved the mobility of nmos pass transistor channel region charge carrier (being electronics).After annealing, conventionally carry out the stressor layers 16 that etching technics is removed the grid 13, source/drain region 12 and the Semiconductor substrate 10 that are positioned at nmos pass transistor.
In the Chinese patent application that is CN101393894A at publication number, can find more manufacture methods about existing MOS transistor.
But, to find in practice, the transistorized saturation current value of utilizing existing method to form is on the low side, affects the performance of device.
Summary of the invention
The problem that the present invention solves has been to provide a kind of transistor and preparation method thereof, and described method has improved transistorized saturation current, has improved the performance of device.
For addressing the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with semiconductor layer, the crystal orientation of described semiconductor layer is different from the crystal orientation of described Semiconductor substrate;
On described semiconductor layer, form dummy gate structure;
In the Semiconductor substrate of described dummy gate structure both sides and semiconductor layer, form source region and drain region;
On described semiconductor layer, form the interlayer dielectric layer flushing with described dummy gate structure;
Remove described dummy gate structure, in described interlayer dielectric layer, form opening, described opening exposes the semiconductor layer of below;
The semiconductor layer that described opening is exposed carries out decrystallized step, forms channel layer;
Described channel layer is annealed, make the crystal orientation of described channel layer identical with the crystal orientation of described Semiconductor substrate;
In described opening, form metal gate structure, described metal gate structure is positioned at described channel layer top.
Alternatively, described transistor is nmos pass transistor, and the crystal orientation of described Semiconductor substrate is (100), and the crystal orientation of described semiconductor layer is (110).
Alternatively, described transistor is PMOS transistor, and the crystal orientation of described Semiconductor substrate is (110), and the crystal orientation of described semiconductor layer is (100).
Alternatively, the thickness of described semiconductor layer is 3～30 nanometers.
Alternatively, described decrystallized step utilizes ion implantation technology to carry out, and the doping ion of described ion implantation technology is silicon ion, germanium ion or carbon ion.
Alternatively, the energy range of described Si ion implantation is 2～30KeV, and angle of inclination is 0～15 degree, and dosage is 9E14～3E15cm-2; The energy range of described Ge+ implantation is 5～40KeV, and angle of inclination is 0～20 degree, and dosage is 1E15～4E15cm -2; The energy range that described carbon ion injects is 1～10KeV, and angle of inclination is 0～15 degree, and dosage range is 1E12～5E12 -2.
Alternatively, the temperature range of described annealing is 550～750 degrees Celsius, and the gas that described annealing utilizes is inert gas, nitrogen or both mixing.
Alternatively, also comprise:
Carry out light dope Implantation, form the step of light doping section in described Semiconductor substrate and semiconductor layer, described light doping section is positioned at described grid structure both sides.
Alternatively, the angle of described light dope Implantation is 15～40 degree.
Alternatively, the making of described metal gate structure comprises:
High K dielectric layer is formed on sidewall and bottom at described opening;
On described high K dielectric layer, make metal gates, described metal gates and high K dielectric layer form metal gate structure.
Alternatively, the material of described high K dielectric layer is: hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide.
Alternatively, also comprise: in the interlayer dielectric layer of described opening both sides, make the step of metal gates side wall, the position of described metal gates side wall is corresponding with the position in described source region and drain region.
Alternatively, the material of described metal gates side wall is one or more in silica, silicon nitride, silicon oxynitride or silicon nitride, and the thickness of described metal gates side wall is no more than 20 nanometers.
Correspondingly, the present invention also provides a kind of transistor, comprising:
Semiconductor substrate, is formed with semiconductor layer in described Semiconductor substrate, and the crystal orientation of described semiconductor layer is different from the crystal orientation of described Semiconductor substrate;
Interlayer dielectric layer, is positioned on described semiconductor layer;
Opening, is positioned at described interlayer dielectric layer, and described opening exposes the semiconductor layer of below;
Metal gate structure, is positioned at described opening, and described metal gate structure covers described semiconductor layer;
Source region, is positioned at semiconductor layer and the Semiconductor substrate of described metal gate structure one side;
Drain region, is positioned at semiconductor layer and the Semiconductor substrate of described metal gate structure opposite side;
Channel layer, in the semiconductor layer between described source region and drain region, and described channel layer flushes with described semiconductor layer, and the crystal orientation of described channel layer is identical with the crystal orientation of described Semiconductor substrate, and the position of described channel layer is corresponding with the position of described opening.
Alternatively, described transistor is nmos pass transistor, and the crystal orientation of described Semiconductor substrate is (100), and the crystal orientation of described semiconductor layer is (110).
Alternatively, described transistor is PMOS transistor, and the crystal orientation of described Semiconductor substrate is (110), and the crystal orientation of described semiconductor layer is (100).
Alternatively, the thickness of described semiconductor layer is 3～30 nanometers.
Alternatively, also comprise:
Light doping section, is positioned at described Semiconductor substrate and semiconductor layer, and described light doping section is positioned at described metal gate structure and channel layer both sides.
Alternatively, have doping ion in described channel layer, described doping ion is silicon ion, germanium ion or carbon ion.
Alternatively, described metal gate structure comprises:
High K dielectric layer, is positioned at sidewall and the bottom of described opening;
Metal gates, is positioned on described high K dielectric layer, and described metal gates and described high K dielectric layer form metal gate structure.
Alternatively, the material of described high K dielectric layer is hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide.
Alternatively, also comprise: metal gates side wall, be located in the interlayer dielectric layer of described opening both sides, described metal gates side wall is corresponding with the position of described source region, drain region and channel layer.
Alternatively, the material of described metal gates side wall is one or more in silica, silicon nitride, silicon oxynitride or silicon nitride, and the thickness of described metal gates side wall is no more than 20 nanometers.
Compared with prior art, the present invention has the following advantages:
First the present invention forms the semiconductor layer with described Semiconductor substrate with different crystal orientations in Semiconductor substrate, on described semiconductor layer, make dummy gate structure, then, in the Semiconductor substrate of described dummy gate structure both sides and semiconductor layer, form source region and drain region; Then remove described dummy gate structure, in interlayer dielectric layer, form the opening of exposed portions serve semiconductor layer; Then described semiconductor layer is carried out to step decrystallized and annealing, in the semiconductor layer exposing, form channel layer at described opening, described channel layer is as the channel region between described source region and drain region.Because described semiconductor layer is different from the crystal orientation of described Semiconductor substrate, thereby in channel region, produce stress, this stress has improved the mobility of the charge carrier in source region and drain region, thereby has improved transistorized drain saturation current, has improved the performance of semiconductor device; Because described channel layer is identical with the crystal orientation of described Semiconductor substrate, thereby prevented the problem that the carrier mobility speed of the channel regions that cause different from the crystal orientation of described Semiconductor substrate, the crystal orientation of described channel layer declines;
Further optimally, in the interlayer dielectric layer of described opening both sides, make the step of metal gates side wall, the position of described metal gates side wall is corresponding with the position in described source region and drain region, not only protected the metal gate structure of follow-up formation, and prevent the short-channel effect in described source region and drain region, reduce the leakage current causing due to Distance Shortened between described source region and drain region;
Further optimally, the thickness of described metal gates side wall is no more than 20 nanometers, thereby preventing that the thickness of described metal gates side wall is excessive causes transistorized area excessive, thereby is conducive to reduce transistorized area.
Accompanying drawing explanation
Fig. 1～Fig. 3 is the preparation method of transistor cross-sectional view of prior art;
Fig. 4 is preparation method of transistor schematic flow sheet of the present invention;
Fig. 5～Figure 11 is preparation method of transistor cross-sectional view of the present invention.
Embodiment
The transistorized saturation current value that existing method forms is on the low side, affects the performance of device.Through inventor, study discovery, causing described transistorized saturation current value reason on the low side is that the mobility of transistorized charge carrier is on the low side, cannot meet actual requirement, has affected the performance of device.And, along with dwindling of transistor feature size, existing transistorized feature size downsizing to 45 nanometer range, the thickness of gate dielectric layer reduces, Distance Shortened between source region and drain region, thus make the leakage problem of existence in described transistor also comparatively serious.
Inventor, through creative work, proposes a kind of transistorized manufacture method, please refer to the preparation method of transistor schematic flow sheet of the present invention shown in Fig. 4.Described method comprises:
Step S1, provides Semiconductor substrate, in described Semiconductor substrate, is formed with semiconductor layer, and the crystal orientation of described semiconductor layer is different from the crystal orientation of described Semiconductor substrate;
Step S2 forms dummy gate structure on described semiconductor layer;
Step S3 forms source region and drain region in the Semiconductor substrate of described dummy gate structure both sides and semiconductor layer;
Step S4 forms the interlayer dielectric layer flushing with described dummy gate structure on described semiconductor layer;
Step S5, removes described dummy gate structure, in described interlayer dielectric layer, forms opening, and described opening exposes the semiconductor layer of below;
Step S6, the semiconductor layer that described opening is exposed carries out decrystallized step, forms channel layer;
Step S7, anneals to described channel layer, makes the crystal orientation of described channel layer identical with the crystal orientation of described Semiconductor substrate;
Step S8 forms metal gate structure in described opening, and described metal gate structure is positioned at described channel layer top.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.For technical scheme of the present invention is described better, please refer to the preparation method of transistor cross-sectional view of the one embodiment of the invention shown in Fig. 5～Figure 11.
First, please refer to Fig. 5, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, be formed with semiconductor layer 101, the crystal orientation of described semiconductor layer 101 is different from the crystal orientation of described Semiconductor substrate 100.
Because the crystal orientation of described semiconductor layer 101 is different from the crystal orientation of described Semiconductor substrate 100, thereby produce stress between described semiconductor layer 101 and described Semiconductor substrate 100.There is relation in the crystal orientation of the crystal orientation of the type of described stress and described semiconductor layer 101 and described Semiconductor substrate 100.
Particularly, when the crystal orientation of described Semiconductor substrate 100 is (100), when the crystal orientation of described semiconductor layer 101 is (110), the stress producing between described Semiconductor substrate 100 and described semiconductor layer 101 is tension stress, this tension stress can improve the mobility of electronics, thereby is of value to the saturation current value that improves nmos pass transistor; When the crystal orientation of described Semiconductor substrate 100 is (110), when the crystal orientation of described semiconductor layer 101 is (100), the stress producing between described Semiconductor substrate 100 and described semiconductor layer 101 is compression, this compression can improve the mobility in hole, thereby be of value to, improves the transistorized saturation current value of PMOS.
If produce enough stress, described semiconductor layer 101 need to meet certain thickness, and the thickness of described semiconductor layer 101 need to be greater than 3 nanometers; But the thickness of described semiconductor layer 101 should be not excessive yet, to prevent forming satisfactory transistor, the thickness of described semiconductor layer 101 should be less than 32 nanometers.In above-mentioned thickness range, can produce enough stress, effectively improve the mobility of charge carrier, can not affect transistorized performance simultaneously.
Then, please refer to Fig. 6, on described semiconductor layer 101, form gate dielectric layer 102, on described gate dielectric layer 102, form dummy grid 103.Described dummy grid 103 and the common formation dummy gate structure of gate dielectric layer 102.
The material of described gate dielectric layer 102 is electrical insulation material, and described electrical insulation material is preferably silica or silicon oxynitride.The thickness range of described gate dielectric layer 102 is 3～80 dusts.Described gate dielectric layer 102 preferably utilizes oxidation technology to make.
The material of described dummy grid 103 is polysilicon.Described polysilicon can utilize chemical vapor deposition method to make.Described chemical vapor deposition method is same as the prior art, and the known technology as those skilled in the art, is not described in detail at this.
Then, please refer to Fig. 7, carry out light dope Implantation, Semiconductor substrate 100 and the interior formation of semiconductor layer 101 light doping section 108 in described dummy grid 103 and gate dielectric layer 102 both sides.
As preferred embodiment, range of tilt angles 14～40 degree of described light dope Implantation, the type of the doping ion of described light dope Implantation should be carried out concrete selection according to the transistorized type that will form, known technology as those skilled in the art, is not described in detail at this.
Then, please refer to Fig. 8, on the surface of the semiconductor layer 101 of described dummy grid 103 and gate dielectric layer 102 both sides, form dummy grid side wall 104, the silica that the material of described dummy grid side wall 104 is individual layer or silicon nitride layer; The ONO structure that the material of described dummy grid side wall 104 can also form for the silicon oxide layer-silicon nitride-silicon oxide layer of multilayer.The manufacture method of described dummy grid side wall 104 is same as the prior art, and the known technology as those skilled in the art, is not described in detail at this.
Because described dummy grid side wall 104 is using the source/leakage ion implantation mask as follow-up formation source region and drain region, concrete setting should be carried out according to the source region that will form and drain region in the position of described dummy grid side wall 104, and the thickness of described dummy grid side wall 104 is unsuitable excessive, otherwise may make the source region of follow-up formation and the distance in drain region excessive, make transistorized area excessive.Because described dummy grid side wall 104 finally will be removed, and the position at described dummy grid side wall 104 forms metal gates side wall, the thickness of this metal gates side wall is no more than 20 nanometers, as preferred embodiment, the thickness of described dummy grid side wall 104 should equal the thickness of the described metal gates side wall of follow-up formation, therefore, the thickness of described dummy grid side wall 104 is no more than 20 nanometers.
Then, please continue to refer to Fig. 8, the described dummy grid side wall 104 of take is mask, carry out source/leakage Implantation, in described Semiconductor substrate 100 and 105He drain region, the interior formation of semiconductor layer 101 source region 106,105He drain region, described source region 106 lays respectively at described dummy grid 103 and gate dielectric layer 102 both sides, and the position in 105He drain region, described source region 106 is corresponding with the position of described dummy grid side wall 104.Described source/leakage Implantation is same as the prior art, and the known technology as those skilled in the art, is not described in detail at this.
Then, please refer to Fig. 9, on described semiconductor layer 101, form the interlayer dielectric layer 107 flushing with described dummy grid 103 and dummy grid side wall 104.Described interlayer dielectric layer 107 covers described source region 105,106He light doping section, drain region 108.
The material of described interlayer dielectric layer 107 is electrical insulation material, and for example described interlayer dielectric layer 107 can be silica, silicon nitride, carborundum or silicon oxynitride.Described interlayer dielectric layer 107 can utilize chemical vapor deposition method to make.
Then, please refer to Figure 10, carry out etching technics, remove described dummy grid 103 (with reference to figure 9), gate dielectric layer 102 (with reference to figure 9), at the interior formation opening of described interlayer dielectric layer 107, described opening exposes the part semiconductor layer 101 between described light doping section 108.Described opening is for making metal gate structure at follow-up processing step.
Because described etching technics may cause dummy grid side wall 104 (with reference to the figure 9) damage that is positioned at dummy grid 103 and gate dielectric layer 102 both sides, thereby may cause the metal gate structure leakage current of follow-up formation.Therefore, as the preferred embodiments of the present invention, also need to carry out etching technics, remove the dummy grid side wall 104 (with reference to figure 9) that is positioned at described dummy grid 103 and gate dielectric layer 102 both sides, the part light doping section between 105He drain region, described source region 106 108 is exposed.
Then, please continue to refer to Figure 10, between described light doping section 108, part semiconductor layer carries out decrystallized step, forms described in channel layer 109 channel layer 109 as transistorized channel region between described light doping section 109.
Described decrystallized employing Implantation forms, and the doping ion of described Implantation is silicon ion, germanium ion or carbon ion.The energy range of described Si ion implantation is 2～30KeV, and angle of inclination is 0～15 degree, and dosage is 9E14～3E15cm-2; The energy range of described Ge+ implantation is 5～40KeV, and angle of inclination is 0～20 degree, and dosage is 1E15～4E15cm -2; The energy range that described carbon ion injects is 1～10KeV, and angle of inclination is 0～15 degree, and dosage range is 1E12～5E12 -2.
Ion implantation technology through described crystallization, the crystal orientation of the semiconductor layer between light doping section 108 is destroyed, thereby the crystal orientation of the channel layer 109 forming is mixed and disorderly, follow-uply can, by readjusting the crystal orientation of described channel layer 109 in annealing steps, make the crystal orientation of described channel layer 109 consistent with the crystal orientation of described Semiconductor substrate 100.
Then, annealed in described channel region 109, arranged again in the crystal orientation of described channel layer 109, thereby the crystal orientation of described channel layer 109 is consistent with the crystal orientation of described Semiconductor substrate 100.As the preferred embodiments of the present invention, need to carry out preferably the parameter of described annealing, so that the crystal orientation of described channel layer 109 is consistent with the crystal orientation of described Semiconductor substrate 100.As an embodiment, the temperature range of described annealing is 550～850 degrees Celsius; The mist that the gas that described annealing utilizes is inert gas or nitrogen or inert gas and nitrogen.Wherein said inert gas can be one or more in argon gas, helium, xenon.
Through described annealing steps, the crystal orientation of described channel region 109 is consistent with the crystal orientation of Semiconductor substrate 100, thereby prevents the crystal orientation of channel region 109 and the crystal orientation of described Semiconductor substrate 100 is inconsistent, the migration rate of the charge carrier that affects described channel region.
Then, please refer to Figure 11, on the sidewall of the opening of described interlayer dielectric layer 107, make metal gates side wall 110, the material of described metal gates side wall 110 is silica, silicon nitride, carborundum or silicon oxynitride.The thickness of described metal gates side wall 110 should be no more than 20 nanometers, to be conducive to reduce transistorized area.The position of described metal gates side wall 110 replaces the position of original dummy grid side wall, thereby the position of described metal gates side wall 110 is corresponding with the position in 105He drain region, described source region 106.
Then, sidewall and bottom at the opening of described interlayer dielectric layer 107 make high K dielectric layer 111, and the material of described high K dielectric layer 111 can be hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide etc.The high K dielectric layer 111 that is wherein positioned at described open bottom is covered in the surface of described epitaxial loayer 109.
Because described high K dielectric layer 111 is positioned at sidewall and the bottom of described opening, thus the bottom that is only formed on opening with the high K dielectric layer of prior art compare, the present invention has reduced transistorized leakage current.
Then, continue with reference to Figure 11, make metal gates 112 in described opening, described metal gates 112 flushes with described interlayer dielectric layer 107, metal gates side wall 1110, high K dielectric layer 111 and metal gates 112.Described metal gates 112 and the common formation metal gate structure of described high K dielectric layer 111.
The transistor forming through above-mentioned processing step, please refer to shown in Figure 11, and described transistor comprises:
Semiconductor substrate 100, is formed with semiconductor layer 101 in described Semiconductor substrate 100, and the crystal orientation of described semiconductor layer 101 is different from the crystal orientation of described Semiconductor substrate 100;
Interlayer dielectric layer 107, is positioned on described semiconductor layer 101;
Opening, is positioned at described interlayer dielectric layer 107, and described opening exposes the semiconductor layer 101 of below;
Metal gate structure, be positioned at described opening, described metal gate structure comprises high K dielectric layer 111 and the metal gates 112 that is positioned at described opening, and wherein said high K dielectric layer 111 is positioned at sidewall and the bottom of described opening, and described metal gates 112 fills up described opening;
Metal gates side wall 110, be positioned at the sidewall of described opening, and between described metal gate structure and described interlayer dielectric layer 107, the thickness of described metal gates side wall 110 is no more than 20 nanometers, excessive to prevent the excessive transistorized area causing of thickness of metal gates side wall 110;
Source region 105, is positioned at semiconductor layer 101 and the Semiconductor substrate 100 of described metal gate structure one side, and the position in described source region 105 is corresponding with the position of described metal gates side wall 110;
Drain region 106, is positioned at semiconductor layer 101 and the Semiconductor substrate 100 of described metal gate structure opposite side, and the position in described drain region 106 is corresponding with the position of described metal gates side wall 110;
Light doping section 108, is positioned at described Semiconductor substrate 100 and semiconductor layer 101, and described light doping section 108 is positioned at described metal gate structure both sides;
Channel layer 109, the position of described channel layer 109 is corresponding with the position of described opening and metal gate structure, the width of described channel layer equals the width of described metal gate structure, described channel layer 109 is in the Semiconductor substrate 100 between described light doping section 108, described channel layer 109 flushes with described semiconductor layer 101, the crystal orientation of described channel layer 109 is identical with the crystal orientation of described Semiconductor substrate 100, described channel layer 109 is as transistorized channel region, in described channel layer 109, have doping ion, described doping ion is germanium ion or silicon ion.
The material of described high K dielectric layer 111 can be hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide, because high K dielectric layer 111 has all been formed on the sidewall at described opening and bottom, thereby prevented transistorized leakage problem.
It should be noted that, concrete setting need to be carried out according to described transistorized type in the crystal orientation of the crystal orientation of described semiconductor layer 100 and Semiconductor substrate 100, when described transistor is nmos pass transistor, the crystal orientation of described Semiconductor substrate 100 is (100), the crystal orientation of described semiconductor layer 101 is (110), the stress producing between described Semiconductor substrate 100 and semiconductor layer 101 is tension stress, thereby be conducive to improve the migration rate of electronics, be conducive to increase the saturation current of nmos pass transistor; When described transistor is PMOS transistor, the crystal orientation of described Semiconductor substrate 100 is (110), and the crystal orientation of described semiconductor layer 101 is (100), thereby is conducive to improve the migration rate in hole, is conducive to increase the transistorized saturation current of PMOS.
If produce enough stress, described semiconductor layer 101 need to meet certain thickness, and the thickness of described semiconductor layer 101 need to be greater than 3 nanometers; But the thickness of described semiconductor layer 101 should be not excessive yet, to prevent forming satisfactory transistor, the thickness of described semiconductor layer 101 should be less than 32 nanometers.In above-mentioned thickness range, can produce enough stress, effectively improve the mobility of charge carrier, can not affect transistorized performance simultaneously.As one embodiment of the present of invention, the thickness of described semiconductor layer is 3～30 nanometers.
To sum up, invention provides a kind of transistor and preparation method thereof, first described method forms the semiconductor layer with described Semiconductor substrate with different crystal orientations in Semiconductor substrate, on described semiconductor layer, make dummy gate structure, then, in the Semiconductor substrate of described dummy gate structure both sides and semiconductor layer, form source region and drain region; Then remove described dummy gate structure, in interlayer dielectric layer, form the opening of exposed portions serve semiconductor layer; Then described semiconductor layer is carried out to step decrystallized and annealing, in the semiconductor layer exposing, form channel layer at described opening, described channel layer is as the channel region between described source region and drain region.Because described semiconductor layer is different from the crystal orientation of described Semiconductor substrate, thereby in channel region, produce stress, this stress has improved the mobility of the charge carrier in source region and drain region, thereby has improved transistorized drain saturation current, has improved the performance of semiconductor device; Because described channel layer is identical with the crystal orientation of described Semiconductor substrate, thereby prevented the problem that the carrier mobility speed of the channel regions that cause different from the crystal orientation of described Semiconductor substrate, the crystal orientation of described channel layer declines.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (23)

1. a transistorized manufacture method, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with semiconductor layer, the crystal orientation of described semiconductor layer is different from the crystal orientation of described Semiconductor substrate, between described semiconductor layer and Semiconductor substrate, produces stress;
On described semiconductor layer, form dummy gate structure;
In the Semiconductor substrate of described dummy gate structure both sides and semiconductor layer, form source region and drain region;
On described semiconductor layer, form the interlayer dielectric layer flushing with described dummy gate structure;
Remove described dummy gate structure, in described interlayer dielectric layer, form opening, described opening exposes the semiconductor layer of below;
The semiconductor layer that described opening is exposed carries out decrystallized step, and the crystal orientation of described semiconductor layer is destroyed, forms channel layer, and the crystal orientation of described channel layer is mixed and disorderly;
Described channel layer is annealed, make the crystal orientation of described channel layer identical with the crystal orientation of described Semiconductor substrate;
In described opening, form metal gate structure, described metal gate structure is positioned at described channel layer top.
2. transistorized manufacture method as claimed in claim 1, is characterized in that, described transistor is nmos pass transistor, and the crystal orientation of described Semiconductor substrate is (100), and the crystal orientation of described semiconductor layer is (110).
3. transistorized manufacture method as claimed in claim 1, is characterized in that, described transistor is PMOS transistor, and the crystal orientation of described Semiconductor substrate is (110), and the crystal orientation of described semiconductor layer is (100).
4. transistorized manufacture method as claimed in claim 1, is characterized in that, the thickness of described semiconductor layer is 3～30 nanometers.
5. transistorized manufacture method as claimed in claim 1, is characterized in that, described decrystallized step utilizes ion implantation technology to carry out, and the doping ion of described ion implantation technology is silicon ion, germanium ion or carbon ion.
6. transistorized manufacture method as claimed in claim 5, is characterized in that, the energy range of described Si ion implantation is 2～30KeV, and angle of inclination is 0～15 degree, and dosage is 9E14～3E15cm -2; The energy range of described Ge+ implantation is 5～40KeV, and angle of inclination is 0～20 degree, and dosage is 1E15～4E15cm -2; The energy range that described carbon ion injects is 1～10KeV, and angle of inclination is 0～15 degree, and dosage range is 1E12～5E12 -2.
7. transistorized manufacture method as claimed in claim 1, is characterized in that, the temperature range of described annealing is 550～750 degrees Celsius, and the gas that described annealing utilizes is inert gas, nitrogen or both mixing.
8. transistorized manufacture method as claimed in claim 1, is characterized in that, also comprises:
Carry out light dope Implantation, form the step of light doping section in described Semiconductor substrate and semiconductor layer, described light doping section is positioned at described grid structure both sides.
9. transistorized manufacture method as claimed in claim 8, is characterized in that, the angle of described light dope Implantation is 15～40 degree.
10. transistorized manufacture method as claimed in claim 1, is characterized in that, the making of described metal gate structure comprises:
High K dielectric layer is formed on sidewall and bottom at described opening;
On described high K dielectric layer, make metal gates, described metal gates and high K dielectric layer form metal gate structure.
11. transistorized manufacture methods as claimed in claim 10, it is characterized in that, the material of described high K dielectric layer is: hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide.
12. transistorized manufacture methods as claimed in claim 1, is characterized in that, also comprise: in the interlayer dielectric layer of described opening both sides, make the step of metal gates side wall, the position of described metal gates side wall is corresponding with the position in described source region and drain region.
13. transistorized manufacture methods as claimed in claim 12, is characterized in that, the material of described metal gates side wall is one or more in silica, silicon nitride, silicon oxynitride or silicon nitride, and the thickness of described metal gates side wall is no more than 20 nanometers.
14. 1 kinds of transistors, is characterized in that, comprising:
Semiconductor substrate, is formed with semiconductor layer in described Semiconductor substrate, and the crystal orientation of described semiconductor layer is different from the crystal orientation of described Semiconductor substrate, between described semiconductor layer and Semiconductor substrate, produces stress;
Interlayer dielectric layer, is positioned on described semiconductor layer;
Opening, is positioned at described interlayer dielectric layer, and described opening exposes the semiconductor layer of below;
Metal gate structure, is positioned at described opening, and described metal gate structure covers described semiconductor layer;
Source region, is positioned at semiconductor layer and the Semiconductor substrate of described metal gate structure one side;
Drain region, is positioned at semiconductor layer and the Semiconductor substrate of described metal gate structure opposite side;
Channel layer, in the semiconductor layer between described source region and drain region, and described channel layer flushes with described semiconductor layer, and the crystal orientation of described channel layer is identical with the crystal orientation of described Semiconductor substrate, and the position of described channel layer is corresponding with the position of described opening.
15. transistors as claimed in claim 14, is characterized in that, described transistor is nmos pass transistor, and the crystal orientation of described Semiconductor substrate is (100), and the crystal orientation of described semiconductor layer is (110).
16. transistors as claimed in claim 14, is characterized in that, described transistor is PMOS transistor, and the crystal orientation of described Semiconductor substrate is (110), and the crystal orientation of described semiconductor layer is (100).
17. transistors as claimed in claim 14, is characterized in that, the thickness of described semiconductor layer is 3～30 nanometers.
18. transistors as claimed in claim 14, is characterized in that, also comprise:
Light doping section, is positioned at described Semiconductor substrate and semiconductor layer, and described light doping section is positioned at described metal gate structure and channel layer both sides.
19. transistors as claimed in claim 14, is characterized in that, have doping ion in described channel layer, and described doping ion is silicon ion, germanium ion or carbon ion.
20. transistors as claimed in claim 14, is characterized in that, described metal gate structure comprises:
High K dielectric layer, is positioned at sidewall and the bottom of described opening;
Metal gates, is positioned on described high K dielectric layer, and described metal gates and described high K dielectric layer form metal gate structure.
21. transistors as claimed in claim 20, is characterized in that, the material of described high K dielectric layer is hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide.
22. transistors as claimed in claim 14, is characterized in that, also comprise: metal gates side wall, be located in the interlayer dielectric layer of described opening both sides, and described metal gates side wall is corresponding with the position of described source region, drain region and channel layer.
23. transistors as claimed in claim 22, is characterized in that, the material of described metal gates side wall is one or more in silica, silicon nitride, silicon oxynitride or silicon nitride, and the thickness of described metal gates side wall is no more than 20 nanometers.
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