CN112018038B - Preparation method of semiconductor device - Google Patents
Preparation method of semiconductor device Download PDFInfo
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- CN112018038B CN112018038B CN202011159377.3A CN202011159377A CN112018038B CN 112018038 B CN112018038 B CN 112018038B CN 202011159377 A CN202011159377 A CN 202011159377A CN 112018038 B CN112018038 B CN 112018038B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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Abstract
The invention discloses a preparation method of a semiconductor device, which at least comprises the following steps: defining a medium-voltage element area and a low-voltage element area on a substrate; respectively forming a first grid oxide layer and a second grid oxide layer in a medium voltage element area and a low voltage element area on the substrate; forming a first grid on the first grid oxide layer, forming a second grid on the second grid oxide layer, forming a first side wall on the side wall of the first grid, and forming a second side wall on the side wall of the second grid; performing first ion implantation on two sides of the second grid electrode in the substrate to form a first ion implantation area; performing second ion implantation in the first ion implantation area to form a second ion implantation area; and carrying out third ion implantation in the first ion implantation area to form a source/drain area. The invention solves the problems of complex process and high cost in the preparation process of the semiconductor device integrated by the low-voltage element and the medium-voltage element.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a semiconductor device.
Background
With the process of semiconductor device steadily stabilized, in the conventional process, low voltage device and medium voltage device are usually integrated to manufacture semiconductor device, such as 1.5V-5V logic power source, including 1.5V Low Voltage Lightly Doped Drain (LVLDD) process and 5V Medium Voltage Lightly Doped Drain (MVLDD) process. The Lightly Doped Drain (LDD) process is a low energy and low concentration ion implantation process for implanting lighter ions of the same type as source and drain (S/D) ions into the drain region of the MOSFET. The purpose is to reduce the electric field intensity in the drain region of the MOSFET, thereby improving the reliability problems such as hot carrier injection (HOT CARRIER INJECTION). This process has been used on a large scale to date in the basic structure of integrated circuit metal-oxide semiconductor field effect transistors. However, with the increasing competitive pressure in the semiconductor mid/low end market, most customers select a mature process (e.g., 110 nm) and require the product to be low cost without affecting the device characteristics. As such, it is very important to omit the medium voltage ldd process step in the process flow, but in the logic power supply integrated with the low voltage device and the medium voltage device, if the medium voltage ldd process step is directly omitted, the subsequent source/drain ion implantation process will affect the characteristics of the low voltage device, which may cause the channel penetration (punch through) of the low voltage device.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which solves the problems of complex process and high cost in the preparation process of the semiconductor device integrating a low-voltage element and a medium-voltage element.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a preparation method of a semiconductor device, which at least comprises the following steps:
providing a substrate;
defining a medium-voltage element area and a low-voltage element area on the substrate;
forming a first gate oxide layer and a second gate oxide layer on the medium-voltage element region and the low-voltage element region, respectively;
forming a first grid electrode on the first grid electrode oxidation layer, and forming a second grid electrode on the second grid electrode oxidation layer;
forming a first side wall on the side wall of the first grid electrode, and forming a second side wall on the side wall of the second grid electrode;
performing first ion implantation in the substrate on two sides of the second grid to form a first ion implantation area;
performing second ion implantation on the substrate corresponding to the position of the first ion implantation area to form a second ion implantation area;
and respectively carrying out third-time ion implantation on the substrate at two sides of the first grid and the second grid to form a source region and a drain region, wherein the second ion implantation region is respectively positioned at the vertical lower boundaries of the source region and the drain region, and the polarity of the second ion implantation region is opposite to that of the corresponding source region and drain region.
In one embodiment of the present invention, the implantation direction of the second ion implantation is a direction perpendicular to the substrate.
In an embodiment of the invention, the first ion implantation direction and the substrate form an inclined angle therebetween.
In one embodiment of the present invention, the energy of the second ion implantation is obtained by the following formula:
E=λ*E0*cosδ0
wherein E is the energy of the second ion implantation; λ is the relation between the implantation depth and the energy of the second ion implantation; e0The energy of the third ion implantation; delta0Is the angle of the third ion implantation.
In one embodiment of the present invention, the concentration D of the second ion implantation is the concentration D of the third ion implantation01/3-1.
In one embodiment of the present invention, the angle between the direction of the third ion implantation and the substrate is less than 90 °.
In an embodiment of the present invention, a depth of the second ion implantation region near the vertical center line is greater than a depth of the second ion implantation region near the two side boundary lines.
In one embodiment of the present invention, the manufacturing method further includes performing well implantation on the medium-voltage element region and the low-voltage element region before forming the first gate oxide layer and the second gate oxide layer.
In an embodiment of the invention, at least one side boundary of each of the second ion implantation regions is located below the second side wall.
In an embodiment of the invention, the preparation method further includes performing ion implantation on the first ion implantation region before the second ion implantation to form a blocking region, and a polarity of the blocking region is opposite to a polarity of the source region and the drain region.
In an embodiment of the invention, the manufacturing method further includes implanting ions with a polarity opposite to that of the source region and the drain region into a region below the second sidewall structure and the second gate structure at a certain inclination angle, so as to form a blocking region with a polarity opposite to that of the source region and the drain region.
The invention saves the process step of medium-pressure lightly doped drain in the preparation process of the semiconductor device integrated by the low-voltage device and the medium-voltage device, thereby reducing the manufacturing cost of the semiconductor device and simplifying the preparation flow. In addition, an additional ion implantation step is added after the low-voltage lightly doped drain process step, so that the influence caused by source/drain ion implantation after the medium-voltage lightly doped drain process step is eliminated.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a method flow diagram of a method of fabricating a semiconductor device in accordance with the present invention;
FIG. 2 is a schematic structural diagram of the step S1 and the step S2 in FIG. 1;
FIG. 3 is a schematic structural diagram of the step S3 and the step S4 in FIG. 1;
FIG. 4 is a schematic structural diagram corresponding to step S5 in FIG. 1;
FIG. 5 is a schematic structural diagram corresponding to step S6 in FIG. 1;
fig. 6 to 8 are schematic structural views of fig. 1 corresponding to step S7 and step S8;
fig. 9 is an enlarged view of a partial region of fig. 8.
Reference numerals
A medium voltage element region 10; a low-voltage element region 20; a substrate 100; a first gate oxide layer 107; a second gate oxide layer 108; a first gate electrode 109; a second gate electrode 110; a first side wall 111; a second side wall 112; a first ion implantation region 113; a blocking region 114; a second ion implantation region 115; a source region 116; a drain region 117; the isolation structure 200.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With the steady progress of semiconductor device manufacturing processes, especially 110nm device manufacturing processes, in the conventional process, low voltage device and medium voltage device devices are usually integrated to manufacture semiconductor devices, such as 1.5V-5V logic power, which includes 1.5V Low Voltage Lightly Doped Drain (LVLDD) and 5V Medium Voltage Lightly Doped Drain (MVLDD). However, as the semiconductor mid/low end market competition pressure increases, most customers select a mature process and require the product to be reduced in cost without affecting the device characteristics. As such, it is very important to omit the medium voltage ldd process step in the process flow, but in the logic power supply integrated with the low voltage device and the medium voltage device, if the medium voltage ldd process step is directly omitted, the subsequent source/drain ion implantation process will affect the characteristics of the low voltage device, which may cause the channel penetration (punch through) of the low voltage device.
Referring to fig. 1, the present invention takes an nmos fabrication process as an example, and provides a method for fabricating a semiconductor device, which at least includes the following steps:
s1, providing a substrate 100;
s2, defining a medium-voltage element area 10 and a low-voltage element area 20 on the substrate 100;
s3, forming a first grid oxide layer 107 and a second grid oxide layer 108 in the areas corresponding to the medium-voltage element area 10 and the low-voltage element area 20 on the substrate 100 respectively;
s4, forming a first grid electrode 109 on the first grid electrode oxidation layer 107, and forming a second grid electrode 110 on the second grid electrode oxidation layer 108;
s5, forming a first side wall 111 on the side wall of the first grid 109, and forming a second side wall 112 on the side wall of the second grid 110;
s6, performing first ion implantation on two sides of the second grid 110 in the substrate 100 to form a first ion implantation area 113;
s7, performing secondary ion implantation on the substrate at a position vertical to the first ion implantation area 113 to form a second ion implantation area 115;
and S8, performing third ion implantation on two sides of the first gate 109 and the second gate 110 in the substrate 100 to form a source region 116 and a drain region 117, wherein the second ion implantation region 115 is located at the vertical lower boundary of the source region 116 and the drain region 117, and the depth of the second ion implantation region 115 close to the vertical center line is greater than the depth of the second ion implantation region 115 close to the boundary lines at two sides. The polarity of the second ion implantation region 115 is opposite to the polarity of the corresponding source region 116 and drain region 117.
Referring to fig. 2, in step S1, a substrate 100 is first provided, the material of the substrate 100 may include, but is not limited to, single crystal or polycrystalline semiconductor material, and the substrate 100 may also include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, which may be a P-type substrate or an N-type substrate, and in this embodiment, only the first doping type is a P-type substrate, that is, in this embodiment, the substrate 100 only exemplifies a P-type substrate 100, for example, a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal Silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a Silicon On Insulator (SOI), or any combination thereof, and a suitable semiconductor material may be selected as the substrate 100 according to the actual requirements of the device, which is not limited herein. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.
Referring to fig. 2, in step S2, a medium voltage device area 10 and a low voltage device area 20 are defined on the substrate 100, for example, a 1.5V-5V logic power supply is taken as an example in the present embodiment, the voltage corresponding to the medium voltage device area 10 is, for example, 5V, and the voltage corresponding to the low voltage device area 20 is, for example, 1.5V. The substrate 100 may include a plurality of medium voltage device regions 10 and a plurality of low voltage device regions 20, and adjacent regions may be isolated from each other by an isolation structure 200. One end of each isolation structure 200 is located in the substrate 100, and the top surface of the isolation structure 200 is higher than the surface of the substrate 100. In some embodiments, the substrate 100 may further include a plurality of isolation structures 200, the plurality of isolation structures 200 divides the semiconductor device into a plurality of units, and the plurality of units may be distributed in parallel at intervals, or may be arbitrarily arranged according to the semiconductor structure. In this embodiment, the adjacent isolation structures 200 and the substrate 100 region therebetween form a medium voltage device region 10 or a low voltage device region 20. In the present embodiment, the isolation structure 200 is, for example, a shallow trench isolation structure 200, the isolation structure 200 is an inverted trapezoid, and since the isolation structure 200 is an inverted trapezoid structure and one end of the isolation structure is located in the substrate 100, an inclined sidewall is formed at a joint of the substrate 100 and the isolation structure 200, the isolation structure 200 may be made of, for example, silicon oxide, silicon nitride or silicon oxynitride, and a width of the isolation structure 200 may be set according to design requirements of the semiconductor structure. In addition, only one medium voltage element region 10 and low voltage element region 20 are shown in the drawings, but it should be understood by those skilled in the art that the structure of the semiconductor device is shown in the drawings only in a schematic form in order to clearly express the core idea of the present application, but this does not represent that the semiconductor device related to the present invention only includes these parts, and the well-known structure and process steps of the semiconductor device can also be included therein.
Referring to fig. 2, in one embodiment of the present invention, the following process steps, but not limited to, may be considered to have been completed on the substrate 100: well implants, such as P-well implants or N-well implants, are performed on the substrate 100 corresponding to the medium-voltage element region 10 and the low-voltage element region 20, and the ion implantation source is preferably a phosphorus source, a boron source, or a fluorine source. In this embodiment, the medium voltage device region 10 and the low voltage device region 20 are sequentially subjected to deep N-well implantation, P-well implantation, and shallow P-well implantation at the same time.
Referring to fig. 3, in step S3, a first gate oxide layer 107 and a second gate oxide layer 108 are formed on the substrate 100 in the areas corresponding to the medium voltage device area 10 and the low voltage device area, respectively. Specifically, a first gate oxide layer 107 and a second gate oxide layer 108 are respectively formed at corresponding positions of the medium voltage device region 10 and the low voltage device region 20 on the substrate 100, the oxide layers cover the surface of the substrate 100, and the oxide layers may be made of, for example, silicon oxide.
Referring to fig. 3, in step S4, a first gate 109 is formed on the first gate oxide layer 107, and a second gate 110 is formed on the second gate oxide layer 108. The first gate 109 and the second gate 110 cover the first gate oxide layer 107 and the second gate oxide layer 108, respectively, and the first gate 109 and the second gate 110 may be made of doped polysilicon, or polysilicon may be deposited in an undoped form and implanted thereafter to form doped polysilicon. In other embodiments, other suitable conductive materials may be used in place of doped polysilicon. In this embodiment, polysilicon may be deposited on the surfaces of the first gate oxide layer 107 and the second gate oxide layer 108 by, for example, chemical vapor deposition, the thickness of the polysilicon layer is the standard thickness in the industry, and is not limited herein, and then the deposited polysilicon layer is processed by planarization treatment, such as obtaining the polysilicon layer with a flat surface by chemical mechanical polishing, etching downwards along the two sides of the polysilicon layer and the oxide layer under the shielding of the photoresist, wherein the etching method can adopt dry etching or wet etching, and is not limited, the first gate 109 and the second gate 110 as shown in fig. 3 are obtained by etching, in this embodiment, the first gate 109 and the second gate 110 and the corresponding first gate oxide layer 107 and the second gate oxide layer 108 are located above the shallow well implantation region on the substrate 100.
Referring to fig. 4, in step S5, a first sidewall 111 is formed on a sidewall of the first gate 109, and a second sidewall 112 is formed on a sidewall of the second gate 110. In this embodiment, the first side wall 111 and the second side wall 112 include an ON side wall structure and an ONO side wall structure, the ON side wall structure covers the side walls of the first gate 109 and the second gate 110, the ONO side wall structure covers the side walls of the ON side wall structure, the ON side wall structure includes a silicon oxide layer and a silicon nitride layer, and the ONO side wall structure includes a silicon oxide layer, a silicon nitride layer and a silicon oxide layer. Specifically, the method for forming the first sidewall 111 and the second sidewall 112 includes the following steps: an ON layer (oxide-nitride) is first formed ON the surfaces of the first gate 109 and the second gate 110, and the ON layer covers the surfaces of the first gate 109 and the second gate 110. In this embodiment, the ON layer includes a silicon oxide layer and a silicon nitride layer sequentially formed ON the surfaces of the first gate 109 and the second gate 110, where the silicon oxide layer may be, for example, silicon oxynitride or silicon dioxide. Specifically, a silicon oxide layer covers the surfaces of the first gate 109 and the second gate 110, including the sidewalls and the exposed surface of the substrate 100, and a silicon nitride layer is formed overlying the surface of the silicon oxide layer. The ON layer may be formed, for example, using a chemical vapor deposition process. In this embodiment, the thickness of each layer of the ON layer may be set by using an existing process, and the thickness of each layer may be a conventional thickness. An ONO layer (oxide-nitride-oxide) may be formed ON the surface of the ON layer in the above manner, the ONO layer covering the surface of the ON layer. And etching the ONO layer and the ON layer by a dry etching method or a wet etching method to obtain an ON side wall structure and an ONO side wall structure. Specifically, in this embodiment, for example, a wet etching process may be used to etch the ONO layer and the ON layer downward in a direction perpendicular to the substrate 100, so as to remove the top portions of the first gate 109 and the second gate 110 and the ONO layer and the ON layer ON the substrate 100, thereby exposing the top surfaces of the first gate 109 and the second gate 110 and the substrate 100 ON two sides of the first gate 109 and the second gate 110, and obtaining the first sidewall 111 and the second sidewall 112 covering the sidewalls of the first gate 109 and the second gate 110. Because the wet etching process belongs to anisotropic etching, two sides of the side wall structure form an inclined angle. The side wall structure can avoid short channel effect caused by the fact that a subsequent source/drain electrode is too close to the grid electrode, and meanwhile, the side wall of the grid electrode is protected. The first sidewall 111 structure and the second sidewall 112 structure of the present invention are used in conjunction with the subsequent first ion implantation and the source/drain implantation, because the first ion implantation and the source/drain implantation are performed in the exposed region of the substrate 100, and because of the sidewall structure, the ion implantation can be performed at a certain angle and selectively at the back of the ON sidewall structure or the back of the ONO sidewall structure, thereby controlling the positions of the first ion implantation and the source/drain implantation under the polysilicon layer, for example, the subsequent first ion implantation process will use an oblique angle to implant ions under the second sidewall 112 structure and the polysilicon layer boundary.
Referring to fig. 5, in step S6, a first ion implantation with a first conductivity type 113 is performed in the substrate 100 at an inclined angle on two sides of the second gate 110, where the first ion implantation is a lightly doped drain implantation, and in this embodiment, the first ion implantation refers to an ion implantation process of implanting a light low-energy and low-concentration ion of the same type as that of the source and drain between the vicinity of the boundary below the polysilicon layer and the source and drain regions. The ion implantation source used for the first ion implantation is preferably a phosphorus source, a boron source or a fluorine source.
Referring to fig. 6 and 9, in step S7, the first ion implantation region 113 is ion implanted to form a blocking region 114, wherein the polarity of the blocking region 114 is opposite to the polarity of the source/ drain regions 116, 117. Specifically, an ion type with a polarity opposite to that of the source region 116/the drain region 117 is implanted into the region at the boundary between the second sidewall 112 structure and the polysilicon layer in the substrate 100 at a certain inclination angle, so as to form a blocking region 114. The blocking region 114 may be located at the boundary of the first ion implantation region 113 and below the second sidewall 112, the blocking region 114 may also traverse the first ion implantation region 113, and a portion of the blocking region 114 is located below the second sidewall 112, the blocking region 114 forms an oblique angle with the horizontal direction, so that the blocking region 114 is formed in the low voltage device region because when a positive voltage is applied to the gate, the source is connected to 0V, and the drain is connected to a positive voltage, electrons are attracted, a channel, also called a channel, is formed between the source and the drain, and the width of the channel depends on the width of the gate, because the width of the gate in the low voltage device region is short, a channel penetration phenomenon is easily generated, that is, when the working condition is not reached, the channel forms a path, which is not allowed, and therefore, by designing the blocking region 114, the difficulty of forming the channel can be increased, therefore, the channel penetration phenomenon can be prevented.
Referring to fig. 7 to 9, in steps S7 and S8, a second ion implantation is performed in the first ion implantation region 113 to form a second ion implantation region 115. The implantation direction of the second ion implantation is a direction perpendicular to the substrate 100, and the implantation angle δ =0 °. Performing third ion implantation on two sides of the first gate 109 and the second gate 110 in the substrate 100, respectively, forming a source region 116/a drain region 117 in a medium voltage element region 10 and a low voltage element region 20, where an included angle between a direction of the third ion implantation and the substrate 100 is less than 90 °, the second ion implantation region 115 in the low voltage element region 20 is located in the source region 116/the drain region 117, the second ion implantation region 115 may be located at any position in the source region 116/the drain region 117, a polarity of the source region 116/the drain region 117 is P-type or N-type, and a polarity of the second ion implantation region 115 is opposite to a polarity of the source region 116/the drain region 117. The depth of the second ion implantation region 115 near the vertical center line of the region is greater than the depth of the second ion implantation region 115 near the boundary lines at both sides of the region. At least one side boundary of each of the second ion implantation regions 115 is located below the second sidewall 112.
Empirically, let the conditions of the source/drain ion implantation be: the energy of the source/drain ion implantation is E0Angle of source/drain ion implantation is delta0Concentration of source/drain ion implantation is D0Then, the energy of the second ion implantation can be obtained by the following formula:
E=λ*E0*cosδ0
wherein E is the energy of the second ion implantation; and lambda is the relation between the implantation depth and the energy of the second ion implantation.
The concentration D of the second ion implantation is the concentration D of the third ion implantation01/3-1. For example, the concentration of the second ion implantation can be obtained by the following formula:
D=1/4D0
in this embodiment, E is, for example, 80Kev to 120Kev, and D is, for example, E +12 to E + 13.
Referring to fig. 7 and 8, for the second ion implantation, the following is explained from a theoretical point of view:
when the process flow of the LDD of the medium voltage device region 10 is omitted, an appropriate angle delta is usually adopted during the source/drain implantation0The implantation is performed to replace the lightly doped drain process of the medium voltage device region 10, and multiple implantations may be selected to achieve a normal performance of the medium voltage device region 10 by adding appropriate energy and concentration so as not to affect the normal source/drain implantation. As shown in FIG. 9, in the present embodiment, taking medium voltage NMOS as an example, the medium voltage device region is omitted during the manufacturing processAfter the process of lightly doping the drain region 10, delta is used0For example, four times of source/drain implantation is performed at 45 °, and the product performance of the medium-voltage N-type metal-oxide-semiconductor device can reach a normal level under other appropriate conditions. The second ion implantation is added to the LDD process of the low voltage device region 20 in order to eliminate the vertical component effect of the subsequent source/drain implantation, so that in this embodiment, a second ion implantation process with an angle δ =0 and opposite polarity to the source/drain is added to the LDD process of the low voltage device region 20.
Referring to fig. 1 to 8, the present invention saves two masks based on the prior art, shortens the process time, and adds a second ion implantation process to the lightly doped process of the low voltage device region 20 after the process flow of lightly doping the drain of the medium voltage device region 10 is omitted, and because the second ion implantation process can be synchronously completed in the lightly doped process of the low voltage device region 20, the present invention saves the process steps compared with the prior art, reduces the cost, and increases the difficulty of forming the current path through the second ion implantation region 115, thereby avoiding the occurrence of the channel penetration phenomenon, and ensuring the performance of the medium voltage device and the low voltage device after the process flow of lightly doping the medium voltage device region 10 is omitted. In addition, the size of the effective channel length of the medium-voltage element can be reduced, for example, the effective channel length can be reduced to 10% -20% of the original size, so that the design density of the customer element during design layout can be greatly improved, meanwhile, the leakage current of the low-voltage element can be improved, and the market competitiveness can be improved.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above disclosure of selected embodiments of the invention is intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A method for manufacturing a semiconductor device, comprising at least the steps of:
providing a substrate;
defining a medium-voltage element area and a low-voltage element area on the substrate;
forming a first gate oxide layer and a second gate oxide layer on the medium-voltage element region and the low-voltage element region, respectively;
forming a first grid electrode on the first grid electrode oxidation layer, and forming a second grid electrode on the second grid electrode oxidation layer;
forming a first side wall on the side wall of the first grid electrode, and forming a second side wall on the side wall of the second grid electrode;
performing first ion implantation of an inclined angle in the substrate on two sides of the second grid electrode to form a first ion implantation area;
performing second ion implantation on the substrate corresponding to the position of the first ion implantation area to form a second ion implantation area, wherein the implantation direction of the second ion implantation is a direction vertical to the substrate;
and respectively carrying out third-time ion implantation on the substrate at two sides of the first grid and the second grid to form a source region and a drain region, wherein the first-time ion implantation is a process of implanting light ions which are the same as the source region and the drain region and are implanted between the vicinity of a boundary below the second grid and the source region and the drain region, the second ion implantation region is positioned at the vertical lower boundary of the source region and the drain region, and the polarity of the second ion implantation region is opposite to that of the corresponding source region and the corresponding drain region.
2. The method according to claim 1, wherein the energy of the second ion implantation is obtained by the following formula:
E=λ*E0*cosδ0
wherein E is the energy of the second ion implantation; λ is the relation between the implantation depth and the energy of the second ion implantation; e0The energy of the third ion implantation; delta0Is the angle of the third ion implantation.
3. The method according to claim 1, wherein the concentration D of the second ion implantation is the concentration D of the third ion implantation01/3-1.
4. The method according to claim 1, wherein an angle between the direction of the third ion implantation and the substrate is less than 90 °.
5. The method for manufacturing a semiconductor device according to claim 1, wherein a depth of the second ion implantation region near a vertical center line of the region is greater than a depth of the second ion implantation region near boundary lines on both sides of the region.
6. A method for manufacturing a semiconductor device according to claim 1, further comprising performing well implantation on the medium-voltage element region and the low-voltage element region before forming the first gate oxide layer and the second gate oxide layer.
7. The method according to claim 1, wherein a side boundary of the second ion implantation region is located below the second sidewall.
8. The method of claim 1, further comprising performing ion implantation on the first ion implantation region before the second ion implantation to form a blocking region, wherein the polarity of the blocking region is opposite to the polarity of the source region and the drain region.
9. The method according to claim 8, further comprising implanting ions having a polarity opposite to that of the source region and the drain region into the region under the second sidewall and the second gate at a certain inclination angle to form a blocking region having a polarity opposite to that of the source region and the drain region.
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