CN113555362A - CMOS device and process method - Google Patents

CMOS device and process method Download PDF

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Publication number
CN113555362A
CN113555362A CN202110862336.9A CN202110862336A CN113555362A CN 113555362 A CN113555362 A CN 113555362A CN 202110862336 A CN202110862336 A CN 202110862336A CN 113555362 A CN113555362 A CN 113555362A
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well
trap
layer
region
cmos device
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蔡莹
金锋
陈峻
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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Abstract

The invention discloses a CMOS device, which is provided with a first well and a second well which are mutually abutted in a substrate, wherein the first well comprises a source region and a drain region of an MOS device; a gate dielectric layer and a gate electrode positioned above the gate dielectric layer are arranged on the surface of the substrate between the LDD regions in the first trap; in the second well, a source region and a drain region of the MOS device are contained; the source region and the drain region are respectively positioned in the LDD region; a gate dielectric layer and a gate electrode positioned above the gate dielectric layer are arranged on the surface of the substrate between the LDD regions in the second trap; and both sides of the grid electrode on the first trap and both sides of the grid electrode on the second trap comprise side walls formed by compounding two layers of dielectric layers. According to the invention, on the premise of not changing PMOS characteristics, LDD injection is carried out on the basis of forming the side walls step by step, so that the distance between the heavily doped region of the source drain end of the NMOS device and a channel is increased, the grid edge electric field of the NMOS close to the drain end is effectively reduced, and the HCI reliability is improved.

Description

CMOS device and process method
Technical Field
The invention relates to the field of semiconductors, in particular to a CMOS device and a process method of the CMOS device.
Background
In the CMOS process, an NMOS device and a PMOS device are simultaneously manufactured on the same silicon substrate to manufacture a CMOS integrated circuit. The CMOS device comprises PMOS and NMOS which are mutually isolated by a well, wherein the PMOS is placed in an N well, and the NMOS is placed in a P well. The CMOS integrated circuit has the advantages of low power consumption, high speed, strong anti-interference capability, high integration level and the like. CMOS technology has become the mainstream technology of current large-scale integrated circuits, and most integrated circuits are manufactured by CMOS technology.
Under high working voltage, a strong transverse electric field exists in a channel of the device, so that a carrier is subjected to impact ionization in the transportation process to generate extra electron hole pairs, and part of hot carriers are injected into a gate oxide layer, so that the threshold voltage of the device is increased, the saturation current and the carrier mobility are reduced, and the like, and the phenomenon is called HCI (hot carrier injection) effect. The hot carrier injection effect is an important index influencing the performance of a semiconductor transistor device and is also an important index of the reliability test of the transistor device.
In the existing high-voltage BCD process, in order to not increase extra mask cost when manufacturing CMOS, NLDD implantation is implemented in a normal injection manner after gate formation, and PLDD implantation is performed after sidewall formation and is performed together with P + in PMOS. Because PLDD injection needs to compensate for the NLDD of the normal injection, the thickness of the gate sidewall cannot be too thick, but this brings that the N + injection of the source and drain regions of the NMOS is too close to the channel, resulting in a strong electric field at the edge of the drain-side gate and failure of HCI reliability.
Disclosure of Invention
The invention aims to solve the technical problem of providing a CMOS device, which reduces the grid fringe electric field of a low-voltage NMOS close to a drain end in the COMS and optimizes the HCI reliability.
The invention also provides a process method of the CMOS device.
In order to solve the above problems, the present invention provides a CMOS device having a first well of a first conductivity type and a second well of a second conductivity type abutting against each other on a semiconductor substrate, edges of the first well and the second well each having an isolation structure, wherein the abutting edges share one isolation structure; the first trap and the second trap form two independent isolation regions respectively.
In the first well, a heavily doped region of a second conductivity type is included and is respectively used as a source region and a drain region of the MOS device; the source and drain regions are respectively located in the LDD regions of the second conductivity type.
The substrate surface between the LDD regions in the first well has a gate dielectric layer and a gate electrode over the gate dielectric layer.
In the second well, a heavily doped region of the first conductivity type is included and is respectively used as a source region and a drain region of the MOS device; the source and drain regions are respectively located in LDD regions of the first conductivity type.
The substrate surface between the LDD regions in the second well has a gate dielectric layer and a gate electrode over the gate dielectric layer.
Both sides of the grid electrode on the first trap and both sides of the grid electrode on the second trap comprise side walls; the side walls are formed by compounding two layers of media.
The further improvement is that the medium of the side wall is an oxide film or a nitride film.
In a further improvement, the isolation structure is field oxide or STI.
In a further improvement, the first conductivity type is P-type and the second conductivity type is N-type.
The technological method of the CMOS device comprises the following steps:
step 1, forming an isolation structure on a semiconductor substrate, and forming a first well of a first conductivity type and a second well of a second conductivity type by ion implantation; forming a dielectric layer on the surface of the semiconductor substrate, and then forming a polycrystalline silicon layer on the dielectric layer; and etching to form a polysilicon gate structure.
Then, impurity ions of a second conductivity type are implanted into the semiconductor substrate to form an LDD region of the second conductivity type.
And 2, depositing a first dielectric film layer, then etching, and respectively forming a first layer of side walls on the two sides of the polysilicon gate of the first trap and the polysilicon gate of the second trap.
And step 3, performing impurity implantation of the first conduction type to form an LDD region.
And 4, implanting heavily-doped impurities of the first conductivity type into the second well to form a source region and a drain region.
And 5, forming a second dielectric film layer again, and then etching to form second layer side walls on the polysilicon gate of the first trap and the two sides of the polysilicon gate of the second trap respectively.
And 6, implanting heavily doped impurities of the second conductivity type into the first well to form a source region and a drain region.
The further improvement is that, in the step 1, the formed isolation structure is field oxide or STI; the normal implantation of the impurity ions of the second conductivity type may be angled implantation or non-angled vertical implantation.
In a further improvement, in the step 2, the formed first dielectric film layer is an oxide film or a nitride film.
The further improvement is that the thickness of the first dielectric film layer is 500-1500A.
In a further improvement, in the step 3, the impurity implantation of the first conductivity type is an oblique angle implantation having a certain inclination angle with the substrate surface, and the implantation direction tends to be deeper below the gate.
In a further improvement, in the step 5, the formed second dielectric film layer is an oxide film or a nitride film.
The further improvement is that the thickness of the second dielectric film layer is 50-1000A.
According to the CMOS device, on the premise that the characteristics of the PMOS are not changed, LDD injection is carried out on the basis that the side walls are formed step by step, so that the distance between a heavily doped region of the source and drain ends of the NMOS device and a channel is increased, the grid edge electric field of the NMOS close to the drain ends is effectively reduced, and the HCI reliability is improved.
Drawings
FIGS. 1 to 6 are schematic views of the process steps of the present invention.
FIG. 7 is a flow chart of the process steps of the present invention.
Description of the reference numerals
101 substrate
102 Pwell
103 Nwell
104 field oxygen
105 grid
206 NLDD
207 PLDD
208 (two-layer) sidewalls.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
In the CMOS device according to the present invention, as shown in fig. 6, in the present embodiment, the first conductivity type is defined as P-type, and the second conductivity type is defined as N-type. In some application scenarios, the first conductivity type and the second conductivity type may be opposite to the aforementioned definitions.
On a semiconductor substrate 101, there are a first P-type well 102 and a second N-type well 103, which are abutted against each other and have isolation structures, such as STI or field oxide, at their edges. The first well 102 of P-type forms an NMOS and the second well 103 of N-type forms a PMOS. Wherein the edges abutting against each other share one isolation structure; the first well 102 and the second well 103 form two independent isolation regions, respectively.
In the first well 102, an N-type heavily doped region N + is included as a source region and a drain region of the MOS device, respectively; the source and drain regions are located in respective N-type LDD regions, i.e., LDD region 206.
The substrate surface between the LDD regions 206 in the first well 102 has a gate dielectric layer and a gate electrode 105 located over the gate dielectric layer. The gate dielectric layer is generally a silicon oxide layer, the gate 105 is a polysilicon layer, a tungsten silicon layer can also cover the upper part of the gate, and the tungsten silicon layer can effectively prevent high-energy common injection N-type impurity ions from injecting and penetrating into channel regions below the gates of the NMOS and the PMOS.
In the second well 103, a P-type heavily doped region P + is included as a source region and a drain region of the MOS device, respectively; the source and drain regions are located in the LDD regions of the P-type, i.e., LDD region 207, respectively.
The substrate surface between the LDD regions in the second well 103 has a gate dielectric layer and a gate electrode over the gate dielectric layer, which structure is consistent with the gate electrode structure over the first well 102.
Both sides of the gate on the first well 102 and both sides of the gate on the second well 103 comprise spacers 208; the side walls are formed by compounding two layers of media. The first layer side wall can be an oxide film or a nitride film, and a silicon oxide film is adopted in the embodiment, and the thickness of the silicon oxide film is 500-1500A. The second layer sidewall can be an oxide film or a nitride film, and the embodiment adopts a silicon oxide film with a thickness of 50-1000A.
The CMOS device may adopt the following process method, including the steps of:
step 1, as shown in fig. 1, an isolation structure, such as STI or field oxide, is formed on a semiconductor substrate, and the present embodiment forms field oxide 104. A first trap 102 of P and a second trap 103 of N type are formed by ion implantation; forming a silicon oxide layer on the surface of the semiconductor substrate as a gate dielectric layer, and then forming a polycrystalline silicon layer on the silicon oxide layer; and etching to form a polysilicon gate structure. The gate structure further comprises a tungsten silicon layer formed above the polysilicon gate, wherein the tungsten silicon layer can effectively block the punch-through of high-energy general injection N-type impurity ions to a channel region below the gates of the NMOS and the PMOS in a subsequent ion general injection process.
Then, N-type impurity ions are implanted into the semiconductor substrate without a mask to form N-type LDD regions 206.
And 2, depositing a silicon oxide layer with the thickness of 500-1500A, and then etching to form first layer side walls 208 on two sides of the polysilicon gate of the first well 102 and the polysilicon gate of the second well 103 respectively. As shown in fig. 2.
Step 3, as shown in fig. 3, performing P-type impurity implantation to form LDD regions 207; and adopting oblique angle implantation, wherein the implantation direction leads the P-type impurity ions to extend to the center of the channel below the grid. And performing oblique angle injection on P-type ions to compensate the normal injection of the N-type LDD to form a P-type LDD, so as to realize a P-type source drain active region.
In step 4, as shown in fig. 4, heavily doped P-type impurity implantation is performed in the second well 103 to form source and drain regions P +.
And 5, forming a second dielectric film layer silicon oxide layer again to form a thickness of 50-1000A, then etching, and forming second layer side walls on two sides of the polysilicon gate of the first well 102 and the polysilicon gate of the second well 103 respectively, as shown in fig. 5.
And 6, heavily doped N-type impurities are injected into the first well to form a source region and a drain region N +. As shown in fig. 6, the CMOS process of the present invention is completed.
The process is based on a process method for improving the reliability of the HCI of the NMOS in the BCD platform, and under the condition that the characteristics of the PMOS are not changed, the distance between the N + of the source and the drain of the NMOS and the channel is increased through a side wall secondary forming process, the grid edge electric field of the NMOS close to the drain is effectively reduced, and the reliability of the HCI is improved.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. A CMOS device, characterized by: the semiconductor device comprises a semiconductor substrate, a first well, a second well, a first conductive type and a second conductive type, wherein the first conductive type and the second conductive type are mutually abutted, edges of the first well and the second well are respectively provided with an isolation structure, and the abutted edges share one isolation structure; the first trap and the second trap form two independent isolation regions respectively;
in the first well, a heavily doped region of a second conductivity type is included and is respectively used as a source region and a drain region of the MOS device; the source region and the drain region are respectively located in the LDD region of the second conductivity type;
a gate dielectric layer and a gate electrode positioned above the gate dielectric layer are arranged on the surface of the substrate between the LDD regions in the first trap;
in the second well, a heavily doped region of the first conductivity type is included and is respectively used as a source region and a drain region of the MOS device; the source region and the drain region are respectively located in the LDD region of the first conductivity type;
a gate dielectric layer and a gate electrode positioned above the gate dielectric layer are arranged on the surface of the substrate between the LDD regions in the second trap;
both sides of the grid electrode on the first trap and both sides of the grid electrode on the second trap comprise side walls; the side walls are formed by compounding two layers of media.
2. The CMOS device of claim 1, wherein: the medium of the side wall is an oxide film or a nitride film.
3. The CMOS device of claim 1, wherein: the isolation structure is field oxide or STI.
4. The CMOS device of claim 1, wherein: the grid electrode comprises a polysilicon layer and tungsten silicon positioned on the polysilicon layer.
5. The CMOS device of claim 1, wherein: the first conductive type is P type, and the second conductive type is N type.
6. A process method of fabricating the CMOS device of claim 1, wherein: comprises the following steps:
step 1, forming an isolation structure on a semiconductor substrate, and forming a first well of a first conductivity type and a second well of a second conductivity type by ion implantation; forming a dielectric layer on the surface of the semiconductor substrate, and then forming a polycrystalline silicon layer and a tungsten silicon layer on the dielectric layer; etching to form a polysilicon gate structure;
then, carrying out common injection of impurity ions of a second conduction type on the semiconductor substrate to form an LDD region of the second conduction type;
depositing a first dielectric film layer, then etching, and respectively forming a first layer of side walls on the two sides of the polysilicon gate of the first trap and the polysilicon gate of the second trap;
step 3, performing impurity implantation of the first conduction type to form an LDD region;
step 4, heavily doped impurities of the first conductivity type are injected into the second well to form a source region and a drain region;
step 5, forming a second dielectric film layer again, then etching, and forming second layer side walls on the polysilicon gate of the first trap and the two sides of the polysilicon gate of the second trap respectively;
and 6, implanting heavily doped impurities of the second conductivity type into the first well to form a source region and a drain region.
7. The process of manufacturing a CMOS device according to claim 6, wherein: in the step 1, the formed isolation structure is field oxide or STI; the common implantation of the impurity ions of the second conduction type is angled implantation or non-angled vertical implantation; the tungsten silicon layer can prevent high-energy common-injection N-type impurity ions from injecting and penetrating through channel regions below gates of NMOS and PMOS in a subsequent ion common-injection process.
8. The CMOS device of claim 6, wherein: in the step 2, the formed first dielectric film layer is an oxide film or a nitride film.
9. The CMOS device of claim 8, wherein: the thickness of the first dielectric film layer is 500-1500A.
10. The CMOS device of claim 6, wherein: in the step 3, the first conductive type impurity implantation is oblique angle implantation with a certain inclination angle with the substrate surface, and the implantation direction tends to be deeper to the lower part of the grid.
11. The CMOS device of claim 6, wherein: in the step 5, the formed second dielectric film layer is an oxide film or a nitride film.
12. The CMOS device of claim 11, wherein: the thickness of the second dielectric film layer is 50-1000A.
CN202110862336.9A 2021-07-29 2021-07-29 CMOS device and process method Pending CN113555362A (en)

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Application publication date: 20211026