CN108470680A - The production method of semiconductor structure - Google Patents
The production method of semiconductor structure Download PDFInfo
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- CN108470680A CN108470680A CN201710100565.0A CN201710100565A CN108470680A CN 108470680 A CN108470680 A CN 108470680A CN 201710100565 A CN201710100565 A CN 201710100565A CN 108470680 A CN108470680 A CN 108470680A
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- semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
Present invention is disclosed a kind of production methods of semiconductor structure.The production method of semiconductor structure provided by the invention, including：It is formed with first kind trap and Second Type trap, and the grid being located on first kind trap and Second Type trap；It carries out first time ion implanting and forms the first injection region；The first mask layer is formed on the first kind trap and on the grid of Second Type trap and carries out second of ion implanting forms the second injection region；The second mask layer is formed on the Second Type trap and on the grid of first kind trap and carries out third time ion implanting so that the first injection region in first kind trap is changed into third injection region, and forms the 4th injection region., can be cost-effective thereby, it is possible at least save the light shield of two layers LDD and corresponding at least two procedures, optimize manufacture craft, shortens the production cycle.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of production method of semiconductor structure.
Background technology
Complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, referred to as
CMOS it is) in integrated circuit design, while to use two kinds of devices of NMOS tube and PMOS tube, and usually matches a kind of electricity of appearance
Line structure.Since the quiescent dissipation of cmos circuit is very small, circuit structure is simple so that it can be used for large-scale integrated electricity
Road, super large-scale integration.
Keep in mind grid groove size with semiconductor fabrication and more does smaller and lower and lower applied voltage direction hair
Exhibition, traditional CMOS structure, come electric field vertical component caused by voltage input/drain bias, and are subtracted by the control to ion implanting
It is small can break-through electron amount and inhibit thermoelectronic effect.But current technique is usually all more complicated, is changed
It is kind.
Invention content
The purpose of the present invention is to provide a kind of production methods of semiconductor structure, on the basis of improving MOS performances, section
About production cost, and shorten the production cycle.
In order to solve the above technical problems, the present invention provides a kind of production method of semiconductor structure, including：
Front-end architecture is provided, the front-end architecture is formed with first kind trap and Second Type trap, and is located at the
Grid on one type trap and Second Type trap；
First time ion implanting is carried out to the front-end architecture, with the grid in first kind trap and Second Type trap respectively
Both sides form the first injection region；
On the first kind trap and the first mask layer is formed on the grid of Second Type trap, and to the Second Type
Trap carries out second of ion implanting, and grid both sides form the second injection region in Second Type trap, first time injection from
Son is identical with the ionic type of second of injection；
Remove first mask layer；
On the Second Type trap and the second mask layer is formed on the grid of first kind trap, and to the first kind
Trap carries out third time ion implanting so that the first injection region in first kind trap is changed into third injection region, and in the first kind
Grid both sides form the 4th injection region in type trap, and the ion of the first time injection is different with the ionic type of third time injection；
Remove second mask layer.
Optionally, for the production method of the semiconductor structure, the first kind trap is N traps, second class
Type trap is p-well.
Optionally, for the production method of the semiconductor structure, the second mask layer thickness on the grid of the N traps
Less than the first mask layer thickness on the grid of the p-well.
Optionally, for the production method of the semiconductor structure, the thickness of the first mask layer on the grid of the p-well
Degree isThe second mask layer thickness on the grid of the N traps is
Optionally, for the production method of the semiconductor structure, the doping concentration of second injection region and injection
Depth is more than the doping concentration and injection depth of first injection region；The doping concentration and injection depth of 4th injection region
More than the doping concentration and injection depth of the third injection region.
Optionally, for the production method of the semiconductor structure, the first time ion implanting be general note N-type from
Son.
Optionally, for the production method of the semiconductor structure, second of ion implanting be injection N-type from
Son, the third time ion implanting are implanting p-type ion.
Optionally, for the production method of the semiconductor structure, the angle of the third time ion implanting be with it is preceding
The normal direction of end structure upper surface is in 30 ° of -60 ° of angles.
Optionally, for the production method of the semiconductor structure, the first secondary ion is being carried out to the front-end architecture
Injection, with grid both sides are formed after the first injection region in first kind trap and Second Type trap respectively；In the first kind
Form the first mask layer on the grid of type trap and Second Type trap, and to the Second Type trap carry out second ion implanting it
Before, further include：
Grid curb wall is formed in the grid both sides.
Optionally, for the production method of the semiconductor structure, it is located at the gate electrode side of the gate electrode side of first kind trap
Wall thickness is less than the grid curb wall thickness of the gate electrode side positioned at Second Type trap.
Optionally, for the production method of the semiconductor structure, it is located at the gate electrode side of the gate electrode side of Second Type trap
Wall thickness is 90nm-110nm, and the grid curb wall thickness for being located at the gate electrode side of first kind trap is 80nm-90nm.
Optionally, for the production method of the semiconductor structure, the front-end architecture further includes gate oxide, described
Gate oxide is located on the first kind trap and Second Type trap, and the grid is located on the gate oxide.
Optionally, for the production method of the semiconductor structure, the thickness of the gate oxide is
Optionally, for the production method of the semiconductor structure, after providing front-end architecture, to the front end
Before structure carries out first time ion implanting, further include：
Rapid thermal oxidation processing is carried out to the grid.
Optionally, the production method of the semiconductor structure is also wrapped after removing second mask layer
It includes：
Carry out annealing process.
The production method of semiconductor structure provided by the invention, including：Front-end architecture is provided, the front-end architecture is formed with
First kind trap and Second Type trap, and the grid that is located on first kind trap and Second Type trap；To the front end
Structure carries out first time ion implanting, with grid both sides form the first injection in first kind trap and Second Type trap respectively
Area；Form the first mask layer on the first kind trap and on the grid of Second Type trap, and to the Second Type trap into
Second of ion implanting of row, grid both sides form the second injection region in Second Type trap, the ion of first time injection and
The ionic type of second of injection is identical；Remove first mask layer；On the Second Type trap and first kind trap
The second mask layer is formed on grid, and third time ion implanting is carried out to the first kind trap so that in first kind trap
First injection region is changed into third injection region, and grid both sides form the 4th injection region, the first time in first kind trap
The ion of injection is different with the ionic type of third time injection；Remove second mask layer.As a result, by first time injection and
Third time injection can form the first injection region and third injection region as LDD, can at least save two compared with prior art
The light shield of layer LDD and corresponding at least two procedures, it is seen that can be greatly cost-effective, optimize manufacture craft, shortens life
Produce the period.
And it is possible to realize the adjusting of NMOS performances by first time ion implanting and second of ion implanting；Pass through
Primary ions are injected and third time ion implanting, and further combined with the thickness of grid curb wall, the thickness of mask layer and third
The selection of secondary ion implant angle realizes the adjusting to PMOS performances, such as improves the leakage current of MOS structure so that product
Performance ensured.
Description of the drawings
Fig. 1-Fig. 6 is a kind of manufacturing process schematic diagram of CMOS structure；
The flow chart of the production method of semiconductor structure in the one embodiment of the invention of the positions Fig. 7；
Fig. 8 is the schematic diagram that front-end architecture is provided in one embodiment of the invention；
Fig. 9 is the schematic diagram that first time ion implanting is carried out in one embodiment of the invention；
Figure 10 is the schematic diagram that grid curb wall is formed in one embodiment of the invention；
Figure 11 is the schematic diagram that second of ion implanting is carried out in one embodiment of the invention；
Figure 12 is the schematic diagram that second of ion implanting is carried out in one embodiment of the invention；
Figure 13 is the schematic diagram of the semiconductor structure obtained in one embodiment of the invention.
Specific implementation mode
The production method of the semiconductor structure of the present invention is described in more detail below in conjunction with schematic diagram, wherein table
Showing the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still
Realize the advantageous effects of the present invention.Therefore, following description should be understood as the widely known of those skilled in the art, and
It is not intended as limitation of the present invention.
The present invention is more specifically described by way of example with reference to attached drawing in the following passage.It is wanted according to following explanation and right
Ask book, advantages and features of the invention that will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Inventor has found in long-term research, when grid width is less than 2 μm, between source electrode and drain electrode caused by bias
By high enough to accelerating the oxide layer that electronics keeps its tunnels thin, this thermoelectronic effect is caused to leak electricity electric field vertical component
Stream will influence transistor performance, as the electron capture effect of grid oxic horizon causes IC chip reliability to ask
Topic.
Traditional LDD (lightly doped drain) knots are realized by using low energy, the ion implantation technology of low current.Deposition and
It is etched back to after dielectric, side wall spacers can be formed in polysilicon gate both sides.High current, the ion implanting of low energy are formed
Heavy doping source/drain, is separated using side wall spacers and grid, so as to reduce source/drain bias caused by electric field it is vertical
Component, and reduce can break-through electron amount and inhibit thermoelectronic effect.
- Fig. 6 is please referred to Fig.1, a kind of production method of CMOS structure is shown, includes the following steps：
As shown in Figure 1, including providing substrate 1, the areas PMOS and NMOS area are formed by ion implanting, the specially areas PMOS are wrapped
N traps 2 are included, NMOS area includes p-well 3, and is isolated by isolation structure (STI) 4, and gate oxide 5 is also formed on substrate 1.
As shown in Fig. 2, forming grid 6, then forms photoresist 7 and cover N traps 2, expose p-well 3, carry out ion implanting, obtain
Obtain LDD structures 8.
As shown in figure 3, removing photoresist 7 and forming photoresist 9, p-well 3 is covered, exposes N traps 2, carries out ion implanting, is obtained
LDD structures 10.
As shown in figure 4, removing photoresist 9 and forming side wall 11.
As shown in figure 5, mask layer 12 is formed, the gate structure (including grid 16 and side wall) on covering N traps 2 and p-well 3,
Ion implanting is carried out, N-type heavily doped region 13 is obtained.
As shown in fig. 6, removal mask layer 12, forms mask layer 14 and cover gate structure (including grid on p-well 3 and N traps 2
Pole 16 and side wall), ion implanting is carried out, p-type heavily doped region 15 is obtained.
When graphical size is less than 0.18 μm, the dosage of LDD ion implantings is just no longer belong to gently inject, i.e., source/drain expands
Open up ion implanting.Meanwhile LDD is the ion implanting of light shield selective area, the light shield number needed is 2 or 4 layers, for polysilicon
Device (such as >=0.18 μm) larger grid CD (critical size) certainly will lead to cost if the light shield number of plies of input is more
It is higher, and extend the production cycle of chip.
Then, the present invention provides a kind of production method of semiconductor structure, improves this problem.
As shown in fig. 7, the embodiment of the present invention provides a kind of production method of semiconductor structure, including：
Step S11, provides front-end architecture, and the front-end architecture is formed with first kind trap and Second Type trap, Yi Jifen
Grid that Wei Yu be on first kind trap and Second Type trap；
Step S12 carries out first time ion implanting, with respectively in first kind trap and Second Type to the front-end architecture
Grid both sides form the first injection region in trap；
Step S13 on the first kind trap and forms the first mask layer on the grid of Second Type trap, and to described
Second Type trap carries out second of ion implanting, and grid both sides form the second injection region, the first time in Second Type trap
The ion of injection is identical with the ionic type of second of injection；
Step S14 removes first mask layer；
Step S15 on the Second Type trap and forms the second mask layer on the grid of first kind trap, and to described
First kind trap carries out third time ion implanting so that and the first injection region in first kind trap is changed into third injection region, and
Grid both sides form the 4th injection region, the ionic species of the ion and third time injection of the first time injection in first kind trap
Type is different；
Step S16 removes second mask layer.
It is described in detail with reference to Fig. 8-13 pairs of above-mentioned steps.
As shown in figure 8, for step S11, front-end architecture is provided, the front-end architecture is formed with 101 He of first kind trap
Second Type trap 102, and the grid 105 that is located on first kind trap 101 and Second Type trap 102.
Specifically, a substrate 100 can be to provide, 100 constituent material of the substrate may be used undoped monocrystalline silicon,
Doped with monocrystalline silicon, the silicon-on-insulator (SOI) etc. of impurity.As an example, in the present embodiment, substrate 100 selects monocrystalline silicon
Material is constituted.Buried layer (not shown) etc. can also be formed in the substrate 100.
Also, the substrate 100 forms first kind trap 101 and Second Type trap 102 by ion implanting, and described first
Type trap 101 and Second Type trap 102 can be by isolation structure (being, for example, STI) 103 isolation.
Further, gate oxide 104 is formed also on the substrate 100, such as can form the grid by boiler tube
Oxide layer 104, thickness can be
The grid 105 can be polycrystalline silicon material.
In embodiments of the present invention, with the first kind trap 101 be N traps, Second Type trap 102 be p-well for carry out
Explanation.Those skilled in the art below on the basis of, by change ion implanting type, first kind trap can also be selected
101 be p-well, and Second Type trap 102 is that N traps are made, and the present invention is compared and is not particularly limited.
Prior art may be used to complete in the offer of above-mentioned front-end architecture, and according to actual needs, note can be adjusted flexibly
Enter the thickness equidimension of ionic species, concentration and film layer.
Referring to FIG. 9, for step S12, first time ion implanting is carried out to the front-end architecture, with respectively in N traps 101
The first injection region 106 is formed with grid both sides in p-well 102.
Specifically, the first time ion implanting is general note N-type ion, i.e., inject (Blanket LDD without light shield whole face
IMP), for example, injection ion can be phosphorus (P) ion, implantation concentration can be 2.2*103/cm2-2.5*103/cm2, depth is about
For
Preferably, in order to be protected to grid in first time ion implanting, it can after step s 11, to described
Grid 105 carries out rapid thermal oxidation processing prevents ion implanting from being made to grid 105 to form layer of oxide layer (not shown)
At damage.
Fig. 9-Figure 10, step S13 are please referred to, on the N traps 101 and forms the first mask on the grid 105 of p-well 102
Layer 108, and second of ion implanting is carried out to the p-well 102,105 both sides of grid form the second injection region in p-well 102
109, the ion of the first time injection is identical with the ionic type of second of injection.This step that is to say to form the mistake of NMOS
Journey.
Specifically, as shown in Figure 10, first forming grid curb wall 107 in 105 both sides of the grid.In order to contribute to the present invention
Preferable MOS performances are obtained, the grid curb wall 107 on N traps 101 and in p-well 102 can be made to have different thickness (i.e. such as
Transverse width shown in Fig. 10) so that the 107 thickness D1 of grid curb wall for being located at 105 side of grid of N traps 101 is less than positioned at p-well
The 107 thickness D2 of grid curb wall of 102 105 side of grid.For example, 107 thickness of grid curb wall positioned at 105 side of grid of p-well 102
D1 is 90nm-110nm, such as 100nm, and the 107 thickness D2 of grid curb wall for being located at 105 side of grid of N traps 101 is 80nm-90nm,
Such as 85nm.The effect of this design will specifically be inquired into step S15.
This step can be that N traps 101 (including grid 105 and grid curb wall is completely covered in first mask layer 108
107) grid 105 and grid curb wall 107, and above p-well 102 are then only covered.In order to obtain preferably injection effect, described the
Thickness H1 of one mask layer 108 at p-well 102 beSuch as can beDeng.
In the present embodiment, first mask layer 108 can be selected as photoresist, can either realize the protection of ion implanting, and can
Convenient removal.
Further, in order to adjust the performance of NMOS, second of ion implanting in this step can also have certain
Angle (as shown in figure 11).
Second of ion implanting is injection N-type ion, such as can be phosphorus, arsenic etc., and implantation concentration can be 2.8*
103/cm2-3.2*103/cm2, depth is about
After second of ion implanting of this step, it is heavily doped as N-type that the second injection region 109 can be formed in p-well 102
Miscellaneous area, the doping concentration and injection depth of second injection region 109 are more than the doping concentration and note of first injection region 106
Enter depth.
Step S14 is to remove first mask layer 108, and common process may be used to complete, such as ashing and cleaning
.
2 are please referred to Fig.1, for step S15, in the p-well 102 and forms the second mask on the grid of N traps 101 105
Layer 110, and third time ion implanting is carried out to the N traps 101 so that the first injection region 106 in N traps 101 is changed into third
Injection region 111, and 105 both sides of grid form the 4th injection region 112, the ion and third of the first time injection in N traps 101
The ionic type of secondary injection is different.This step that is to say to form the process of PMOS.
In the present embodiment, second mask layer 110 can be selected as photoresist, can either realize the anti-of ion implanting
Shield, and can easily remove.
It is understood that LDD structures (i.e. the first injection region 106 and third injection in N traps 101 and in p-well 102
Area 111) its doping type is inconsistent, and the first time ion implanting carried out before forms the first note in N traps 101
Enter area 106, therefore, this step is the neutralization to the first injection region 106 in N traps 101 first by the realization of third time ion implanting,
Then the first injection region 106 is further changed into third injection region 111.
In order to preferably realize this purpose, as described above, the grid curb wall 107 at N traps 101 is relatively thin, thus, it is possible to
Enough ensure that third time ion implanting can influence entire first injection region, 106 region.
In addition it is also possible to be the angle for adjusting third time ion implanting, the angle of the e.g. described third time ion implanting
To be in 30 ° of -60 ° of angle thetas with the normal direction of front-end architecture upper surface, such as 35 °.
It is understood that above-mentioned grid curb wall thickness, mask layer thickness and implant angle these conditions can foundations
Whether actual needs selection or not, and can be that multiple conditions are used in conjunction with.
The thickness that the part on N traps 101 can also be further located to second mask layer 110 is adjusted,
So that 110 thickness of the second mask layer on the grid 105 of the N traps 101 is covered less than first on the grid 105 of the p-well 102
108 thickness of film layer.For example, the 110 thickness H2 of the second mask layer on the grid 105 of the N traps 101 is
Such asDeng.Thus the occlusion area to ion implanting is reduced, can also realize preferable ion implanting.
The third time ion implanting is implanting p-type ion, such as can be boron, gallium etc., and implantation concentration can be 1.5*
104/cm2-1.8*104/cm2, depth is about
After the third time ion implanting of this step, third injection region 111 is on the one hand formd, is on the other hand also formed
4th injection region 112, wherein third injection region 111 are LDD structures, and the 4th injection region 112 is used as N-type heavily doped region, described the
The doping concentration and injection depth of four injection regions 112 are more than the doping concentration and injection depth of the third injection region 111.
Step S16 is to remove second mask layer 110, and common process may be used to complete, such as ashing and cleaning
.After its removal, structure as shown in fig. 13 that can be obtained, for the CMOS of the embodiment of the present invention, including substrate 100, N
Trap 101 and p-well 102, the N traps 101 and p-well 102 are isolated by isolation structure 103, and third injection region is formed in N traps 101
111 and the 4th injection region 112, the first injection region 106 and the second injection region 109 are formed in p-well 102, on N traps 101 and P
Gate oxide 104 and grid 105 and grid curb wall 107 are formed on trap 102.
Further, after removing second mask layer, further include：Annealing process is carried out, conventional work may be used
Skill is completed.
It is understood that the present invention may be equally applicable for adjusting other MOS structures, such as the work for LV/HVMOS
Skill again may be by adjusting photoresist thickness or ion implantation angle etc. to ensure that a kind of structure (such as HVMOS) performance is complete
In the case of kind, twice LDD processes are adjusted in turn and ensure that another structure (such as LVMOS) performance is met the requirements, this kind of side
Method can equally save at least two layers of LDD light shield and corresponding at least two procedures shorten chip to save manufacturing cost
Production cycle.
In conclusion the production method of semiconductor structure provided by the invention, including：Front-end architecture, the front end are provided
Structure is formed with first kind trap and Second Type trap, and the grid being located on first kind trap and Second Type trap；
First time ion implanting is carried out to the front-end architecture, with grid both sides are formed in first kind trap and Second Type trap respectively
First injection region；On the first kind trap and the first mask layer is formed on the grid of Second Type trap, and to described second
Type trap carries out second of ion implanting, and grid both sides form the second injection region, the first time injection in Second Type trap
Ion it is identical with the ionic type of second injection；Remove first mask layer；On the Second Type trap and first
The second mask layer is formed on the grid of type trap, and third time ion implanting is carried out to the first kind trap so that the first kind
The first injection region in type trap is changed into third injection region, and grid both sides form the 4th injection region, institute in first kind trap
It is different with the ionic type of third time injection to state the ion of injection for the first time；Remove second mask layer.Pass through first as a result,
Secondary injection and third time injection can form the first injection region and third injection region as LDD, compared with prior art can be extremely
The light shield of two layers LDD and corresponding at least two procedures are saved less, it is seen that can be greatly cost-effective, optimization makes work
Skill shortens the production cycle.
And it is possible to realize the adjusting of NMOS performances by first time ion implanting and second of ion implanting；Pass through
Primary ions are injected and third time ion implanting, and further combined with the thickness of grid curb wall, the thickness of mask layer and third
The selection of secondary ion implant angle realizes the adjusting to PMOS performances, such as improves the leakage current of MOS structure so that product
Performance ensured.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (15)
1. a kind of production method of semiconductor structure, including：
Front-end architecture is provided, the front-end architecture is formed with first kind trap and Second Type trap, and is located at the first kind
Grid on type trap and Second Type trap；
First time ion implanting is carried out to the front-end architecture, with the grid both sides in first kind trap and Second Type trap respectively
Form the first injection region；
Form the first mask layer on the first kind trap and on the grid of Second Type trap, and to the Second Type trap into
Second of ion implanting of row, grid both sides form the second injection region in Second Type trap, the ion of first time injection and
The ionic type of second of injection is identical；
Remove first mask layer；
Form the second mask layer on the Second Type trap and on the grid of first kind trap, and to the first kind trap into
Row third time ion implanting so that the first injection region in first kind trap is changed into third injection region, and in first kind trap
Middle grid both sides form the 4th injection region, and the ion of the first time injection is different with the ionic type of third time injection；
Remove second mask layer.
2. the production method of semiconductor structure as described in claim 1, which is characterized in that the first kind trap is N traps, institute
It is p-well to state Second Type trap.
3. the production method of semiconductor structure as claimed in claim 2, which is characterized in that second on the grid of the N traps
Mask layer thickness is less than the first mask layer thickness on the grid of the p-well.
4. the production method of semiconductor structure as claimed in claim 3, which is characterized in that first on the grid of the p-well
The thickness of mask layer isThe second mask layer thickness on the grid of the N traps is
5. the production method of semiconductor structure as claimed in claim 2, which is characterized in that the doping of second injection region is dense
Degree and injection depth are more than the doping concentration and injection depth of first injection region；The doping concentration of 4th injection region and
Inject doping concentration and injection depth that depth is more than the third injection region.
6. the production method of semiconductor structure as claimed in claim 5, which is characterized in that the first time ion implanting is general
Note N-type ion.
7. the production method of semiconductor structure as claimed in claim 6, which is characterized in that second of ion implanting is note
Enter N-type ion, the third time ion implanting is implanting p-type ion.
8. the production method of semiconductor structure as claimed in claim 2, which is characterized in that the angle of the third time ion implanting
Degree is the normal direction with front-end architecture upper surface in 30 ° of -60 ° of angles.
9. the production method of semiconductor structure as claimed in claim 2, which is characterized in that carrying out the to the front-end architecture
Primary ions are injected, with grid both sides are formed after the first injection region in first kind trap and Second Type trap respectively；Institute
State and form the first mask layer on the grid of first kind trap and Second Type trap, and to the Second Type trap carry out second from
Before son injection, further include：
Grid curb wall is formed in the grid both sides.
10. the production method of semiconductor structure as claimed in claim 9, which is characterized in that be located at the grid of first kind trap
The grid curb wall thickness of side is less than the grid curb wall thickness of the gate electrode side positioned at Second Type trap.
11. the production method of semiconductor structure as claimed in claim 10, which is characterized in that be located at the grid of Second Type trap
The grid curb wall thickness of side is 90nm-110nm, and the grid curb wall thickness for being located at the gate electrode side of first kind trap is 80nm-90nm.
12. the production method of semiconductor structure as described in claim 1, which is characterized in that the front-end architecture further includes grid
Oxide layer, the gate oxide are located on the first kind trap and Second Type trap, and the grid is located at the gate oxide
On.
13. the production method of semiconductor structure as claimed in claim 12, which is characterized in that the thickness of the gate oxide is
14. the production method of semiconductor structure as described in claim 1, which is characterized in that after front-end architecture is provided,
Before carrying out first time ion implanting to the front-end architecture, further include：
Rapid thermal oxidation processing is carried out to the grid.
15. the production method of semiconductor structure as described in claim 1, which is characterized in that removing second mask layer
Later, further include：
Carry out annealing process.
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