CN108470680B - Method for manufacturing semiconductor structure - Google Patents
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- CN108470680B CN108470680B CN201710100565.0A CN201710100565A CN108470680B CN 108470680 B CN108470680 B CN 108470680B CN 201710100565 A CN201710100565 A CN 201710100565A CN 108470680 B CN108470680 B CN 108470680B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
The invention discloses a manufacturing method of a semiconductor structure. The manufacturing method of the semiconductor structure provided by the invention comprises the following steps: forming a first type trap, a second type trap and a grid electrode respectively positioned on the first type trap and the second type trap; carrying out first ion implantation to form a first implantation area; forming a first mask layer on the first type trap and the grid electrode of the second type trap and carrying out secondary ion implantation to form a second implantation area; and forming a second mask layer on the second type trap and the grid electrode of the first type trap and carrying out third ion implantation to convert the first implantation area in the first type trap into a third implantation area and form a fourth implantation area. Therefore, at least two layers of light masks of LDD and at least two corresponding processes can be saved, the cost can be saved, the manufacturing process can be optimized, and the production period can be shortened.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
Background
A Complementary Metal Oxide Semiconductor (CMOS) is a circuit structure that is formed by simultaneously using two devices, i.e., an NMOS transistor and a PMOS transistor, and usually paired together in an integrated circuit design. Because the static power consumption of the CMOS circuit is very small and the circuit structure is simple, the CMOS circuit can be used for large-scale integrated circuits and ultra-large scale integrated circuits.
As semiconductor fabrication technology is developing in the direction of smaller gate channel size and lower applied voltage, the conventional CMOS structure controls the vertical component of the electric field caused by source/drain bias voltage by controlling ion implantation, and reduces the amount of electrons that can pass through to suppress hot electron effect. However, the current processes are generally complex and require improvement.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor structure, which saves the production cost and shortens the production period on the basis of improving the MOS performance.
To solve the above technical problem, the present invention provides a method for fabricating a semiconductor structure, comprising:
providing a front-end structure, wherein the front-end structure is formed with a first type trap and a second type trap, and a grid electrode respectively positioned on the first type trap and the second type trap;
performing first ion implantation on the front-end structure to form first implantation regions on two sides of a grid electrode in the first type well and the second type well respectively;
forming a first mask layer on the first type trap and the grid electrode of the second type trap, carrying out secondary ion implantation on the second type trap, and forming second implantation areas on two sides of the grid electrode in the second type trap, wherein the ion type of the first implantation is the same as that of the second implantation;
removing the first mask layer;
forming a second mask layer on the second type trap and the grid electrode of the first type trap, and carrying out third ion implantation on the first type trap to convert a first implantation area in the first type trap into a third implantation area and form fourth implantation areas on two sides of the grid electrode in the first type trap, wherein the types of the first implantation ions and the third implantation ions are different;
and removing the second mask layer.
Optionally, for the manufacturing method of the semiconductor structure, the first-type well is an N-well, and the second-type well is a P-well.
Optionally, for the manufacturing method of the semiconductor structure, a thickness of the second mask layer on the gate of the N-well is smaller than a thickness of the first mask layer on the gate of the P-well.
Optionally, for the manufacturing method of the semiconductor structure, the thickness of the first mask layer on the gate of the P-well is
The thickness of the second mask layer on the grid electrode of the N trap is
Optionally, for the manufacturing method of the semiconductor structure, the doping concentration and the implantation depth of the second implantation region are greater than those of the first implantation region; the doping concentration and the implantation depth of the fourth implantation area are larger than those of the third implantation area.
Optionally, for the method for manufacturing the semiconductor structure, the first ion implantation is a normal N-type ion implantation.
Optionally, for the manufacturing method of the semiconductor structure, the second ion implantation is performed by implanting N-type ions, and the third ion implantation is performed by implanting P-type ions.
Optionally, for the method for manufacturing the semiconductor structure, the angle of the third ion implantation is 30 ° to 60 ° from the normal direction of the upper surface of the front end structure.
Optionally, for the manufacturing method of the semiconductor structure, after performing first ion implantation on the front end structure to form first implantation regions on two sides of the gate in the first type well and the second type well, respectively; forming a first mask layer on the gates of the first type well and the second type well, and before performing the second ion implantation on the second type well, the method further comprises:
and forming grid side walls on two sides of the grid.
Optionally, in the method for manufacturing the semiconductor structure, the thickness of the gate sidewall on the gate side of the first-type well is smaller than the thickness of the gate sidewall on the gate side of the second-type well.
Optionally, in the method for manufacturing the semiconductor structure, the thickness of the gate sidewall on the gate side of the second-type well is 90nm to 110nm, and the thickness of the gate sidewall on the gate side of the first-type well is 80nm to 90 nm.
Optionally, for the manufacturing method of the semiconductor structure, the front-end structure further includes a gate oxide layer, the gate oxide layer is located on the first type well and the second type well, and the gate is located on the gate oxide layer.
Optionally, for the manufacturing method of the semiconductor structure, the thickness of the gate oxide layer is
Optionally, for the method for manufacturing the semiconductor structure, after providing the front end structure, before performing the first ion implantation on the front end structure, the method further includes:
and carrying out rapid thermal oxidation treatment on the grid electrode.
Optionally, for the manufacturing method of the semiconductor structure, after removing the second mask layer, the method further includes:
and carrying out an annealing process.
The manufacturing method of the semiconductor structure provided by the invention comprises the following steps: providing a front-end structure, wherein the front-end structure is formed with a first type trap and a second type trap, and a grid electrode respectively positioned on the first type trap and the second type trap; performing first ion implantation on the front-end structure to form first implantation regions on two sides of a grid electrode in the first type well and the second type well respectively; forming a first mask layer on the first type trap and the grid electrode of the second type trap, carrying out secondary ion implantation on the second type trap, and forming second implantation areas on two sides of the grid electrode in the second type trap, wherein the ion type of the first implantation is the same as that of the second implantation; removing the first mask layer; forming a second mask layer on the second type trap and the grid electrode of the first type trap, and carrying out third ion implantation on the first type trap to convert a first implantation area in the first type trap into a third implantation area and form fourth implantation areas on two sides of the grid electrode in the first type trap, wherein the types of the first implantation ions and the third implantation ions are different; and removing the second mask layer. Therefore, the first injection region and the third injection region which are used as LDD can be formed through the first injection and the third injection, compared with the prior art, at least two layers of light masks of LDD can be saved, and at least two corresponding procedures are saved, so that the cost can be greatly saved, the manufacturing process is optimized, and the production period is shortened.
Moreover, the NMOS performance can be adjusted through the first ion implantation and the second ion implantation; through the first ion implantation and the third ion implantation, and further combining the thickness of the grid side wall, the thickness of the mask layer and the selection of the third ion implantation angle, the PMOS performance is adjusted, for example, the leakage current of the MOS structure is improved, so that the performance of the product is ensured.
Drawings
FIGS. 1-6 are schematic diagrams of a CMOS structure fabrication process;
FIG. 7 is a flow chart of a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating a front end architecture according to an embodiment of the present invention;
FIG. 9 is a schematic view illustrating a first ion implantation in accordance with an embodiment of the present invention;
FIG. 10 is a schematic view illustrating the formation of gate spacers according to an embodiment of the present invention;
FIG. 11 is a schematic view illustrating a second ion implantation in accordance with an embodiment of the present invention;
FIG. 12 is a schematic view illustrating a second ion implantation in accordance with an embodiment of the present invention;
fig. 13 is a schematic view of a semiconductor structure obtained in an embodiment of the present invention.
Detailed Description
The method of fabricating a semiconductor structure of the present invention will now be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The inventors have found in long-term studies that when the gate width is less than 2 μm, the vertical component of the electric field due to the bias between the source and drain electrodes is high enough to accelerate electrons to tunnel through the thin oxide layer, and the leakage current caused by this hot electron effect affects the transistor performance and also causes reliability problems of the integrated circuit chip due to the electron trapping effect of the gate oxide layer.
Conventional LDD (lightly doped drain) junctions are realized by using a low-energy, low-current ion implantation process. After depositing and etching back the dielectric, sidewall spacers are formed on both sides of the polysilicon gate. High current, low energy ion implantation forms a highly doped source/drain separated from the gate by a sidewall spacer, thereby reducing the vertical component of the electric field caused by source/drain bias and reducing the number of punchable electrons to suppress hot electron effects.
Referring to fig. 1-6, a method for fabricating a CMOS structure is shown, which includes the following steps:
as shown in fig. 1, the method includes providing a substrate 1, forming a PMOS region and an NMOS region by ion implantation, specifically, the PMOS region includes an N well 2, the NMOS region includes a P well 3 and is isolated by an isolation Structure (STI)4, and forming a gate oxide layer 5 on the substrate 1.
As shown in fig. 2, a gate 6 is formed, a photoresist 7 is formed to cover the N-well 2 and expose the P-well 3, and ion implantation is performed to obtain an LDD structure 8.
As shown in fig. 3, the photoresist 7 is removed and a photoresist 9 is formed to cover the P-well 3 and expose the N-well 2, and ion implantation is performed to obtain an LDD structure 10.
As shown in fig. 4, the photoresist 9 is removed and side walls 11 are formed.
As shown in fig. 5, a mask layer 12 is formed to cover the gate structures (including the gate 16 and the sidewalls) on the N-well 2 and the P-well 3, and ion implantation is performed to obtain an N-type heavily doped region 13.
As shown in fig. 6, the mask layer 12 is removed, a mask layer 14 is formed to cover the gate structures (including the gate 16 and the sidewalls) on the P-well 3 and the N-well 2, and ion implantation is performed to obtain the P-type heavily doped region 15.
When the patterning size is smaller than 0.18 μm, the dose of the LDD ion implantation is no longer a light implant, i.e., a source/drain extension ion implantation. Meanwhile, the LDD is the ion implantation of the selective area of the mask, the number of the required masks is 2 or 4, and for the device with larger polysilicon gate CD (critical dimension) (for example ≧ 0.18 μm), if the number of the mask layers is large, the cost is high and the production cycle of the chip is prolonged.
Accordingly, the present invention provides a method for fabricating a semiconductor structure, which improves the above-mentioned problem.
As shown in fig. 7, an embodiment of the invention provides a method for manufacturing a semiconductor structure, including:
step S11, providing a front-end structure, wherein the front-end structure is formed with a first type trap and a second type trap, and gates respectively positioned on the first type trap and the second type trap;
step S12, carrying out first ion implantation on the front-end structure to form first implantation regions on two sides of a grid electrode in the first type trap and the second type trap respectively;
step S13, forming a first mask layer on the first type trap and the grid electrode of the second type trap, carrying out second ion implantation on the second type trap, and forming second implantation areas on two sides of the grid electrode in the second type trap, wherein the first implantation ions and the second implantation ions are of the same type;
step S14, removing the first mask layer;
step S15, forming a second mask layer on the second type trap and the grid electrode of the first type trap, and carrying out third ion implantation on the first type trap to convert the first implantation area in the first type trap into a third implantation area, and forming fourth implantation areas on two sides of the grid electrode in the first type trap, wherein the types of the first implantation ions and the third implantation ions are different;
in step S16, the second mask layer is removed.
The above steps are described in detail below with reference to fig. 8-13.
As shown in fig. 8, for step S11, a front end structure is provided that is formed with a first type well 101 and a second type well 102, and a gate 105 on the first type well 101 and the second type well 102, respectively.
Specifically, a substrate 100 may be provided, and the substrate 100 may be formed of undoped monocrystalline silicon, impurity-doped monocrystalline silicon, silicon-on-insulator (SOI), or the like. By way of example, in the present embodiment, the substrate 100 is made of a single crystalline silicon material. A buried layer (not shown) or the like may also be formed in the substrate 100.
Furthermore, the substrate 100 forms a first type well 101 and a second type well 102 by ion implantation, and the first type well 101 and the second type well 102 may be isolated by an isolation structure (e.g., STI) 103.
Further, a gate oxide layer 104 is formed on the substrate 100, for example, the gate oxide layer 104 may be formed through a furnace tube, and the thickness thereof may be
The gate 105 may be a polysilicon material.
In the embodiment of the present invention, the first-type well 101 is an N-well, and the second-type well 102 is a P-well. On the basis of the following description, a person skilled in the art may select the first type well 101 to be a P-well and the second type well 102 to be an N-well by changing the type of ion implantation, and the comparison of the present invention is not particularly limited.
The front-end structure can be provided by adopting the existing process, and the sizes of the implanted ion species, the concentration, the thickness of the film layer and the like can be flexibly adjusted according to actual needs.
Referring to fig. 9, for step S12, a first ion implantation is performed on the front-end structure to form first implantation regions 106 on both sides of the gate in the N-well 101 and the P-well 102, respectively.
Specifically, the first ion implantation is a normal N-type ion implantation, i.e., a Blanket LDDIMP (Blanket LDDIMP), for example, the implanted ions may be phosphorus (P) ions, and the implantation concentration may be 2.2 × 103/cm2-2.5*103/cm2A depth of about
Preferably, in order to protect the gate during the first ion implantation, after step S11, the gate 105 may be subjected to a rapid thermal oxidation process to form an oxide layer (not shown) to prevent the gate 105 from being damaged by the ion implantation.
Referring to fig. 9-10, in step S13, a first mask layer 108 is formed on the N-well 101 and the gate 105 of the P-well 102, and a second ion implantation is performed on the P-well 102 to form second implantation regions 109 at two sides of the gate 105 in the P-well 102, where the first implantation ions and the second implantation ions are of the same type. This step is also the process of forming the NMOS.
Specifically, as shown in fig. 10, gate spacers 107 are formed on two sides of the gate 105. In order to obtain better MOS performance in the present invention, the gate spacers 107 on the N-well 101 and the P-well 102 may have different thicknesses (i.e., the lateral widths shown in fig. 10), so that the thickness D1 of the gate spacer 107 on the gate 105 side of the N-well 101 is smaller than the thickness D2 of the gate spacer 107 on the gate 105 side of the P-well 102. For example, the thickness D1 of the gate sidewall 107 on the gate 105 side of the P-well 102 is 90nm to 110nm, such as 100nm, and the thickness D2 of the gate sidewall 107 on the gate 105 side of the N-well 101 is 80nm to 90nm, such as 85 nm. The function of this design will be discussed in detail in step S15.
In this step, the first mask layer 108 may completely cover the N-well 101 (including the gate 105 and the gate sidewall 107), and only the gate 105 and the gate sidewall 107 are covered above the P-well 102. For better implantation, the thickness H1 of the first mask layer 108 at the P-well 102 is set to be
For example, can be
And the like. In this embodiment, the first mask layer 108 may be selected as a photoresist, so as to achieve protection of ion implantation and facilitate removal.
Further, in order to adjust the performance of the NMOS, the second ion implantation in this step may have a certain included angle (as shown in fig. 11).
The second ion implantation is to implant N-type ions, such as phosphorus, arsenic, etc., with an implant concentration of 2.8 x 103/cm2-3.2*103/cm2A depth of about
After the second ion implantation in this step, a second implantation region 109 may be formed in the P-well 102 as an N-type heavily doped region, and the doping concentration and implantation depth of the second implantation region 109 are greater than those of the first implantation region 106.
The step S14 of removing the first mask layer 108 can be performed by conventional processes, such as ashing and cleaning.
Referring to fig. 12, for step S15, a second mask layer 110 is formed on the P-well 102 and the gate 105 of the N-well 101, and a third ion implantation is performed on the N-well 101, so that the first implantation region 106 in the N-well 101 is transformed into a third implantation region 111, and fourth implantation regions 112 are formed on two sides of the gate 105 in the N-well 101, where the first implantation ion and the third implantation ion are of different types. This step is also the process of forming the PMOS.
In this embodiment, the second mask layer 110 may be selected as a photoresist, so as to achieve protection of ion implantation and facilitate removal.
It will be appreciated that the LDD structures (i.e. the first implanted region 106 and the third implanted region 111) in the N-well 101 and in the P-well 102 are not of the same doping type, and a first ion implantation performed previously has formed the first implanted region 106 in the N-well 101, so this step is first to achieve neutralization of the first implanted region 106 in the N-well 101 by a third ion implantation, and then to further transform the first implanted region 106 into the third implanted region 111.
To better achieve this, as mentioned above, the gate sidewall 107 at the N-well 101 is thinner, so as to ensure that the third ion implantation can affect the whole area where the first implantation region 106 is located.
In addition, the third ion implantation may be performed at an angle of 30 ° to 60 °, for example, 35 °, with respect to the normal of the upper surface of the front-end structure.
It is understood that the gate sidewall thickness, the mask layer thickness and the implantation angle may be selected or not according to actual requirements, and a plurality of conditions may be combined together.
Further, the thickness of the portion of the second mask layer 110 on the N-well 101 may be adjusted, so that the thickness of the second mask layer 110 on the gate 105 of the N-well 101 is smaller than the thickness of the first mask layer 108 on the gate 105 of the P-well 102. For example, the thickness H2 of the second mask layer 110 on the gate 105 of the N-well 101 is
Such as
And the like. Therefore, the shielding area for ion implantation is reduced, and better ion implantation can be realized.
The third ion implantation is to implant P-type ions, such as boron, gallium, etc., and the implantation concentration may be 1.5 × 104/cm2-1.8*104/cm2A depth of about
After the third ion implantation in this step, on one hand, a third implantation region 111 is formed, and on the other hand, a fourth implantation region 112 is also formed, where the third implantation region 111 is an LDD structure, the fourth implantation region 112 is used as an N-type heavily doped region, and a doping concentration and an implantation depth of the fourth implantation region 112 are greater than those of the third implantation region 111.
The step S16 of removing the second mask layer 110 can be performed by conventional processes, such as ashing and cleaning. After the removal, a structure as shown in fig. 13 can be obtained, and for the CMOS of the embodiment of the present invention, the CMOS includes a substrate 100, an N well 101 and a P well 102, where the N well 101 and the P well 102 are isolated by an isolation structure 103, a third implantation region 111 and a fourth implantation region 112 are formed in the N well 101, a first implantation region 106 and a second implantation region 109 are formed in the P well 102, a gate oxide layer 104 is formed on the N well 101 and on the P well 102, and a gate 105 and a gate sidewall 107 are formed.
Further, after removing the second mask layer, the method further includes: the annealing process can be completed by adopting a conventional process.
It is understood that the present invention is also applicable to adjust other MOS structures, for example, for LV/HVMOS process, it is also possible to adjust photoresist thickness or ion implantation angle to ensure the performance of one structure (for example, HVMOS) is complete, and in turn, adjust two LDD processes to ensure the performance of the other structure (for example, LVMOS) meets the requirement.
In summary, the method for fabricating a semiconductor structure provided by the present invention includes: providing a front-end structure, wherein the front-end structure is formed with a first type trap and a second type trap, and a grid electrode respectively positioned on the first type trap and the second type trap; performing first ion implantation on the front-end structure to form first implantation regions on two sides of a grid electrode in the first type well and the second type well respectively; forming a first mask layer on the first type trap and the grid electrode of the second type trap, carrying out secondary ion implantation on the second type trap, and forming second implantation areas on two sides of the grid electrode in the second type trap, wherein the ion type of the first implantation is the same as that of the second implantation; removing the first mask layer; forming a second mask layer on the second type trap and the grid electrode of the first type trap, and carrying out third ion implantation on the first type trap to convert a first implantation area in the first type trap into a third implantation area and form fourth implantation areas on two sides of the grid electrode in the first type trap, wherein the types of the first implantation ions and the third implantation ions are different; and removing the second mask layer. Therefore, the first injection region and the third injection region which are used as LDD can be formed through the first injection and the third injection, compared with the prior art, at least two layers of light masks of LDD can be saved, and at least two corresponding procedures are saved, so that the cost can be greatly saved, the manufacturing process is optimized, and the production period is shortened.
Moreover, the NMOS performance can be adjusted through the first ion implantation and the second ion implantation; through the first ion implantation and the third ion implantation, and further combining the thickness of the grid side wall, the thickness of the mask layer and the selection of the third ion implantation angle, the PMOS performance is adjusted, for example, the leakage current of the MOS structure is improved, so that the performance of the product is ensured.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (13)
1. A method for fabricating a semiconductor structure, comprising:
providing a front-end structure, wherein the front-end structure is formed with a first type trap and a second type trap, and a grid electrode respectively positioned on the first type trap and the second type trap;
performing first ion implantation on the front-end structure to form first implantation regions on two sides of a grid electrode in the first type well and the second type well respectively;
forming a first mask layer on the first type trap and the grid electrode of the second type trap, carrying out secondary ion implantation on the second type trap, and forming second implantation areas on two sides of the grid electrode in the second type trap, wherein the ion type of the first implantation is the same as that of the second implantation;
removing the first mask layer;
forming a second mask layer on the second type trap and the grid electrode of the first type trap, and carrying out third ion implantation on the first type trap to convert a first implantation area in the first type trap into a third implantation area and form fourth implantation areas on two sides of the grid electrode in the first type trap, wherein the types of ions implanted for the first time and the ions implanted for the third time are different, the thickness of a second mask layer on the grid electrode of the first type trap is smaller than that of a first mask layer on the grid electrode of the second type trap, and the angle of the third ion implantation is an included angle of 30-60 degrees with the normal direction of the upper surface of the front end structure;
and removing the second mask layer.
2. The method of fabricating a semiconductor structure of claim 1, wherein said well of the first type is an N-well and said well of the second type is a P-well.
3. The method of claim 2, wherein the first mask layer on the gate of the P-well has a thickness of
The thickness of the second mask layer on the grid electrode of the N trap is
4. The method of fabricating a semiconductor structure according to claim 2, wherein the second implanted region has a doping concentration and an implantation depth greater than those of the first implanted region; the doping concentration and the implantation depth of the fourth implantation area are larger than those of the third implantation area.
5. The method of claim 4, wherein the first ion implantation is a normal N-type ion implantation.
6. The method of claim 5, wherein the second ion implantation is an implantation of N-type ions and the third ion implantation is an implantation of P-type ions.
7. The method of fabricating a semiconductor structure according to claim 2, wherein after performing a first ion implantation on the front-end structure to form first implantation regions on both sides of the gate in the first-type well and the second-type well, respectively; forming a first mask layer on the gates of the first type well and the second type well, and before performing the second ion implantation on the second type well, the method further comprises:
and forming grid side walls on two sides of the grid.
8. The method of claim 7, wherein a thickness of the gate sidewall on the gate side of the well of the first type is less than a thickness of the gate sidewall on the gate side of the well of the second type.
9. The method of claim 8, wherein a thickness of the gate sidewall on the gate side of the well of the second type is 90nm to 110nm, and a thickness of the gate sidewall on the gate side of the well of the first type is 80nm to 90 nm.
10. The method of fabricating a semiconductor structure of claim 1, wherein said front end structure further comprises a gate oxide layer, said gate oxide layer being located on said well of the first type and said well of the second type, said gate being located on said gate oxide layer.
11. Such asThe method of fabricating a semiconductor structure of claim 10 wherein said gate oxide layer has a thickness of
12. The method of fabricating a semiconductor structure according to claim 1, wherein after providing a front-end structure, prior to performing a first ion implantation into the front-end structure, further comprising:
and carrying out rapid thermal oxidation treatment on the grid electrode.
13. The method of claim 1, further comprising, after removing the second mask layer:
and carrying out an annealing process.
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