DD269944A1 - METHOD FOR PRODUCING A HIGH-INTEGRATED SEMICONDUCTOR ARRANGEMENT WITH COMPLEMENTARY CIRCUIT STRUCTURE - Google Patents

Abstract

The invention relates to a method for producing a highly integrated semiconductor device having a complementary circuit structure, in which after the production of the transistor gates, a phosphor LDD implantation is performed. The method according to the invention is essentially characterized in that, after the field oxide regions have been formed on a semiconductor substrate of a first conductivity type to separate the transistor regions, well-shaped regions of a second conductivity type are introduced in the semiconductor substrate, gate oxide regions and transistor gates have been applied, a phosphor LDD implantation is carried out, Thereafter, a first protective barrier enclosing the transistor gates (first spacer) is produced by thermal oxidation, then a first resist mask covering the n-channel transistor regions is applied and a boron ion implantation is carried out, in which case the first resist mask is subsequently removed again an LP-CVD silicon dioxide layer is applied so that the LP-CVD silicon layer is removed again by subsequent over-coating, wherein on the side surfaces of the transistor gates a second spacer forming protective wall-shaped R est remains that subsequently applied to the p-channel transistor regions covering second resist mask and an arsenic ion implantation is performed and that after removal of the second resist mask, a healing of the source-drain regions is performed.

Description

6 9 9 4

Process for producing a highly integrated semiconductor device with complementary circuit structure

Field of application of the invention

The invention relates to a method for producing a highly integrated semiconductor device having a complementary circuit structure, in which, after the transistor gates have been produced, a phosphor LDD (lightly doped drain) implantation is carried out. The method is used in particular in the manufacture of integrated MOS circuits in GMOS silicon gate technology with a high integration density. "

Characteristic of the known state of the art

In order to enable integrated semiconductor arrangements with an ever higher packing density and a correspondingly further reduction of the transistor structures, it is known (DE 37 09 708, EP 189 914) to produce metal-oxide-semiconductor field-effect transistors in an LDD arrangement.

In such arrangements, lightly doped semiconductor layers having a conductivity type of the same conductivity with respect to the active layers (source, drain) are arranged on the circumference of these active layers. Here, the Fremdatomkonzentrations3piegel the circumferentially arranged layer regions is lower than that of the active layers, the production of these semiconductor devices is known (see IEEE Transaction on electron devices 29 (1982) 4 _, p.590 ff and IEEE Journal of Solid State circuits 20 (FIGS. 1985) 1, p.349)

2699

using an oxide sidewall spacer technology.

Thus, a method for producing a highly integrated semiconductor device having a complementary circuit structure is known, in which first thick field oxide regions are applied to a p-type silicon substrate for the purpose of initiating the transistor regions After introducing n-type annular regions into the silicon substrate A 20nm thick gate oxide layer is formed by thermal oxidation and a polysilicon layer is deposited, and then the polysilicon layer is patterned by a reactive ion etching process to form the transistor gates.

Thereafter, a one-dose phosphodial LDD implantation is performed

13 -2 · "

from 0.5 ... 5 · 10 cm and with an energy of 40 ...

100 KeV performed. In connection with this, a protective layer (spacer) enclosing the transistors is produced and a resist mask covering the p-channel transistors is applied. Now with a dose of 1 ....

15 -? 6 x 10 cm and an energy of 40 ... 100 KeV an arsenic ion implantation performed and after removal of the resist mask there is an annealing at a temperature of 900 ... 1000 ° 0th

Subsequently, a second resist mask, covering the n-channel;! -Transistors, is applied and boron ion implantation with BF _{2 is} performed. This boron ion implantation is performed with an energy of 40 ... " ¹ O KeV

15 -2 and a dose of 1 ... 6 x 10 cm.

Finally, the thus generated source-drain regions are annealed and completed the integrated semiconductor device in a known manner.

A disadvantage of this process, which can also be referred to as a single-spacer technology, is the short spacer length of 100 to 200 nm, which is due to the low p ⁺ (boron) penetration depth.

This leads to a low short-circuit withstand voltage, a high field strength at the drain edge, a large hot electrore effect and a strong avalanche effect, which negatively influences the yield of this production method. Furthermore, a method is known in which the LDD phosphor implantation is carried out via a protective oxide of the transistor gate, whereby an improvement of the overlapping capacity pn is achieved. However, the disadvantages of the known production methods are also not avoided by this method 1 »

Object of the invention

The object of the invention is a method for producing a highly integrated semiconductor device with complementary circuit structure, in which a high yield, by avoiding a high field strength at the drain edge, a low short-channel Spannungscfestigkeit and by preventing large hot electron effects and strong Avalanche effects in the n-channel transistor, without highü economic effort is guaranteed.

Explanation of the essence of the invention

The invention is based on the object, a method for producing a hoc hinter egriert egg. Semiconductor arrangement with

To provide complementary circuit structure, which ensures a low penetration depth in the p ⁺ ion implantation of the p-channel transistors while allowing the introduction of the source-drain regions of the n-channel transistors via a Spacar with a sufficiently large Lan ^ e.

According to the invention, the object is achieved in that after the on a semiconductor substrate of a first. Conductor type thick field oxide regions formed to separate the transistor regions, trough-shaped regions of a second conductivity type introduced in the semiconductor substrate, gate oxide regions and transistor gates were applied, a phosphor LDD implantation with a dose of 0.5 ... 5 · 10 ¹ - ⁵ cm " ² and an energy of 40 ..100 KeV is carried out and that thereafter a first protective barrier enclosing the transistor gates (first spacer) is produced by a thermal oxidation at a temperature of about 800 ° C. Subsequently, the regions of the transistors with n Applied first channel-mask covering resist mask and carried out a boron ion implantation with a dose of 1 ... 6 x 10 cm "and an energy when using BPp of 30 ... 100 KeV, followed by the first Lackm ^ each one was removed and a 100 to 250 nm thick silica layer was deposited by an LP-CVD method.

By subsequent overetching, in particular by a reactive ion etching process, the silicon dioxide layer is removed again. It remains on the side surfaces of the Trahsistorgates a second spacer forming protective wall-shaped remainder of the LP-CVD silicon dioxide: ldschicht. Now, a second resist mask is applied covering the transistor regions with p-channel regions. With

15 -2 a dose of 1 ... 6 x 10 cm and an energy of

2 6 9 9

30 ... 100 KeV is then performed an arsenic ion implantation.

After the second resist mask has been removed, annealing of the source-drain regions is carried out at a temperature of 900-950 ° C. and, finally, the semiconductor order is completed in a known manner. By tfas inventive method is achieved that in a complementary CMOS technology, the n- and p-channel transistors can be set completely separate.

It is obvious that both ρ- or n-type semiconductor substrates with n- or p-well regions as well as double-well techniques can be used.

embodiment

The inventive method for producing a highly integrated semiconductor device with complementary circuit structure will be explained below with reference to an exemplary embodiment. 1 shows the layer structure during boron implantation FIG. 2 shows the layer structure during the Araan implantation

Thick field oxide regions 2 are first formed on a p-type silicon substrate 1 to separate the transistor regions, and trough-shaped regions 3 are introduced into the silicon substrate 1. Subsequently, gate oxide regions 4 and transistor gates 5 with corresponding channel doping are produced by applying a 20 nm thick silicon dioxide layer, a channel implantation, a deposition of a polysilicon layer, a structuring of the polysilicon layer by reactive ion etching.

This will be followed by a phosphor LDD implantation

13 -2 carried out with a dose of 1.5 x 10 cm and an energy of 60 KeV. After a kuczen oxide over-acidification, a silicon dioxide layer 6 is grown by thermal oxidation at a temperature of 800 ° G covering the surface of the polysilicon regions (transistor gates) 5 having a thickness of 120 nm and the silicon substrate surface having a thickness of 30 nm.

This silicon dioxide layer 6 enclosing the transistor gates 5 forms the first spacer. After the application of a first resist mask 7 covering the regions of the n-channel transistors, a boron mask is deposited.

1 ion implantation using BP ₀ at a dose of 5 * 10

-2 cm and an energy of 50 KeV. In this case, the previously formed first spacer ensures a sufficient channel length of the short channel transistors, wherein the LDD phosphor is securely covered and no connection problems occur. Subsequently, the resist mask is removed again and a 150 nm thick silicon dioxide layer is deposited by means of an LP-CVD process. Subsequently, the silicon dioxide layer is replaced by a reactive silicon dioxide layer

Ion etching removed again, wherein on the side surfaces of the enclosed by the silicon dioxide layer 6 transistor gates 5 a protective barrier (second spacer 8) of 150 nm remains. Now the p-channel transistor regions are covered by a second resist mask 9 and an arsenic ion implantation is performed. In this implantation, the second spacer 8 separates the location of the arsenic implant from that of the boron implant, thereby reducing the Racdfeidstärke at the drain sufficiently for the n-channel transistor wD.rd.

After the arsenic ion implantation, with one dose

15 -2 of 5 χ 10 cm and an energy of 50 KeV, the second resist mask 9 is removed again and then carried out a healing of the source-drain regions at a temperature of 900 ° G. Following this 30 minute annealing, the semiconductor device with complementary circuit structure is completed in a known manner.

Claims (4)

9 9 4 Claim A method of manufacturing a highly integrated semiconductor device having a complementary circuit structure on a semiconductor substrate of a first conductivity type wherein thick field oxide regions are formed to separate the transistor regions, trough-shaped regions of a second conductivity type are inserted in the semiconductor substrate, gate oxide regions and transistor gates are formed with corresponding channel doping, and source-drain regions be formed and finally dip semiconductor device is completed, characterized in that after generating the transistor gates a phosphor LDD implantation (lightly doped drain implantation) is performed, that thereafter by a thermal oxidation at a temperature of about 800 ° G, a transistor gates enclosing first Schutawall (first spacer) is generated, then applied to the areas covering a transistor with n-channel regions covering first resist mask and completed a boron ion implantation After this, the resist mask is removed and an insulating layer completely covering the surface of the semiconductor substrate is deposited, the insulating layer subsequently being removed by an overetching, a second protective barrier being provided on the sides of the transistor gates enclosed by the first protective layer. second spacer), thereafter covering the regions of the p-channel region transistors with a second resist mask and performing an arsenic ion implantation, followed by removing the second resist mask an annealing of the generated source-drain Gebieuo in one becomes. a temperature of about 850 .. · 950 ° C carried out 2. The method according to claim 1, characterized in that the phosphor LDD implantation with a dose of 0 | 5 ... 5 · ΊΟ ¹³ cm " ² and
is carried out, 5 · 10 cm " ² and with an energy of 40 ... 100 KeV 3. The method according to claim 1, characterized in that the ion implantation of boron with a dose of .1 ... 15 -2
10 cm and when using 30 ... 100 KeV is performed. 15 -2
10 cm and when using BP ₂ with an energy 4. The method according to claim 1, characterized in that the arsenic ion implantation with a dose of 1 ... 6 10 ⁵ cm " ² and with an energy of 30 ... 100 KeV is performed. - For this 1 sheet drawings -