JPH06318698A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce an increase in delay time of an element due to an increase in a gate capacitance, to reduce a rise in a threshold voltage due to a substrate bias voltage and to prevent a substrate punchthrough phenomenon. CONSTITUTION:Highly doped P-layers 4n extended to the lower part of an N<-> source/drain region 2 are formed in both end parts on the surface of a channel region. In addition, highly doped P-layers 4a are formed in parts in the boundary region between an N<+> source/drain region 3 and the N<-> source/ drain region 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a MOS (Metal Oxi).
The present invention relates to a semiconductor device having a de Semiconductor transistor and a method for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a MOS has been used as one of semiconductor devices.
Transistors are known. FIG. 46 shows a conventional MOS
It is sectional drawing which showed the transistor. Referring to FIG. 46, in the conventional MOS transistor, N ⁻ source / drain regions 202 are formed on the main surface of P type semiconductor substrate 201 with a predetermined space therebetween so as to sandwich channel region 204. Then, a pair of N ⁺ source / drain regions 203 are formed so as to be continuous with the N ⁻ source / drain regions 202. A gate electrode 206 is formed on the channel region 204 via a gate oxide film 205. Sidewall oxide films 207 are formed on both side wall portions of the gate electrode 206.

47 to 50 are sectional structural views for illustrating a manufacturing process of the conventional MOS transistor shown in FIG. 46 to 50, a conventional MOS transistor manufacturing process will be described.

First, as shown in FIG. 47, boron is applied to a P-type silicon substrate at 670 keV, 2 × 10 ¹³ / cm ² and 8
Ions are implanted under the conditions of 0 keV and 1 × 10 ¹³ / cm ² to form a P-type well (not shown). After that, for example, boron is ion-implanted into the channel under the conditions of 30 keV and 1 × 10 ¹³ / cm ² . This forms a channel (not shown).

Next, as shown in FIG. 48, after a gate oxide film layer 205a made of a silicon oxide film is formed on the entire surface of the P-type silicon substrate 201, the gate oxide film layer 20 is formed.
A polysilicon layer 206a is formed on 5a. And
The polysilicon layer 206a and the gate oxide film layer 205a are patterned by using the photoengraving technique and the dry etching technique. As a result, the gate oxide film 205 and the gate electrode 205 as shown in FIG. 49 are formed. Then, using the gate electrode 206 as a mask, boron ions are implanted under the conditions of 30 keV and 4 × 10 ¹³ / cm ² . As a result, N ⁻ source / drain regions 203 are formed.

Next, as shown in FIG. 50, after forming an oxide film (not shown) on the entire surface, anisotropic etching is performed to form a sidewall film 207. Arsenic is added to the P-type silicon substrate 201 at 50 keV, 1 × using the sidewall film 207 and the gate electrode 206 as a mask.
Ion implantation is performed under the condition of 10 ¹⁵ / cm ² . As a result, N ⁺ source / drain regions 203 are formed. In this way, the basic structure of the N-type MOSFET as shown in FIG. 46 is formed.

By the way, in order to realize a high-density integrated circuit, miniaturization of elements is being advanced. One of the advantages of miniaturization is that the operating speed of the device can be increased. In such miniaturization, if the gate length of the MOSFET is shortened to 1 μm or less, a phenomenon that the threshold voltage is lowered is observed. This is called the short channel effect. Dennard et al. Have proposed a method (scaling rule) of miniaturizing an element without changing the threshold voltage in order to prevent such a short channel effect.
These are, for example, [R. H. Dennard, F.M.
H. Gaensslen, H .; N. Yu, V. L. Ri
deout, E.I. Bassous, and A. R. Le
Blanc, IEEE J. Solid-State
Circuits, SC-9, 256 (1974). ]
Etc. are disclosed.

Table 1 below summarizes the other device structural parameters when the gate length is 1 / K and the electrical characteristics of the miniaturized device.

[0009]

[Table 1]

With reference to Table 1 above, according to this scaling rule, when the gate length is 1 / K, the delay time per circuit, which is the operating speed of the element, becomes 1 / K, and the gate capacitance becomes 1 / K. It turns out that

However, in reality, the operating voltage of the element is TTL (T
transistor-Transistor Logi
c) It is fixed at the level (5V or 3.3V).
Therefore, the above scaling rule does not hold as it is. That is, in the prior art, since the drain voltage is high, the channel impurity concentration is higher than the scaling rule (1 × 10 ¹⁷ / c) in order to suppress the decrease in the threshold voltage.
m ^{3 to} 5 × 10 ¹⁷ / cm ³ ).

Operating speed of element (delay time per circuit)
Is represented by CV / I = CR as shown in Table 1.
Here, C is the gate capacitance, V is the voltage, I is the current, and R is the resistance. Therefore, as one method of increasing the speed of the device, it is conceivable to reduce the gate capacitance C. The gate capacitance C is expressed by the following equation (1).

[0013]

[Equation 1]

Here, C is the gate capacitance, C ₀ is the capacitance of the gate oxide film per unit area, K ₀ is the relative permittivity of the oxide film,
K _S is the relative permittivity of silicon, ε ₀ is the permittivity in vacuum,
V _G is the gate voltage, q is the unit charge amount, _tox is the oxide film thickness,
N _A is the channel impurity concentration. From the above formula (1),
It can be seen that the gate capacitance C increases as the channel impurity concentration N _A increases. In fact, as described above, since the channel impurity concentration N _A is made high in order to suppress the decrease in the threshold voltage, the gate capacitance C becomes large even if the element is miniaturized. Therefore, there is a problem that the delay time per circuit becomes long.

The threshold voltage V _{TH of the} MOSFET is expressed by the following equation (2).

[0016]

[Equation 2]

Referring to the above equation (2), V _FB is a flat band voltage, φ _F is a Fermi level, C _ox is a gate oxide film capacitance, and V _sub is a substrate bias voltage. This formula (2)
As can be seen from the above, the thicker the gate oxide film, the smaller the gate oxide film capacitance C _ox , and the larger the increase rate of the threshold voltage V _TH due to the substrate bias voltage V _sub . Therefore, by applying the substrate bias voltage V _sub , the threshold voltage V _TH of the parasitic MOS transistor in the element isolation region made of a thick oxide film can be significantly increased over the threshold voltage of the MOS transistor in the element region. it can. As a result, the leak current between elements due to the parasitic MOS transistor can be significantly reduced. For these reasons, the method of applying the substrate bias voltage V _sub is
Widely used in transistor LSIs.

[0018]

However, as described above, the channel impurity concentration N _A is conventionally made high in order to suppress the decrease in the threshold voltage V _TH . For this reason,
As can be seen from the coefficient (substrate effect constant) of the substrate bias voltage V _{sub in} the above equation (2), the change in the threshold voltage V _TH due to the substrate bias becomes large. As a result, there is a problem that the threshold voltage V _TH becomes too high.

Further, in order to prevent substrate punch-through which is a phenomenon in which a drain current flows when the gate voltage is lower than the threshold voltage, it is necessary to suppress the extension of the depletion layer in the source / drain regions. Therefore, in the past,
The method of making the junction depth of the source / drain regions shallow has been adopted. Specifically, it was formed to a junction depth of about 0.08 μm.

However, when the junction depth is made shallow as described above, the resistance R of the source / drain regions becomes large, so that the delay time of the element (delay time per circuit) becomes long. Here, when salicide is used when the junction depth of the source / drain region is shallow, the source / drain resistance is 10Ω or less, and the resistance can be reduced even if the junction depth is shallow. However, the source /
There is a problem that defects occur in the drain region, which causes leakage.

As described above, in the conventional semiconductor device having the MOS transistor, the channel impurity concentration is made high in order to suppress the decrease in the threshold voltage when the element is miniaturized, so that the gate capacitance becomes large. There is a problem that the delay time per circuit becomes large. Further, there is a problem that when the substrate bias voltage is applied to increase the channel impurity concentration, the change in the threshold voltage becomes large, resulting in the threshold voltage becoming too high. Further, since the junction depth of the source / drain regions is made shallow in order to prevent the substrate punch-through, the source / drain resistance becomes high and the delay time of the device becomes long.

The present invention has been made in order to solve the above problems, and it is possible to suppress an increase in gate capacitance due to an increase in channel impurity concentration even when an element is miniaturized, and a substrate. It is an object of the present invention to provide a semiconductor device capable of reducing a change in threshold voltage when a bias voltage is applied, and further capable of reducing source / drain resistance while preventing substrate punch-through, and a manufacturing method thereof. To do.

[0023]

According to another aspect of the present invention, there is provided a semiconductor device, wherein a semiconductor region of a first conductivity type having a main surface is provided with a predetermined interval so as to sandwich a channel region on the main surface of the semiconductor region. A pair of source / drain regions of the second conductivity type formed separately from each other, and a first high type of the first conductivity type formed in a part of the channel region and extending deeper than the source / drain regions. The semiconductor device includes a concentration impurity region and a gate electrode formed on the channel region with a gate insulating layer interposed therebetween.

Further, preferably, a second high-concentration impurity region of the first conductivity type may be further formed in at least one of the pair of source / drain regions described above.

According to another aspect of the semiconductor device of the present invention, a semiconductor region of the first conductivity type having a main surface and a second conductivity type formed on the main surface of the semiconductor region with a predetermined distance therebetween so as to sandwich a channel region. A pair of source / drain regions, a high-concentration impurity region of a first conductivity type formed in at least one of the pair of source / drain regions, and a channel region formed under the source / drain regions. A buried oxide layer having an opening below.

According to a fourth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming a gate electrode on a main surface of a semiconductor region of the first conductivity type via a gate insulating layer, and a method of manufacturing the first conductivity type using the gate electrode as a mask. Forming a high-concentration impurity region of a first conductivity type having a first depth in a part of a region where a channel region of a semiconductor region is formed by introducing an impurity; and forming a channel on a main surface of the semiconductor region. And forming a pair of source / drain regions of the second conductivity type having a second depth that is shallower than the first depth at a predetermined interval so as to define the region.

According to a fifth aspect of the method of manufacturing a semiconductor device, a step of forming a gate electrode on the main surface of the first conductivity type semiconductor region via a gate insulating layer, and oxygen ions in the semiconductor region using the gate electrode as a mask. To form a buried oxide layer having an opening under the gate electrode by performing a heat treatment on the main surface of the semiconductor region so that the channel region is located under the gate electrode. The method includes forming a pair of source / drain regions of the second conductivity type and forming a high-concentration impurity region of the first conductivity type in at least one of the pair of source / drain regions.

[0028]

In the semiconductor device according to the first and second aspects, since the first high-concentration impurity region of the first conductivity type is formed only in a part of the channel region, the conventional high-concentration impurity region is formed over the entire surface of the channel region. The increase in the gate capacitance is reduced as compared with the case of forming. As a result, an increase in delay time per circuit due to an increase in gate capacitance is suppressed as compared with the conventional case. At the same time, the change in the threshold voltage due to the application of the substrate bias voltage is suppressed. Further, since the above-described first high-concentration impurity region is formed to extend deeper than the source / drain regions, extension of the depletion layer in the source / drain regions is suppressed. This effectively prevents the substrate punch-through phenomenon.

If a second high-concentration impurity region of the first conductivity type is further formed in at least one of the pair of source / drain regions described above and is used together with the first high-concentration impurity region, the threshold value is increased. It becomes easier to control the value voltage.

In the semiconductor device according to the third aspect, since the high-concentration impurity region of the first conductivity type is formed in at least one of the pair of source / drain regions, the first conductivity type is formed over the entire surface of the conventional channel region. An increase in gate capacitance is suppressed as compared with the case where a high concentration impurity region of a mold is formed. This suppresses an increase in delay time per circuit. At the same time, the change in the threshold voltage due to the substrate bias voltage is also suppressed. Further, since the buried oxide layer having an opening under the channel region is formed under the source / drain region, extension of the depletion layer from the source / drain region is suppressed. This effectively prevents the substrate punch-through phenomenon.

In the method of manufacturing a semiconductor device according to a fourth aspect, the first conductivity type impurities are introduced into at least a part of a region where a channel region of the semiconductor region is formed by introducing impurities of the first conductivity type using the gate electrode as a mask. Since the high-concentration impurity region of is formed,
An increase in gate capacitance is suppressed as compared with the case where a conductive high concentration impurity region is formed. This suppresses an increase in delay time per circuit. At the same time, the change in the threshold voltage due to the application of the substrate bias voltage is also suppressed. Further, since the high-concentration impurity region is formed to have the first depth deeper than the second depth of the source / drain region, the substrate punch-through phenomenon of the source / drain region is effectively prevented.

In the method of manufacturing a semiconductor device according to the fifth aspect, oxygen ions are implanted into the semiconductor region using the gate electrode as a mask and heat treatment is performed to form a buried oxide layer having an opening below the gate electrode. Therefore, the buried oxide layer suppresses the extension of the depletion layer in the source / drain regions. This effectively prevents the substrate punch-through phenomenon. In addition, since the first-conductivity-type high-concentration impurity region is formed in at least one of the source / drain regions, compared with the conventional case where the first-conductivity-type high-concentration impurity region is formed over the entire surface of the channel region. The increase in capacity is suppressed. This also suppresses an increase in delay time per circuit. At the same time, the change in the threshold voltage due to the application of the substrate bias voltage is also suppressed.

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structural view showing a MOS transistor according to an embodiment of the present invention. Referring to FIG. 1, in the MOS transistor according to the first embodiment, a pair of N ^- source / pair of N ^- source / The drain region 2 is formed. Inside the N ⁻ source / drain region 2, a pair of N ⁺ source / drain regions 3 are formed. On the main surface of the P-type silicon substrate 1 located in the boundary region between the N ⁺ source / drain region 3 and the N ⁻ source / drain region 2, a pair of P having a high impurity concentration is formed.
The layer 4a is formed.

A pair of channel P layers 4b having a high impurity concentration are formed at both ends of the channel region 8. The channel P layer 4b is formed so as to extend deeper than the N ⁻ source / drain region 2. A gate electrode 6 is formed on the channel region 8 via a gate oxide film 5. Sidewall films 7 are formed on both side wall portions of the gate electrode 6.

In the first embodiment, the channel P layer 4b is formed only in a part of the channel region 8 instead of in the whole region, so that the gate P layer 4b having a high concentration is formed in the whole channel region. The increase in capacity can be reduced. As a result, it is possible to effectively eliminate the inconvenience that the delay time per circuit increases due to the increase in the gate capacitance. Such an effect is also applicable to the P layer 4a. The reason why the gate capacitance can be reduced in the first embodiment as compared with the conventional case where a high concentration P layer is formed over the entire channel region will be described.

FIG. 2 is a schematic diagram used to calculate the gate capacitance of the first embodiment shown in FIG. FIG. 3 is FIG.
It is an equivalent circuit diagram corresponding to. First, referring to FIG. 2, in this schematic diagram, the gate capacitance is composed of the gate capacitances of three capacitors existing in three regions under the gate oxide film 5. That is, one P layer 4a, one capacitor formed in the region consisting of the N ⁻ source / drain region 2 and the channel P layer 4b, and the other channel P layer 4b, N ^−.
Another source / drain region 2 and P layer 4a
It is composed of three capacitors, one capacitor and another capacitor formed in the central region where the channel P layer 4b, the N ⁻ source / drain regions 2 and the P layer 4a are not present. Here, as shown in FIG.
The capacitance of each of the above-mentioned three capacitors is the capacitance C _{1 in} which the gate oxide film capacitance 11 and the gate-substrate capacitance 14 are connected in series, and the capacitance C in which the gate oxide film capacitance 12 and the gate-substrate capacitance 15 are directly connected. ₂ and a capacitance C _{3 in} which the gate oxide film capacitance 13 and the gate-substrate capacitance 16 are connected in series. Therefore, the total gate capacitance C is represented by the following equation (3), since the above-mentioned capacitances C ₁ , C ₂ and C ₃ are connected in parallel.

[0038]

[Equation 3]

Then, substituting the values calculated according to the equation (1) for the capacitances C ₁ , C ₂ and C ₃ of the above equation (3),
It becomes like the following formula (4).

[0040]

[Equation 4]

Referring to the above equation (4), the above three
The gate oxide film capacitance per unit area of the capacitor is the gate
Since the oxide film 5 is common, the same value C₀become. That
, N _A1, N_A3Are both P layers 4a and N^-Sauce / drain
Average the impurity concentrations of the in region 2 and the channel P layer 4b
Impurity concentration,_A2Is an impurity in the center of the channel
The concentration. From the above formula (4), high concentration over the entire channel
Higher concentration P in a part of the channel than in the case of forming a P layer
It can be seen that the total gate capacitance C decreases when the layer is formed.
It That is, N_A1, N_A3Only high concentration, N_A2Is low
N is the degree_A1, N_A2, N_A3I will make all of the high concentration
It can be seen that the total gate capacitance C decreases. By this
And high-speed MOSFE with shorter delay time
T can be realized.

Further, in the first embodiment, the impurity concentration N _A2 at the center of the channel is made relatively low, and only the impurity concentrations N _A1 and N _{A3 at} both ends of the channel are made high so that the entire conventional channel can be obtained. The fluctuation of the threshold voltage due to the substrate bias can be reduced as compared with the case of increasing the concentration. That is, according to the above-mentioned formula (2), the threshold voltage V _TH increases as the square root of the product of the substrate bias voltage V _sub and the channel impurity concentration N _A increases. In this embodiment, the channel impurity concentration N _A is smaller than that in the conventional case where the entire channel is made high in concentration. As a result, it is possible to reduce the fluctuation of the threshold voltage due to the substrate bias voltage V _sub as compared with the conventional case. As a result, the increase in the threshold voltage can be reduced as compared with the conventional case where the entire channel has a high concentration.

Further, in this embodiment, as shown in FIG.
The high concentration channel P layer 4b to N ^-Source / drain
Forming deeper than region 2 (about 0.4 μm)
Therefore, the extension of the depletion layer from the drain region to the source region
Can be prevented. As a result, substrate punch through
The phenomenon can be effectively prevented. As a result,
Like N^-Source / drain regions 2 and N⁺Source
/ It is not necessary to make the junction depth of the drain region 3 shallow. This
Therefore, source / drain regions 2 and 3 are formed as in the conventional case.
The resistance value of the
There is no inconvenience that the delay time of is long.

4 to 8 are sectional structural views for explaining the manufacturing process of the MOS transistor of the first embodiment shown in FIG. A manufacturing process of the MOS transistor of the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 4, gate oxide film layer 5a and nitride film 9 are formed on the main surface of P type silicon substrate 1.

Next, as shown in FIG. 5, the nitride film 9 located in the gate region is removed by anisotropic etching. Then, a polysilicon layer 6a is formed on the entire surface. As a result, the concave portion on the gate region is filled. Polysilicon layer 6
After forming a resist 10 in a predetermined region on a, anisotropic etching is performed to form a gate oxide film 5 and a gate electrode 6 as shown in FIG. Then, using the resist 10 as a mask again, on the P-type silicon substrate 1,
Impurities are ion-implanted twice. For example, 0.
In case of 3 μm transistor, 70 keV, 1 × 10 ¹³ /
Ion implantation is performed in two steps of cm ² and then 20 keV and 3 × 10 ¹³ / cm ² . The former ion implantation is for preventing substrate punch-through, and the latter ion implantation is for controlling the threshold voltage. As a result, the P layer 4 having a depth of about 0.4 μm is formed. After that, the nitride film 9 and the resist 10 are removed.

Next, as shown in FIG. 7, using the gate electrode 6 as a mask, for example, arsenic ions are added at 30 keV, 1 × 1.
Oblique rotation ion implantation is carried out at 45 ° under the condition of 0 ¹³ / cm ² . The advantage of this oblique rotation ion implantation is that when the impurity distribution of arsenic is observed in the horizontal direction of the channel (direction parallel to the gate oxide film 5), the oblique implantation is gentler than the implantation at 0 °. This is the point where the concentration changes. Figure 9
FIG. 4 is a distribution diagram showing an impurity distribution by a Monte Carlo method when ion implantation is performed in the vertical direction. With reference to FIG. 9, it can be seen that the impurity distribution changes more gently in the oblique direction (direction shown by b in the figure) than in the direction perpendicular to the implantation direction (direction shown by a in the figure). . Therefore, it can be seen that the impurity concentration in the horizontal direction of the channel changes more gently when the ions are injected from the oblique direction than when the ions are injected from the vertical direction. By using the oblique rotation ion implantation method as described above, the electric field in the horizontal direction of the channel can be relaxed, and the MOS due to the drain avalanche hot carrier generated near the drain is formed.
It is possible to prevent deterioration of the transistor. If the N ⁻ source / drain regions 3 are formed in this manner, as shown in FIG.
The original P layer 4 shown in FIG. 2 is divided into a P layer 4a and a channel P layer 4b as shown in FIG.

Next, as shown in FIG. 8, an oxide film (not shown) is deposited on the entire surface and then anisotropically etched to form a sidewall film 7. Then, by using the sidewall film 7 and the gate electrode 6 as a mask, arsenic ions are obliquely rotated and implanted at 50 keV and 4 × 10 ¹⁵ / cm ² at 7 ° to form the N ⁺ source / drain regions 3. The source / drain region 2
The heat treatment to activate 3 and 3 is, for example, 85
It is carried out at 0 ° C. for about 20 minutes in a nitrogen atmosphere. In this way, the MOS transistor of the first embodiment as shown in FIG. 1 is formed.

FIG. 10 shows an MO according to the second embodiment of the present invention.
It is a cross-section figure which showed the S transistor. Referring to FIG. 10, in the second embodiment, unlike the first embodiment shown in FIG. 1, buried P layer 17 is formed below N ⁺ source / drain region 23. Further, the N ⁻ source / drain region 22 is formed of the sidewall film 7 and the gate oxide film 5.
Is formed only in the region located below.

In the second embodiment, as described above, the embedded P
By forming the layer 17, the operation of the parasitic MOS transistor in the element isolation region can be suppressed in addition to the effect of the first embodiment described above. That is, FIG.
Although not shown in the figure, an element isolation region exists on the right side of the N ⁺ source / drain region 23. And the buried P layer 1
7 functions as a channel stopper for the parasitic MOS transistor in the element isolation region. This allows
The parasitic MOS transistor in the element isolation region becomes difficult to operate, and a latch-up resistant structure is obtained.

11 to 15 are sectional structural views for explaining the manufacturing process of the MOS transistor of the second embodiment shown in FIG. Next, the manufacturing process of the MOS transistor of the second embodiment will be described with reference to FIGS. First, the process shown in FIGS. 11 to 13 is the same as the manufacturing process of the first embodiment shown in FIGS. After this, as shown in FIG.
The buried P layer 17 is formed by ion implantation under the conditions of V and 5 × 10 ¹² / cm ² . Then, the arsenic ions are exposed to 45 ° under the conditions of 30 keV and 1 × 10 ¹³ / cm ² .
Diagonally rotate ion implantation. This allows N ^- source /
The drain region 22 is formed. After that, the resist 10 is removed.

Next, as shown in FIG. 15, a sidewall film 7 is formed by depositing an oxide film (not shown) on the entire surface and then performing anisotropic etching. Arsenic ions are obliquely ion-implanted at 7 ° under the conditions of 50 keV and 4 × 10 ¹⁵ / cm ^{2 using} the sidewall film 7 and the gate electrode 6 as a mask. As a result, N ⁺ source / drain regions 23 are formed. The buried P layer 17 contains boron ions at 120 keV after the sidewall film 7 is formed.
It can also be formed by oblique rotary ion implantation at 10 ° under the condition of 6 × 10 ¹² / cm ² . In this way, the MOS transistor of the second embodiment is formed.

FIG. 16 shows an MO according to the third embodiment of the present invention.
It is a cross-section figure which showed the S transistor. Referring to FIG. 16, in the third embodiment, channel P layer 24 is formed so as to cover the entire surface of N ⁻ source / drain region 2. With this structure, the substrate punch-through phenomenon can be prevented more effectively than in the first embodiment shown in FIG.

FIG. 17 shows the M of the third embodiment shown in FIG.
FIG. 6 is a cross-sectional structure diagram for explaining the manufacturing process of the OS transistor. Referring to FIG. 17, MOS of the third embodiment
The manufacturing process of the transistors, 20 keV, boron using the resist 10 as a mask 4 × 10 ¹³ / cm ²
Ion implantation is performed under the conditions of. Thereby, the P layer 4a is formed. Next, boron is also used at 90 keV, 5 × 10 ¹²
By injecting under the conditions of / cm ^2, the channel P
Form layer 24. Then, phosphorus is added at 30 keV, 1 × 1
Injection under the condition of 0 ¹³ / cm ² . As a result, N ⁻ source / drain regions 2 are formed. When the N ⁻ source / drain region 2 is formed by oblique rotation ion implantation, arsenic ions are added at 30 keV, 1 × 10 ¹³ / cm 3.
Oblique rotation ion implantation at 45 ° under the condition of ² .

After that, as shown in FIG. 16, after forming the sidewall film 7, arsenic is obliquely rotated at 7 ° under the conditions of 50 keV and 4 × 10 ¹⁵ / cm ^{2 using} the sidewall film 7 as a mask. Ion implantation. This gives N ⁺
Source / drain regions 3 are formed. The channel P
The layer 24 can also be formed by implanting boron ions by the oblique rotation ion implantation method after forming the sidewall film 7. In this way, the MOS transistor according to the third embodiment is formed.

FIG. 18 shows an MO according to the fourth embodiment of the present invention.
It is a cross-section figure which showed the S transistor. See Figure 18
In comparison, in the fourth embodiment, the P-type silicon substrate 31
The main surface has a recess 31a. And in the recess
On the bottom channel region 37 via the gate oxide film 35
The gate electrode 36 is formed. In addition, the recess 31a
The channel region 37 is sandwiched between the bottom portion and the side wall portion.
N at predetermined intervals ^-Source / drain region 32 is shaped
Is made. The upper surface of the recess 31a has N^-Sauce / do
N to connect to rain area 32⁺Source / drain
A region 33 is formed. Both ends of the channel region 37
A channel P layer 34b is formed correspondingly. N^-Saw
A P layer 34a is formed on the surface region of the drain / steam region 32.
Has been done.

Thus, in the fourth embodiment, the recess 3
N using the top and side surfaces of 1a ⁺Source / drain
Region 33 and N^-Source / drain regions 32 are formed
Therefore, as compared with the above-described first to third embodiments,
A pair of N⁺Distance between the source / drain regions 33, 33
The separation becomes longer. As a result, the depletion layer is removed from the drain region.
It becomes difficult to reach the source area by extending and punch through the substrate.
The phenomenon can be prevented more effectively. Also this this
In the structure of the four embodiments, N⁺Of the source / drain region 33
The junction depth is the depth of the recess 31a, for example, about 0.3 μm.
You can go deep. By this, N⁺Source/
The resistance of the drain region 33 is the above-mentioned first to third embodiments.
It can be made smaller than that of the embodiment. As a result, the element
The delay time can be shortened.

19 to 22, the fourth portion shown in FIG.
FIG. 6 is a cross-sectional structure diagram for explaining the manufacturing process of the MOS transistor of the example. With reference to FIGS. 19 to 22,
Next, the manufacturing process of the MOS transistor of the fourth embodiment will be described.

First, as shown in FIG. 19, arsenic ions of 100 keV are applied to the entire main surface of the P-type silicon substrate 31.
7 × 10 ¹⁵ / cm ² and arsenic ion at 50 keV, 1 × 1
Two ion implantations of 0 ¹⁵ / cm ² are performed. Thus, the N ⁺ source / drain regions 33 to be described later N ⁺
Form the layer 33a. After that, a resist 38 is formed in a predetermined region on the N ⁺ layer 33a. When the gate length is 0.3 μm, the resist 38 is formed so as to have an opening of 0.4 μm. Then, using the resist 38 as a mask, a silicon-based gas is caused to flow, and anisotropic etching is performed while depositing silicon on the side wall. Thereby, the recess 31a as shown in FIG. 20 is formed. After that, the resist 38 is removed.

Next, as shown in FIG. 21, a gate oxide film layer (not shown) and a polysilicon layer (not shown) are formed on the entire surface, and then a resist 39 is formed on the polysilicon layer. The gate electrode 36 formed of the gate oxide film 35 and the polysilicon layer is formed by anisotropically etching the polysilicon layer and the gate oxide film layer using the resist 39 as a mask. Further, phosphorus is obliquely ion-implanted at 45 ° under the conditions of 30 keV and 1 × 10 ¹³ / cm ^{2 using} the resist 39 as a mask. As a result, N ^-
Source / drain regions 32 are formed.

Next, as shown in FIG. 22, by using the resist 39 as a mask, boron ions are obliquely ion-implanted in two steps, low energy and high energy, to form a P layer 34a and a channel P layer 34b. To do.
In this way, the MOS transistor of the fourth embodiment is completed.

FIG. 23 shows an MO according to the fifth embodiment of the present invention.
It is a cross-section figure which showed the S transistor. Referring to FIG. 23, in the fifth embodiment, unlike the fourth embodiment shown in FIG. 18, the channel P layer 44 covers the entire N ⁻ source / drain regions 32 and N ⁺ source / drain regions 33. Is formed. This makes it possible to more effectively prevent the depletion layer from extending from the drain region,
The substrate punch-through phenomenon can be reduced more effectively than in the fourth embodiment.

As a method of forming the channel P layer 44 of the MOS transistor of the fifth embodiment, boron is 250 keV, 6 × 10 ¹² with the resist 39 as a mask in the manufacturing process of the fourth embodiment shown in FIG. / Cm
It is formed by ion implantation under the condition of ² .

FIG. 24 shows an MO according to the sixth embodiment of the present invention.
It is a cross-section figure which showed the S transistor. Referring to FIG. 24, in the sixth embodiment, P-type silicon substrate 51 has groove-shaped recess 51a. A gate electrode 56 is formed on the channel region 57 at the bottom of the recess 51a with the gate oxide film 55 interposed therebetween. N ⁻ source / drain regions 52 are formed on the bottom surface and side surfaces of the recess 51 a so as to sandwich the channel region 57 at a predetermined interval. N ⁺ source / drain regions 53 are formed on the upper surface of the recess 51 a so as to be connected to the N ⁻ source / drain regions 52. N ^- source / drain region 5
A P layer 54a is formed in the surface region of No. 2. A channel P layer 54b is formed under both ends of the channel region 57 and part of the N ⁻ source / drain regions.

In the sixth embodiment, the threshold voltage is controlled by the P layer 54a and the portion of the channel P layer 54b located on the surface of the channel region 57. Further, the substrate punch-through phenomenon can be effectively prevented by the high-concentration channel P layer 54b extending deep under the N ⁻ source / drain regions 52.

Further, the N ⁺ source /
Since the drain regions 53, 53 are formed, the distance between the N ⁺ source / drain regions 53, 53 becomes longer, which also effectively prevents the substrate punch-through phenomenon.

25 to 29 are sectional structural views for illustrating the manufacturing process of the MOS transistor of the sixth embodiment shown in FIG. The manufacturing process of the MOS transistor of the sixth embodiment will be described with reference to FIGS.

First, as shown in FIG. 25, an oxide film layer (not shown) having a thickness of about 0.4 μm is formed on the main surface of P type silicon substrate 51, and then a gate length of 0.3 μm is formed.
In the case of forming the above MOS transistor, an opening of 0.4 μm is formed. As a result, the oxide film 58 having a predetermined pattern shape is formed. Using this oxide film 58 as a mask, oxygen ions are 145 keV, 3 × 10 ¹⁷ / cm 3.
Ions are implanted into the P-type silicon substrate 51 under the condition of ² .
Then, a heat treatment is performed under a temperature condition of about 1300 ° C. to form a gate oxide film layer 55a as shown in FIG. 26 by the oxygen ions implanted in the P-type silicon substrate 51.

Next, as shown in FIG. 27, a nitride film is formed on the entire surface.
After forming a layer (not shown), a predetermined area on the nitride film layer
A resist 60 is formed on. Mask the resist 60
The nitride film layer and the P-type silicon substrate 51 are etched as
The patterned single crystal
The recon layer 56a and the nitride film 59 are formed. Resist
The gate oxide film layer 55a is further etched by using 60 as a mask.
28, the game as shown in FIG.
The oxide film 55 is formed. After that, the oxide film 58 and
Boron 70keV, 1x1 with jisuto 60 as a mask
0¹³/ Cm²Under the conditions of 20 keV and 3 × 10
¹³/ Cm²Ion implantation is performed in two steps under
U Thereby, the P layer 54 is formed. In addition, the former
On implantation is ion implantation to prevent substrate punch through.
The latter ion implantation is for threshold voltage control.
Ion implantation. After this, the oxide film 58 and the resist
And the nitride film 59 are removed. Next, in FIG.
As shown, the arsenic ion is 50 keV, 1 × 10¹⁵/ C
m²Oblique rotation ion implantation is performed at 30 ° under the conditions of. this
By N^-Source / drain regions 52 are formed. Next
Similarly, arsenic ions were added at 50 keV, 1 × 10¹⁵/ Cm
²Ion implantation is performed at 0 ° under the conditions of. By this, N⁺
Source / drain regions 53 are formed.

By the formation of N ⁻ source / drain regions 52, P layer 54 shown in FIG. 28 is divided into P layer 54a and channel P layer 54b. Also,
The single crystal silicon layer 56a shown in FIG. 28 is partially amorphized due to the implantation of arsenic ions, and becomes the gate electrode 56 made of polysilicon close to single crystal. In this way, the MOS transistor of the sixth embodiment is formed.

FIG. 30 shows an MO according to the seventh embodiment of the present invention.
It is a cross-section figure which showed the S transistor. Referring to FIG. 30, in the seventh embodiment, unlike the sixth embodiment described above, the channel P layer 64 has an N ⁻ source / drain region 5 in it.
2 and N ⁺ source / drain regions 53 are formed to cover the entire surface. By forming in this way, the extension of the depletion layer from the drain region can be suppressed more effectively as compared with the sixth embodiment, and the substrate punch-through phenomenon can be prevented more effectively.

FIG. 31 shows an MO according to the eighth embodiment of the present invention.
It is a cross-section figure which showed the S transistor. Referring to FIG. 31, in the eighth embodiment, a groove-shaped recess 71a is formed on the main surface of P-type silicon substrate 71. And
A gate electrode 76 is formed on a channel region 78 on the bottom surface of the groove-shaped recess 71a with a gate oxide film 75 interposed therebetween. A channel region 78 is formed on the side surface and the bottom surface of the recess 71a.
N ⁻ source / drain regions 72 are formed with a predetermined distance therebetween so as to sandwich them. N ⁻ is formed on the upper surface of the recess 71a.
N ⁺ source / drain regions 73 are formed so as to be connected to the source / drain regions 72. A P layer 74 a is formed on the surface portion of the N ⁻ source / drain region 72. A channel P layer 74b extending below the N ⁻ source / drain region 72 is provided at both ends of the channel region 78.
Are formed.

A buried P layer 77 is formed so as to cover the side surface of the N ⁻ source / drain region and the bottom of the N ⁺ source / drain region 73.

In the eighth embodiment, the channel P layer 74b is used.
And the P layer 74a control the threshold voltage. Further, the high-concentration channel P layer 74b extending below the N ⁻ source / drain regions 72 can prevent the substrate punch-through phenomenon. Further, by forming the N ⁺ source / drain regions 73, 73 on the upper surface of the recess 71a, the distance between the N ⁺ source / drain regions 73, 73 becomes longer, which also effectively prevents the substrate punch-through phenomenon. can do.

32 to 36 are sectional structural views for explaining the manufacturing process of the MOS transistor of the eighth embodiment shown in FIG. 32 to 36, the manufacturing process of the MOS transistor of the eighth embodiment will be described.

First, as shown in FIG. 32, an oxide film layer (not shown) is formed on a P-type silicon substrate 71, and then a resist 80 is formed in a predetermined region on the oxide film layer. By anisotropically etching the oxide film layer using the resist 80 as a mask, for example, when forming a 0.3 μm transistor, the oxide film 7 having an opening width of about 0.4 μm.
9 is formed. Further, the resist 80 and the oxide film 79
By anisotropically etching the P-type silicon substrate 71 using the as a mask, the recess 7 as shown in FIG.
1a is formed. After forming the gate oxide film layer 75a on the entire surface, the polysilicon layer 7 is formed on the gate oxide film layer 75a.
6a is formed. The polysilicon layer 76a is polished and removed using the gate oxide film layer 75a as a stopper film. As a result, a polysilicon layer 76a having a smooth lateral connection with the gate oxide film layer 75a shown in FIG. 34 is obtained.

Thereafter, arsenic was added at 50 keV, 1 × 10 ¹⁵ /
Ion implantation is performed under the condition of cm ² . As a result, N ⁺ source / drain regions 73 are formed. By this ion implantation, arsenic is simultaneously implanted into the polysilicon layer 76a. After that, an oxide film layer (not shown) is formed on the entire surface, and then a resist 82 is formed on a predetermined region on the oxide film layer.
The oxide film 81 is formed by etching the oxide film layer using the resist 82 as a mask. After this resist 8
Remove 2. Then, the polysilicon layer 76a is anisotropically etched using the oxide film 81 as a mask, and the gate oxide film layer 75a is wet-etched in a separate step, so that the gate oxide film 75 and the gate electrode as shown in FIG. 76 is formed. Thereafter, arsenic is obliquely ion-implanted at 10 ° under the conditions of 50 keV and 1 × 10 ¹⁴ / cm ² . As a result, N ⁻ source / drain regions 72 are formed.

Next, as shown in FIG.
keV, 6 × 10 ¹² / cm ² and 10 keV,
By implanting twice under the condition of 5 × 10 ¹³ / cm ² , the P layer 74a, the channel P layer 74b and the buried P layer 7 are formed.
Form 7. After that, the oxide film 81 is removed. In this way, the MOS transistor of the eighth embodiment is completed.

FIG. 37 shows an MO according to the ninth embodiment of the present invention.
It is a cross-section figure which showed the S transistor. See Figure 37
In comparison, with the MOS transistor according to the ninth embodiment,
Has a concave portion 91a formed on the main surface of the P-type silicon substrate 91.
Is made. And the channel at the bottom of the recess 91a
A gate electrode 96 is formed on the region 97 via a gate oxide film 95.
Are formed. One of the side surface and the bottom surface of the recess 91a
At a predetermined interval so that the channel region 97 is sandwiched between the parts.
N^-Source / drain regions 92 are formed. Concave
The upper surface of the portion 91a has N^-In the source / drain region 92
N to connect ⁺Source / drain regions 93 are formed
Has been.

Recessed portion 91 of N ⁻ source / drain region 92
A P layer 94a is formed in a region located on the bottom surface of a. A channel P extending below the N ⁻ source / drain region 92 is provided at both ends of the surface region of the channel region 97.
The layer 94b is formed.

In the ninth embodiment, the threshold voltage of the MOS transistor is controlled by the P layer 94a and the channel P layer 94b. Also, the N ⁻ source / drain region 92
With the high-concentration channel P layer 94b extending below, the extension of the depletion layer from the drain region can be suppressed,
The substrate punch-through phenomenon can be effectively prevented.
Furthermore, the N ⁺ source / drain regions 93, 93 are formed in the recess 9
Since it is formed on the upper surface of 1a, the distance between the N ⁺ source / drain regions 93, 93 becomes long, which also prevents the substrate punch-through phenomenon.

38 to 42 are sectional structural views for illustrating the manufacturing process of the MOS transistor of the ninth embodiment shown in FIG. With reference to FIGS. 38 to 42, the manufacturing process of the MOS transistor of the ninth embodiment will be described.

First, as shown in FIG. 38, arsenic is deposited on the main surface of P-type silicon substrate 91 at 100 keV, 5 × 10 ¹⁵ /
N ⁺ source / drain regions 93 are formed by ion implantation under the condition of cm ² . After forming an oxide film layer (not shown) on the entire surface of the N ⁺ source / drain region 93, a resist 99 is formed on a predetermined region on the oxide film layer. By anisotropically etching the oxide film layer using the resist 99 as a mask, an oxide film 98 having a predetermined pattern is formed. Specifically, the oxide film 98
The opening width is about 0.1 μm, and the distance between the two holes is about 0.1 μm. Then, the resist 99 is used as a mask to further anisotropically etch the P-type silicon substrate 91 to form the recess 9 as shown in FIG.
1a and 91b are formed. After that, the resist 99 and the oxide film 98 are removed. The recesses 91a and 91
The depth of b is about 0.35 μm.

After that, an underlying oxide film 100 is formed on the entire surface, and then a nitride film 101 is formed on the underlying oxide film 100.

Next, as shown in FIG. 40, the nitride film 101 is formed.
Then, the oxide film 100 is anisotropically etched until the bottom surfaces of the recesses 91a and 91b are exposed.

Next, as shown in FIG. 41, when the entire surface is oxidized, an oxide film 102 is formed on the upper surface of N ⁺ source / drain region 93. At the same time, a thick oxide film is formed on the bottom surfaces of the recesses 91a and 91b, and bird's beaks at both ends of the thick oxide film extend and are connected at the central portion. As a result, the gate oxide film layer 95a is formed. From this state, boron is 200 keV, 6 ×
Under the condition of 10 ¹² / cm ² , 50 keV, 2 × 10 ¹³ /
42 by ion implantation under the condition of cm ² .
A P layer 94a and a P layer (not shown) to be the channel P layer are formed as shown in FIG. After that, the nitride film 101 and the oxide films 100 and 102 (see FIG. 41) are removed by wet etching. Further, the gate oxide film layer 9
The portions of 5a (see FIG. 41) exposed on the bottom surfaces of the recesses 91a and 91b are removed by anisotropic etching.

Next, as shown in FIG.
Oblique rotation ion implantation is performed at 45 ° under the conditions of eV and 1 × 10 ¹⁵ / cm ² . As a result, N ⁻ source / drain regions 92 are formed. Arsenic is also ion-implanted into the gate electrode 96 by a series of arsenic implantation steps. In this way, the MOS transistor of the ninth embodiment is formed.
The manufacturing process of the ninth embodiment has an advantage that the gate oxide film layer 95a can be easily formed by the normal LOCOS process.

FIG. 43 shows an M according to the tenth embodiment of the present invention.
FIG. 3 is a cross-sectional structure diagram showing an OS transistor. Referring to FIG. 43, in the MOS transistor according to the tenth embodiment, an N ⁻ source / region is formed on the main surface of P type silicon substrate 111 with a predetermined space therebetween so as to sandwich channel region 118.
The drain region 112 is formed. Further, N ⁺ source / drain regions 113 are formed so as to be connected to the N ⁻ source / drain regions 112. N ⁺ source / drain region 1
A P layer 114 a is formed in a part of a boundary region between the N 13 and the N ⁻ source / drain region 112. N ^- source /
Drain region 112 and N ⁺ source / drain region 1
An oxide film layer 119 is formed under 13. A gate electrode 116 is formed on the channel region 118 via a gate oxide film 115. Sidewall films 117 are formed on both side wall portions of the gate electrode 116.

As described above, in the tenth embodiment, the presence of the buried oxide layer 119 can prevent the soft error due to the radiation injection. In addition, the buried oxide layer 119
Is formed so as to have an opening below the channel region 118, the holes generated by collisional ionization of electrons in the vicinity of the N ⁺ source / drain region 113 are generated in the P-type 11
It can escape to the 1 side. In addition, since it has a pseudo SOI structure, it has almost no stray capacitance, and if the power consumption is the same, the speed can be increased to about twice as high as that on the bulk.

44 and 45 are cross-sectional structural views for illustrating the manufacturing process of the MOS transistor of the tenth embodiment shown in FIG. 43. The manufacturing process of the MOS transistor of the tenth embodiment will be described below with reference to FIGS.

First, as shown in FIG. 44, a gate oxide film 115, a gate electrode 116 made of polysilicon, and an oxide film 120 are formed on a P-type silicon substrate 111 by using a photolithography technique and a dry etching technique. To do. Then, using the oxide film 120 as a mask, oxygen ions are ion-implanted at 70 keV and 5 × 10 ¹⁷ / cm ² , for example. Here, the oxide film 120 plays a role of preventing oxygen ions from being implanted into the gate electrode 116 during the ion implantation of the oxygen ions. After this, for example, 1000
The implanted oxygen ions are reacted with the silicon atoms of the P-type silicon substrate 111 by heat treatment under a high temperature condition of ℃ or higher. As a result, a buried oxide layer 119 as shown in FIG. 45 is formed.

After that, arsenic was changed to 50 keV, 1 × 10 ¹⁴ /
The N ⁻ source / drain region 112 is formed by ion implantation under the condition of cm ² . Further, boron ions are ion-implanted under the conditions of 10 keV and 1 × 10 ¹³ / cm ² to form the high-concentration P layer 114a.

Finally, as shown in FIG.
After forming the roll film 117, arsenic is added at 50 keV, 1 ×
10¹⁵/ Cm²Ion implantation is performed under the conditions of. By this
R, N ⁺Source / drain regions 113 are formed. this
In this way, the MOS transistor of the tenth embodiment is completed.
To be done.

[0094]

According to the semiconductor device of the first and second aspects, the first high-concentration impurity region of the first conductivity type which is different from the source / drain regions is formed in a part of the channel region. The increase in the gate capacitance can be reduced as compared with the case where the first-conductivity-type high-concentration impurity region is formed on the entire surface of the channel region. As a result, it is possible to effectively prevent an increase in delay time per circuit due to an increase in gate capacitance. Further, the rate of change in the threshold voltage due to the substrate bias voltage can be reduced as compared with the case where the entire channel region is made to have a high concentration. As a result, the problem that the threshold voltage becomes too high as in the conventional case can be solved. Further, by forming the first high-concentration impurity region so as to extend deeper than the source / drain regions, it is possible to effectively prevent the depletion from extending from the source / drain region that constitutes the drain region. . As a result, the substrate punch through phenomenon can be effectively prevented. Since the substrate punch-through phenomenon can be effectively prevented in this way, it is not necessary to make the junction depth of the source / drain region shallow in order to prevent the substrate punch-through phenomenon as in the conventional case, and the source / drain region can be prevented from being formed. The resistance does not rise. As a result, the source /
It is also possible to solve the problem that the delay time of the device becomes long due to the increase in the resistance value of the drain region.

If the second high-concentration impurity region of the first conductivity type is further formed in at least one of the pair of source / drain regions, the second high-concentration impurity region and the above-mentioned second high-concentration impurity region are formed. The threshold voltage can be easily controlled by the first high concentration impurity region.

According to the semiconductor device of the third aspect, by forming the high-concentration impurity region of the first conductivity type in at least one of the source / drain regions, the conventional conductivity type of the first conductivity type is formed over the entire channel region. An increase in gate capacitance can be reduced as compared with the case of forming a high concentration impurity region. As a result, the delay time per circuit can be shortened as compared with the conventional case. Further, by forming the buried oxide layer below the source / drain regions, it is possible to suppress the depletion layer from extending from the side of the source / drain regions that constitutes the drain region, and the substrate punch-through phenomenon is effective. Can be prevented.

According to the method of manufacturing a semiconductor device of the fourth aspect, by introducing the first conductivity type impurity using the gate electrode as a mask, a part of the region of the semiconductor region where the channel region is formed has the first conductivity type. Forming a high-concentration impurity region of the first type on the entire surface of the conventional channel region.
It is possible to easily manufacture a semiconductor device capable of suppressing an increase in gate capacitance as compared with the case where a conductivity type high concentration impurity region is formed. Further, by forming the high-concentration impurity region of the first conductivity type so as to have a first depth deeper than the second depth of the source / drain region, the depletion layer from the drain region side of the source / drain region is formed. Can be prevented from extending. As a result, a semiconductor device capable of preventing the substrate punch through phenomenon can be easily manufactured.

According to the method of manufacturing a semiconductor device of the fifth aspect, oxygen ions are implanted into the semiconductor region using the gate electrode as a mask and heat treatment is performed to form a buried oxide layer having an opening under the gate electrode. Thus, the buried oxide layer can effectively prevent the depletion layer from extending from the drain region side of the source / drain region. As a result, a semiconductor device capable of effectively preventing the punch-through phenomenon can be easily manufactured. Also,
By forming a high-concentration impurity region of the first conductivity type in at least one of the pair of source / drain regions,
The increase in gate capacitance can be reduced as compared with the conventional case where a high concentration impurity region is formed over the entire surface of the channel region. As a result, it is possible to easily manufacture a semiconductor device capable of preventing a long delay time per circuit due to an increase in gate capacitance.

[Brief description of drawings]

FIG. 1 is a sectional structural view showing a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram for calculating the gate capacitance of the first embodiment shown in FIG.

FIG. 3 is an equivalent circuit diagram corresponding to the schematic diagram of FIG.

FIG. 4 is a sectional structural view for illustrating a first step of the manufacturing process of the MOS transistor of the first embodiment shown in FIG.

5 is a cross-sectional structural view for explaining a second step of the manufacturing process of the MOS transistor of the first embodiment shown in FIG.

6 is a sectional structural view for illustrating a third step of the manufacturing process of the MOS transistor of the first example shown in FIG. 1. FIG.

FIG. 7 is a sectional structural view for illustrating a fourth step of the manufacturing process of the MOS transistor of the first embodiment shown in FIG.

FIG. 8 is a sectional structural view for illustrating a fifth step of the manufacturing process of the MOS transistor of the first embodiment shown in FIG.

FIG. 9 is a schematic diagram for explaining the relationship between the ion implantation direction and the impurity concentration distribution.

FIG. 10 is a sectional structural view showing a MOS transistor according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional structural view for explaining the first step of the manufacturing process of the MOS transistor of the second embodiment shown in FIG.

12 is a sectional structural view for illustrating a second step of the manufacturing process of the MOS transistor of the second embodiment shown in FIG.

FIG. 13 is a sectional structural view for illustrating a third step of the manufacturing process of the MOS transistor of the second embodiment shown in FIG.

14 is a sectional structural view for illustrating a fourth step of the manufacturing process of the MOS transistor of the second embodiment shown in FIG.

15 is a sectional structural view for illustrating a fifth step of the manufacturing process of the MOS transistor of the second embodiment shown in FIG.

FIG. 16 is a sectional structural view showing a MOS transistor according to a third embodiment of the present invention.

FIG. 17 is a sectional structural view for illustrating a manufacturing process for the MOS transistor of the third embodiment shown in FIG.

FIG. 18 is a sectional structural view showing a MOS transistor according to a fourth embodiment of the present invention.

FIG. 19 is a cross-sectional structural view for explaining the first step of the manufacturing process of the MOS transistor of the fourth example shown in FIG.

FIG. 20 is a sectional structural view for illustrating a second step of the manufacturing process of the MOS transistor of the second embodiment shown in FIG.

FIG. 21 is a sectional structural view for illustrating a third step of the manufacturing process of the MOS transistor of the fourth example shown in FIG.

22 is a sectional structural view for illustrating a fourth step of the manufacturing process of the MOS transistor of the second embodiment shown in FIG. 18. FIG.

FIG. 23 is a sectional structural view showing a MOS transistor according to a fifth embodiment of the present invention.

FIG. 24 is a sectional structural view showing a MOS transistor according to a sixth embodiment of the present invention.

25 is a cross-sectional structure diagram for illustrating the first step of the manufacturing process of the MOS transistor of the sixth embodiment shown in FIG.

FIG. 26 is a sectional structural view for illustrating a second step of the manufacturing process for the MOS transistor of the sixth embodiment shown in FIG.

27 is a cross-sectional structure diagram for illustrating the third step of the manufacturing process of the MOS transistor of the sixth exemplary embodiment shown in FIG.

28 is a cross-sectional structure diagram for illustrating the fourth step of the manufacturing process of the MOS transistor of the sixth example shown in FIG.

29 is a cross-sectional structure diagram for illustrating the fifth step of the manufacturing process of the MOS transistor of the sixth embodiment shown in FIG.

FIG. 30 is a sectional structural view showing a MOS transistor according to a seventh embodiment of the present invention.

FIG. 31 is a sectional structural view showing a MOS transistor according to an eighth embodiment of the present invention.

32 is a sectional structure diagram for illustrating the first step of the manufacturing process of the MOS transistor of the eighth embodiment shown in FIG. 31. FIG.

33 is a cross-sectional structure diagram for illustrating the second step of the manufacturing process of the MOS transistor of the eighth exemplary embodiment shown in FIG.

FIG. 34 is a cross-sectional structure diagram for illustrating the third step of the manufacturing process of the MOS transistor of the eighth exemplary embodiment shown in FIG.

FIG. 35 is a cross-sectional structure diagram for illustrating the fourth step of the manufacturing process of the MOS transistor of the eighth embodiment shown in FIG.

36 is a cross-sectional structure diagram for illustrating the fifth step of the manufacturing process of the MOS transistor of the eighth exemplary embodiment shown in FIG.

FIG. 37 is a sectional structural view showing a MOS transistor according to a ninth embodiment of the present invention.

38 is a cross-sectional structure diagram for illustrating the first step of the manufacturing process of the MOS transistor of the ninth exemplary embodiment shown in FIG. 37. FIG.

39 is a cross-sectional structure diagram for illustrating the second step of the manufacturing process of the MOS transistor of the ninth exemplary embodiment shown in FIG. 37. FIG.

40 is a cross-sectional structure diagram for illustrating the third step of the manufacturing process of the MOS transistor of the ninth exemplary embodiment shown in FIG. 37. FIG.

41 is a cross-sectional structure diagram for illustrating the fourth step of the manufacturing process of the MOS transistor of the ninth exemplary embodiment shown in FIG.

42 is a cross-sectional structure diagram for illustrating the fifth step of the manufacturing process of the MOS transistor of the ninth exemplary embodiment shown in FIG.

FIG. 43 is a sectional structural view showing a MOS transistor according to a tenth embodiment of the present invention.

44 is a cross-sectional structure diagram for illustrating the first step of the manufacturing process of the MOS transistor of the tenth embodiment shown in FIG. 43. FIG.

FIG. 45 is a cross-sectional structure diagram for illustrating the second step of the manufacturing process of the MOS transistor of the tenth embodiment shown in FIG. 43.

FIG. 46 is a sectional structural view showing a conventional MOS transistor.

FIG. 47 is a cross-sectional structural view for explaining the first step of the manufacturing process for the conventional MOS transistor shown in FIG. 46.

48 is a sectional structure diagram for illustrating the second step of the manufacturing process for the conventional MOS transistor shown in FIG. 46. FIG.

49 is a sectional structure diagram for illustrating the third step of the manufacturing process for the conventional MOS transistor shown in FIG. 46. FIG.

FIG. 50 is a cross-sectional structural view for explaining the fourth step of the manufacturing process for the conventional MOS transistor shown in FIG. 46.

[Explanation of symbols]

1: P-type silicon substrate 2: N ^- source / drain region 3: N ⁺ source / drain region 4a: P layer 4b: Channel P layer 5: Gate oxide film 6: Gate electrode 8: Channel region In each figure, The same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] 1. A first-conductivity-type semiconductor region having a main surface, and a pair of second-conductivity-type sources formed on the main surface of the semiconductor region with a predetermined distance therebetween so as to sandwich a channel region. / Drain region, a first high-concentration impurity region of the first conductivity type formed in a part of the channel region and extending deeper than the source / drain region, and a gate on the channel region A semiconductor device, comprising: a gate electrode formed through an insulating layer. 2. The semiconductor device according to claim 1, wherein a second high-concentration impurity region of the first conductivity type is further formed in at least one of the pair of source / drain regions. 3. A first-conductivity-type semiconductor region having a main surface, and a pair of second-conductivity-type sources formed on the main surface of the semiconductor region with a predetermined distance therebetween so as to sandwich a channel region. / Drain region, a first-conductivity-type high-concentration impurity region formed in at least one of the pair of source / drain regions, and an opening formed under the source / drain region and under the channel region. And a buried oxide layer having. 4. A step of forming a gate electrode on a main surface of a first-conductivity-type semiconductor region with a gate insulating layer interposed therebetween, and introducing the first-conductivity-type impurity by using the gate electrode as a mask. Forming a high-concentration impurity region of the first conductivity type having a first depth in a part of the region where the channel region is formed, and defining the channel region on the main surface of the semiconductor region. And a step of forming a pair of source / drain regions of the second conductivity type having a second depth shallower than the first depth with a predetermined distance therebetween. 5. A step of forming a gate electrode on a main surface of a semiconductor region of the first conductivity type with a gate insulating layer interposed, and oxygen ions are implanted into the semiconductor region using the gate electrode as a mask to perform heat treatment. Thereby forming a buried oxide layer having an opening under the gate electrode, and a second conductivity type on the main surface of the semiconductor region at a predetermined interval so that a channel region is located under the gate electrode. Forming a pair of source / drain regions, and forming a first-conductivity-type high-concentration impurity region in at least one of the pair of source / drain regions. Method.