CN104362095A - Production method of tunneling field-effect transistor - Google Patents
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- CN104362095A CN104362095A CN201410616285.1A CN201410616285A CN104362095A CN 104362095 A CN104362095 A CN 104362095A CN 201410616285 A CN201410616285 A CN 201410616285A CN 104362095 A CN104362095 A CN 104362095A
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- 230000005669 field effect Effects 0.000 title claims abstract description 18
- 230000005641 tunneling Effects 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 24
- 238000002360 preparation method Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 239000003989 dielectric material Substances 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims description 2
- 238000005240 physical vapour deposition Methods 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 230000004913 activation Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 210000000746 body region Anatomy 0.000 abstract description 2
- 230000000295 complement effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000012190 activator Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a production method of a tunneling field-effect transistor and belongs to the field of CMOS (complementary metal-oxide-semiconductor transistor) ULSI (ultra-large scale integrated circuits) and their field-effect transistor logic devices. According to the production method, a p-type silicon wafer of relative high impedance is used as a trench region and a body region of a TFET (tunneling field-effect transistor) device, a mask for injection of an N<-> region is added on basis of the standard CMOS-IC process, the N<-> region injected deep in a trench, device isolation is achieved for the TFET in circuit application, and device performances and device area are unaffected.
Description
Technical field
The invention belongs to the FET logic device in CMOS super large integrated circuit (ULSI) and circuit field, be specifically related to a kind of method of isolation tunneling field-effect transistor (TFET).
Background technology
Along with MOSFET size enters nanoscale, the negative effects such as the short-channel effect of device are further serious, and the OFF state leakage current of device constantly increases.Simultaneously, the restriction that sub-threshold slope due to conventional MOS FET is subject to thermoelectric potential synchronously cannot reduce along with reducing of device size, there is the theoretical limit of 60mV/dec, leakage current is increased further along with reducing of supply voltage, thereby increases device power consumption.Power problems is one of the severeest problem having become limiting device scaled down nowadays.In ultralow pressure low-power consumption field, tunneling field-effect transistor (TFET) becomes everybody focus paid close attention in recent years because it has very low leakage current and super steep sub-threshold slope.
TFET is different from conventional MOS FET, its source and drain doping type is contrary, and channel region and interior body region are generally intrinsic doping, and the quantum band-to-band-tunneling utilizing grid to control back-biased P-I-N knot realizes conducting, it can work at the lower voltage, and technique and traditional cmos process compatibility.But in actual small size standard CMOS IC preparation technology, break-through is prevented in order to suppress the short channel effect of MOSFET, in the body of MOSFET, the doping content in (subsurface) region is higher, surf zone is low-doped, its doping content is for all too high TFET device, if carry out the leakage current of integrated TFET device meeting increased device completely based on standard CMOS IC technique, and have impact to TFET on state characteristic.In addition, TFET device is three terminal device, and for N-type TFET, source is P
+district, drain region is N
+, substrate is generally P-, and there is identical doping type in light dope substrate and source region, and therefore light dope substrate can be drawn by source region simultaneously, enjoys same potential; But for P type TFET, source region is N+, and drain region is P
+.When TFET device composition complicated circuit, NTFET and PTFET enjoys same substrate, because resistance substrate is usually not high enough, causes the P of different TFET device
+district can be interconnected by substrate, and the P of different TFET devices in circuit application
+may there is difference in the current potential in district, therefore light dope substrate can cause current potential crosstalk, and this is a very large problem in the circuit of TFET device composition, needs a kind of method of effectively isolating each TFET device.
Summary of the invention
The object of the invention is to propose a kind of preparation method isolating tunneling field-effect transistor.In the method, the p-type silicon chip of relative high resistant is adopted directly to be used as channel region and the tagma of TFET device, and comparison with standard CMOS IC technique, add one piece for injecting N
-mask plate, by raceway groove comparatively depths inject N
-isolated area, achieves the isolation of tunneling field-effect transistor (TFET) device in circuit application, does not affect device performance and device area simultaneously.
A preparation method for tunneling field-effect transistor with isolation, specifically comprises the following steps:
(1) substrate prepares: (concentration is 1 × 10 for light dope or low-doped p-type semiconductor substrate
14~ 2 × 10
15cm
-3);
(2) initial thermal oxidation deposit one deck nitride;
(3) adopt shallow-trench isolation fabrication techniques active area STI to isolate, remove nitride;
(4) N is used
-isolated area mask plate, photoetching exposes the region at TFET device place, and area is greater than active region area, carries out N
-isolated area is injected; N
-the injection degree of depth of isolated area needs the source and drain junction depth (source and drain junction depth about 10 ~ 100nm) being greater than device, but can not exceed the degree of depth (the STI region degree of depth about 300 ~ 500nm) of STI region, and injecting degree of depth representative value is 200 ~ 300nm; N
-isolated area concentration is higher than P type semiconductor substrate concentration, but can not higher than 1 × 10
17cm
-3, concentration about 5 × 10
15~ 5 × 10
16cm
-3;
(5) oxide of growth before removing, regrow gate dielectric material;
(6) deposit grid material, then photoetching and etching, form gate figure;
(7) with photoresist and grid for mask, ion implantation forms the source of TFET; For N-type TFET, source is P+ doping, and can adopt the P+ injection condition in CMOS technology, energy is 4 ~ 50keV, and dosage is 3e14 ~ 5e15, ensures concentration about 1 × 10
20~ 1 × 10
21cm
-3; For P type TFET, source is N+ doping, and can adopt the N+ injection condition in CMOS technology, energy is 15 ~ 50keV, and dosage is 3e14 ~ 9e15, ensures concentration about 1 × 10
20~ 1 × 10
21cm
-3;
(8) with photoresist and grid for mask, the impurity of the another kind of doping type of ion implantation, forms the leakage of TFET; For N-type TFET, leak for N
+doping, can adopt the N in CMOS technology
+injection condition, energy is 15 ~ 50keV, and dosage is 3e14 ~ 9e15, concentration about 1 × 10
20~ 1 × 10
21cm
-3; For P type TFET, leak for P
+doping, can adopt the P in CMOS technology
+injection condition, energy is 4 ~ 50keV, and dosage is 3e14 ~ 5e15, concentration about 1 × 10
20~ 1 × 10
21cm
-3;
(9) quick high-temp annealing activator impurity;
(10) finally enter the consistent later process of same CMOS, comprise deposit passivation layer, opening contact hole and metallization etc., can tunneling field-effect transistor be obtained.
In above-mentioned preparation method, semiconductor substrate materials in described step (1) is selected from the germanium (GOI) on the binary of Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV races or ternary semiconductor, isolate supports (SOI) or insulator.
In above-mentioned preparation method, the gate dielectric layer material in described step (5) is selected from SiO
2, Si
3n
4and high-K gate dielectric material.
In above-mentioned preparation method, the method for the growth gate dielectric layer in described step (5) is selected from one of following method: conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition and physical vapor deposition.
In above-mentioned preparation method, the grid material in described step (6) is selected from doped polycrystalline silicon, metallic cobalt, nickel and other metals or metal silicide.
Proposed by the invention utilizes N
-isolated area is isolated in the method for tunneling field-effect transistor, directly have employed doped with P type substrate as the raceway groove of TFET device and tagma, the leakage current that effectively prevent owing to adopting the heavy doping N trap of MOSFET or P trap to cause as raceway groove and tagma increases.Because this light dope substrate causes P between different components
+the problem of the current potential crosstalk in district can by the N injected
-isolated area solves.In the method, in order to prevent directly being connected with source-drain area, N
-the injection degree of depth of isolated area needs the source and drain junction depth being greater than device, but the degree of depth can not exceed the degree of depth of STI region, otherwise device tagma and substrate still connect together.Meanwhile, N
-isolated area concentration is higher than P type semiconductor substrate concentration, ensure that the P type substrate the region injected is original can be compensated into N-type like this, but concentration again can not higher than 1 × 10
17cm
-3, otherwise too high doping content still can bring the increase of leakage current.The method effectively isolates tunneling field-effect transistor, and does not affect the performance of tunneling field-effect transistor and the area of device, makes TFET device application become possibility to complicated circuit.This partition method is applicable between different N TFET device, or between different PTFET, is also applicable between NTFET and PTFET.
Accompanying drawing explanation
Fig. 1 is the device profile map after removing nitride after forming STI isolation on a semiconductor substrate;
Fig. 2 is the region using the photoetching of N-isolated area mask plate to expose TFET device place, carries out the TFET device profile map after the injection of N-isolated area;
Fig. 3 is photoetching and etches the device profile map after forming grid;
Fig. 4 is that photoetching exposes the source region of TFET device and the device profile map behind the source region of ion implantation formation high-dopant concentration;
Fig. 5 is that photoetching exposes the drain region of TFET device and the device profile map behind the highly doped drain region of ion implantation formation opposite types;
Fig. 6 is through the device profile map after later process (contact hole, metallization);
Fig. 7 is the device profile map of the different tunneling field-effect transistors with band N-of the present invention isolation;
In figure:
1---Semiconductor substrate; 2---oxide layer;
3---STI isolates; 4---N-isolated area;
5---photoresist; 6---dielectric layer;
7---grid; 8---highly doped source region;
9---highly doped drain region; 10---the passivation layer of later process;
11---the metal of later process.
Embodiment
Below by example, the present invention will be further described.It should be noted that the object publicizing and implementing example is to help to understand the present invention further, but it will be appreciated by those skilled in the art that: in the spirit and scope not departing from the present invention and claims, various substitutions and modifications are all possible.Therefore, the present invention should not be limited to the content disclosed in embodiment, and the scope that the scope of protection of present invention defines with claims is as the criterion.
One instantiation of preparation method of the present invention comprises the processing step shown in Fig. 1 to Fig. 6:
1, substrate doping be light dope, crystal orientation be <100> body silicon substrate 1 on initial thermal oxidation layer of silicon dioxide 2, thickness is about 10nm, and deposit one deck silicon nitride, thickness is about 100nm, STI etching afterwards, and CMP after deposit isolated material filling deep hole, adopt shallow-trench isolation fabrication techniques active area STI to isolate 3, then wet etching removes silicon nitride, as shown in Figure 1.
2, utilize N-isolated area mask plate, photoetching exposes the region at NTFET device place, and area is greater than active area, and carry out N-isolated area afterwards and inject 4, implanted dopant is P, and energy and dosage are respectively 200keV 2e12, as shown in Figure 2.
3, the silicon dioxide of surperficial initial growth is removed in drift, then heat growth one deck gate dielectric layer 6, and gate dielectric layer is SiO
2, thickness is 1 ~ 5nm; Deposit grid material 7, grid material is doped polysilicon layer, and thickness is 150 ~ 300nm.Make gate figure by lithography, etch grid material 7 until gate dielectric layer 6, as shown in Figure 3.
5, with photoresist 5 and grid 7 for mask, the source 8 of ion implantation NTFET, the energy of ion implantation is 40keV, and dosage is 1e15, and implanted dopant is BF
2 +, as shown in Figure 4.
6, with photoresist 5 and grid 7 for mask, the leakage 9 of ion implantation NTFET, the energy of ion implantation is 50keV, and dosage is 1e15, and implanted dopant is As
+, as shown in Figure 5.
7, carry out a quick high-temp annealing, activate the impurity of source and drain doping.
8, finally enter conventional cmos later process, comprise deposit passivation layer 10, opening contact hole and metallization 11 etc., be illustrated in figure 6 the obtained described N-type tunneling field-effect transistor prepared based on dark N trap isolation technology.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (6)
1. a preparation method for tunneling field-effect transistor, specifically comprises the following steps:
(1) substrate prepares: light dope or low-doped p-type semiconductor substrate, doping content is 1 × 10
14~ 2 × 10
15cm
-3;
(2) initial thermal oxidation deposit one deck nitride;
(3) adopt shallow-trench isolation fabrication techniques active area STI to isolate, remove nitride;
(4) use N-isolated area mask plate, photoetching exposes the region at TFET device place, and area is greater than active region area, carries out N-isolated area and injects; The injection degree of depth of N-isolated area is greater than the source and drain junction depth of device, but can not exceed the degree of depth of STI region, and injection depth value is 200 ~ 300nm; N-isolated area concentration, but can not higher than 1 × 10 higher than P type semiconductor substrate concentration
17cm
-3, concentration about 5 × 10
15~ 5 × 10
16cm
-3;
(5) oxide of growth before removing, regrow gate dielectric material;
(6) deposit grid material, then photoetching and etching, form gate figure;
(7) with photoresist and grid for mask, ion implantation forms the source of TFET, and concentration range is 1 × 10
20~ 1 × 10
21cm
-3;
(8) with photoresist and grid for mask, the impurity of the another kind of doping type of ion implantation, form the leakage of TFET, concentration range is 1 × 10
20~ 1 × 10
21cm
-3;
(9) high-temperature annealing activation impurity;
(10) finally enter the consistent later process of same CMOS, comprise deposit passivation layer, opening contact hole and metallization, can tunneling field-effect transistor be obtained.
2. preparation method as claimed in claim 1, it is characterized in that, semiconductor substrate materials in described step (1) is selected from the germanium on the binary of Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV races or ternary semiconductor, isolate supports or insulator.
3. preparation method as claimed in claim 1, is characterized in that, in described step (4), source and drain junction depth is 10 ~ 100nm, and the STI region degree of depth is 300 ~ 500nm.
4. preparation method as claimed in claim 1, it is characterized in that, the gate dielectric layer material in described step (5) is selected from SiO
2, Si
3n
4and high-K gate dielectric material.
5. preparation method as claimed in claim 1, it is characterized in that, the method for the growth gate dielectric layer in described step (5) is selected from one of following method: conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition and physical vapor deposition.
6. preparation method as claimed in claim 1, it is characterized in that, the grid material in described step (6) is selected from doped polycrystalline silicon, metallic cobalt, nickel and other metals or metal silicide.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106531622A (en) * | 2016-12-29 | 2017-03-22 | 中国科学院微电子研究所 | Preparation method of gallium arsenide-based MOSFET gate dielectric |
| CN109065615A (en) * | 2018-06-12 | 2018-12-21 | 西安电子科技大学 | A kind of heterogeneous tunneling field-effect transistor of novel planar InAs/Si and preparation method thereof |
| CN111785770A (en) * | 2019-04-03 | 2020-10-16 | 北京大学 | Substrate leakage isolation structure of conventional tunneling field effect transistor and process method |
| WO2021227448A1 (en) * | 2020-05-13 | 2021-11-18 | 北京大学 | Tunnel field effect transistor drain end underlap region self-aligning preparation method |
| CN115497816A (en) * | 2022-10-19 | 2022-12-20 | 晋芯电子制造(山西)有限公司 | Preparation system and method of semiconductor field effect integrated circuit |
| EP4354496A1 (en) * | 2022-10-13 | 2024-04-17 | Nxp B.V. | Isolation structure for an active component |
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| CN109065615A (en) * | 2018-06-12 | 2018-12-21 | 西安电子科技大学 | A kind of heterogeneous tunneling field-effect transistor of novel planar InAs/Si and preparation method thereof |
| CN109065615B (en) * | 2018-06-12 | 2021-05-07 | 西安电子科技大学 | Novel planar InAs/Si heterogeneous tunneling field effect transistor and preparation method thereof |
| CN111785770A (en) * | 2019-04-03 | 2020-10-16 | 北京大学 | Substrate leakage isolation structure of conventional tunneling field effect transistor and process method |
| WO2021227448A1 (en) * | 2020-05-13 | 2021-11-18 | 北京大学 | Tunnel field effect transistor drain end underlap region self-aligning preparation method |
| EP4354496A1 (en) * | 2022-10-13 | 2024-04-17 | Nxp B.V. | Isolation structure for an active component |
| CN115497816A (en) * | 2022-10-19 | 2022-12-20 | 晋芯电子制造(山西)有限公司 | Preparation system and method of semiconductor field effect integrated circuit |
| CN115497816B (en) * | 2022-10-19 | 2023-10-17 | 弘大芯源(深圳)半导体有限公司 | Semiconductor field effect integrated circuit and preparation method thereof |
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