CN104362095A - Production method of tunneling field-effect transistor - Google Patents

Abstract

The invention discloses a preparation method of a tunneling field effect transistor with isolation, and belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large integrated circuits (ULSI). In this method, a relatively high-resistance p-type silicon wafer is used directly as the channel region and body region of the TFET device, and compared with the standard CMOS IC process, a mask plate for implanting N- is added. The N-isolation region is implanted deep in the channel to realize the isolation of the tunneling field effect transistor (TFET) in the circuit application without affecting the device performance and device area.

Description

A kind of preparation method of tunneling field effect transistor

technical field

The invention belongs to the field of field effect transistor logic devices and circuits in a CMOS ultra large integrated circuit (ULSI), and in particular relates to a method for isolating a tunneling field effect transistor (TFET).

Background technique

As the size of the MOSFET enters the nanometer scale, the negative effects such as the short channel effect of the device become more and more serious, and the off-state leakage current of the device continues to increase. At the same time, because the sub-threshold slope of the traditional MOSFET is limited by the thermoelectric potential and cannot be reduced synchronously with the reduction of the device size, there is a theoretical limit of 60mV/dec, which makes the leakage current further increase with the reduction of the power supply voltage, thus increased device power consumption. The power consumption problem has become one of the most severe problems limiting the scaling of devices today. In the field of ultra-low voltage and low power consumption, the tunneling field effect transistor (TFET) has become a hot spot in recent years because of its low leakage current and ultra-steep subthreshold slope.

TFET is different from traditional MOSFET, its source-drain doping type is opposite, and the channel region and the body region are usually intrinsic doping, using the gate to control the quantum band tunneling of the reverse biased PIN junction to achieve conduction, it It can work at a lower voltage, and the process is compatible with the traditional CMOS process. However, in the actual small-size standard CMOS IC manufacturing process, in order to suppress the short-channel effect of the MOSFET and prevent punch-through, the doping concentration in the body (subsurface) region of the MOSFET is relatively high, and the surface region is low-doped. The doping concentration is relatively low for TFET devices. Both are too high, if the TFET device is integrated completely based on the standard CMOS IC process, the leakage current of the device will be increased, and the conduction characteristics of the TFET will be affected. In addition, TFET devices are three-terminal devices. For N-type TFETs, the source is P ⁺ region, the drain region is N ⁺ , the substrate is usually P-, and the lightly doped substrate and source region have the same doping type, so light The doped substrate can be drawn out through the source region at the same time and share the same potential; but for a P-type TFET, the source region is N+ and the drain region is P ⁺ . When TFET devices form complex circuits, NTFETs and PTFETs share the same substrate. Because the substrate resistance is usually not high enough, the P ⁺ regions of different TFET devices can be connected to each other through the substrate, and the P ⁺ regions of different TFET devices in circuit applications The potentials of the regions may be different, so the lightly doped substrate will cause potential crosstalk, which is a big problem in a circuit composed of TFET devices, and a method for effectively isolating each TFET device is needed.

Contents of the invention

The object of the present invention is to provide a preparation method of an isolated tunneling field effect transistor. In this method, a relatively high-resistance p-type silicon wafer is used directly as the channel region and the body region of the TFET device, and compared with the standard CMOS IC process, a mask plate for implanting ^N- is added. The N ^- isolation region is implanted deep in the channel to realize the isolation of the tunneling field effect transistor (TFET) in the circuit application without affecting the device performance and device area.

A method for preparing a tunneling field effect transistor with isolation, specifically comprising the following steps:

(1) Substrate preparation: lightly doped or lowly doped p-type semiconductor substrate (with a concentration of 1×10 ¹⁴ to 2×10 ¹⁵ cm ^-3 );

(2) initial thermal oxidation and deposition of a layer of nitride;

(3) Use shallow trench isolation technology to make STI isolation in the active area to remove nitrides;

(4) Use the N ^- isolation mask to expose the area where the TFET device is located by photolithography, and the area is larger than the active area, and perform N ^- isolation implantation; the implantation depth of the N ^- isolation area needs to be greater than the source and drain of the device Junction depth (source-drain junction depth is about 10-100nm), but cannot exceed the depth of the STI region (the depth of the STI region is about 300-500nm), and the typical value of the implantation depth is 200-300nm; the concentration of the N ^- isolating region is higher than that of the P-type semiconductor Substrate concentration, but not higher than 1×10 ¹⁷ cm ^-3 , about 5×10 ¹⁵ to 5×10 ¹⁶ cm ^-3 ;

(5) Remove the previously grown oxide and re-grow the gate dielectric material;

(6) Deposit gate material, followed by photolithography and etching to form a gate pattern;

(7) Using photoresist and gate as a mask, ion implantation forms the source of TFET; for N-type TFET, the source is P+ doping, and the P+ implantation conditions in the CMOS process can be used, the energy is 4-50keV, and the dose is 3e14 ～5e15, the guaranteed concentration is about 1×10 ²⁰ ～1×10 ²¹ cm ^-3 ; for P-type TFET, the source is N+ doping, and the N+ implantation conditions in CMOS process can be adopted, the energy is 15～50keV, and the dose is 3e14～ 9e15, the guaranteed concentration is about 1×10 ²⁰ ～1×10 ²¹ cm ^-3 ;

(8) Using photoresist and gate as a mask, ions implant another doping type of impurity to form the drain of TFET; for N-type TFET, the drain is N ⁺ doped, and N ⁺ implantation in CMOS process can be used conditions, the energy is 15-50keV, the dose is 3e14-9e15, and the concentration is about 1×10 ²⁰ ～1×10 ²¹ cm ^-3 ; for a P-type TFET, the drain is P ⁺ doped, and P ⁺ implantation in the CMOS process can be used conditions, the energy is 4-50keV, the dose is 3e14-5e15, and the concentration is about 1×10 ²⁰ ～1×10 ²¹ cm ^-3 ;

(9) Rapid high-temperature annealing activates impurities;

(10) Finally, it enters the subsequent process that is consistent with CMOS, including depositing a passivation layer, opening a contact hole, and metallizing, etc., to produce a tunneling field effect transistor.

In the above-mentioned preparation method, the semiconductor substrate material in the step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV group binary or ternary compound semiconductors, Silicon on insulator (SOI) or germanium on insulator (GOI).

In the above preparation method, the material of the gate dielectric layer in the step (5) is selected from SiO ₂ , Si ₃ N ₄ and high-K gate dielectric materials.

In the above preparation method, the method for growing the gate dielectric layer in the step (5) is selected from one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition and physical vapor deposition.

In the above preparation method, the gate material in the step (6) is selected from doped polysilicon, metal cobalt, nickel and other metals or metal silicides.

In the method for isolating tunneling field-effect transistors by using N ^- isolating regions proposed by the present invention, lightly doped P-type substrates are directly used as channel and body regions of TFET devices, effectively avoiding heavy doping due to the adoption of MOSFETs. The leakage current increases due to the mixed N well or P well as the channel and body region. The problem of potential crosstalk between P ⁺ regions between different devices due to the lightly doped substrate can be solved by implanting ^N- isolation regions. In this method, in order to prevent direct connection with the source and drain regions, the implantation depth of the N ^- isolation region needs to be greater than the source and drain junction depth of the device, but the depth cannot exceed the depth of the STI region, otherwise the device body region and the substrate are still connected together . At the same time, the concentration of the N ^- isolating region should be higher than that of the P-type semiconductor substrate, so as to ensure that the original P-type substrate in the implanted region can be compensated for N-type, but the concentration cannot be higher than 1×10 ¹⁷ cm ^-3 , Otherwise, too high doping concentration will still increase the leakage current. The method effectively isolates the tunneling field effect transistor without affecting the performance of the tunneling field effect transistor and the area of the device, making it possible to apply the TFET device to complex circuits. This isolation method is applicable between different NTFET devices, or between different PTFETs, and is also applicable between NTFETs and PTFETs.

Description of drawings

Figure 1 is a cross-sectional view of the device after the nitride is removed after the STI isolation is formed on the semiconductor substrate;

Figure 2 is a cross-sectional view of the TFET device after the N-isolation region is implanted to expose the region where the TFET device is located by using the N-isolation region mask lithography;

3 is a cross-sectional view of the device after photolithography and etching to form the gate;

Figure 4 is a cross-sectional view of the device after photolithography exposes the source region of the TFET device and ion implants to form a source region with a high doping concentration;

Fig. 5 is a cross-sectional view of the device after photolithography exposes the drain region of the TFET device and ion implants to form a highly doped drain region of the opposite type;

Figure 6 is a cross-sectional view of the device after the subsequent process (contact hole, metallization);

Fig. 7 is a cross-sectional view of devices with different tunneling field effect transistors with N-isolation of the present invention;

In the picture:

1——Semiconductor substrate; 2——Oxide layer;

3——STI isolation; 4——N-isolation area;

5——photoresist; 6——dielectric layer;

7—gate; 8—highly doped source region;

9——Highly doped drain region; 10——Passivation layer in subsequent processes;

11—Metals in subsequent processes.

Detailed ways

The present invention will be further described below by example. It should be noted that the purpose of the disclosed embodiments is to help further understand the present invention, but those skilled in the art can understand that various replacements and modifications are possible without departing from the spirit and scope of the present invention and the appended claims of. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the protection scope of the present invention is subject to the scope defined in the claims.

A specific example of the preparation method of the present invention comprises the processing steps shown in Fig. 1 to Fig. 6:

1. Initially thermally oxidize a layer of silicon dioxide 2 on a bulk silicon substrate 1 with a lightly doped substrate doping concentration and a crystal orientation of <100>, with a thickness of about 10 nm, and deposit a layer of silicon nitride with a thickness of About 100nm, followed by STI etching, and depositing isolation material to fill the deep hole, CMP, using shallow trench isolation technology to make STI isolation 3 in the active area, and then wet etching to remove silicon nitride, as shown in Figure 1.

2. Using the N-isolation area mask, photolithography exposes the area where the NTFET device is located, and the area is larger than the active area. After that, the N-isolation area is implanted 4, the implanted impurity is P, and the energy and dose are 200keV 2e12, respectively. as shown in picture 2.

3. Float away the silicon dioxide initially grown on the surface, and then thermally grow a gate dielectric layer 6, the gate dielectric layer is SiO ₂ , with a thickness of 1-5nm; deposit the gate material 7, which is a doped polysilicon layer with a thickness of 150-300nm. The gate pattern is photolithographically etched, and the gate material 7 is etched until the gate dielectric layer 6, as shown in FIG. 3 .

5. Using the photoresist 5 and the gate 7 as a mask, ions are implanted into the source 8 of the NTFET. The ion implantation energy is 40keV, the dose is 1e15, and the implanted impurity is BF ₂ ⁺ , as shown in FIG. 4 .

6. Using the photoresist 5 and the gate 7 as a mask, ions are implanted into the drain 9 of the NTFET. The ion implantation energy is 50keV, the dose is 1e15, and the implanted impurity is As ⁺ , as shown in FIG. 5 .

7. Perform a rapid high-temperature annealing to activate the impurities doped in the source and drain.

8. Finally enter the conventional CMOS back-end process, including depositing passivation layer 10, opening contact holes and metallization 11, etc., as shown in FIG. field effect transistor.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (6)

1. a preparation method for tunneling field-effect transistor, specifically comprises the following steps:

(1) substrate prepares: light dope or low-doped p-type semiconductor substrate, doping content is 1 × 10 ¹⁴~ 2 × 10 ¹⁵cm ^-3;

(2) initial thermal oxidation deposit one deck nitride;

(3) adopt shallow-trench isolation fabrication techniques active area STI to isolate, remove nitride;

(4) use N-isolated area mask plate, photoetching exposes the region at TFET device place, and area is greater than active region area, carries out N-isolated area and injects; The injection degree of depth of N-isolated area is greater than the source and drain junction depth of device, but can not exceed the degree of depth of STI region, and injection depth value is 200 ~ 300nm; N-isolated area concentration, but can not higher than 1 × 10 higher than P type semiconductor substrate concentration ¹⁷cm ^-3, concentration about 5 × 10 ¹⁵~ 5 × 10 ¹⁶cm ^-3;

(5) oxide of growth before removing, regrow gate dielectric material;

(6) deposit grid material, then photoetching and etching, form gate figure;

(7) with photoresist and grid for mask, ion implantation forms the source of TFET, and concentration range is 1 × 10 ²⁰~ 1 × 10 ²¹cm ^-3;

(8) with photoresist and grid for mask, the impurity of the another kind of doping type of ion implantation, form the leakage of TFET, concentration range is 1 × 10 ²⁰~ 1 × 10 ²¹cm ^-3;

(9) high-temperature annealing activation impurity;

(10) finally enter the consistent later process of same CMOS, comprise deposit passivation layer, opening contact hole and metallization, can tunneling field-effect transistor be obtained.

2. preparation method as claimed in claim 1, it is characterized in that, semiconductor substrate materials in described step (1) is selected from the germanium on the binary of Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV races or ternary semiconductor, isolate supports or insulator.

3. preparation method as claimed in claim 1, is characterized in that, in described step (4), source and drain junction depth is 10 ~ 100nm, and the STI region degree of depth is 300 ~ 500nm.

4. preparation method as claimed in claim 1, it is characterized in that, the gate dielectric layer material in described step (5) is selected from SiO ₂, Si ₃n ₄and high-K gate dielectric material.

5. preparation method as claimed in claim 1, it is characterized in that, the method for the growth gate dielectric layer in described step (5) is selected from one of following method: conventional thermal oxidation, nitriding thermal oxidation, chemical vapor deposition and physical vapor deposition.

6. preparation method as claimed in claim 1, it is characterized in that, the grid material in described step (6) is selected from doped polycrystalline silicon, metallic cobalt, nickel and other metals or metal silicide.