CN115497816A - Preparation system and method of semiconductor field effect integrated circuit - Google Patents
Preparation system and method of semiconductor field effect integrated circuit Download PDFInfo
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- CN115497816A CN115497816A CN202211279018.0A CN202211279018A CN115497816A CN 115497816 A CN115497816 A CN 115497816A CN 202211279018 A CN202211279018 A CN 202211279018A CN 115497816 A CN115497816 A CN 115497816A
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- 238000002360 preparation method Methods 0.000 title description 5
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- 238000002347 injection Methods 0.000 claims abstract description 57
- 239000007924 injection Substances 0.000 claims abstract description 57
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 57
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 57
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- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H01L21/26—Bombardment with radiation
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a system and a method for preparing a semiconductor field effect integrated circuit, which comprises the following steps: the semiconductor device comprises a P-type semiconductor substrate, a first area, a second area and an insulating plate; a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed in the first region; a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar; insulating plates are respectively arranged on the upper layers of the first area and the second area. The first injection region and the second injection region are used for carrying out ion injection on the semiconductor integrated circuit, so that the conductive contact quality of the N-type semiconductor is improved, and the silicon dioxide insulating layer is arranged, so that impurities can be effectively prevented from permeating towards the surface of the substrate, and the reliability and the stability of the device integrated circuit are improved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a preparation method and a preparation method of a semiconductor field effect integrated circuit.
Background
Semiconductor integrated circuit devices are receiving attention for size, function and low cost manufacturing, and ion implantation is a method of introducing a controllable amount of impurities into a substrate to change electrical properties in a semiconductor process, and is almost implemented by doping ion implantation in modern semiconductor processes, and different effects are produced by the difference of implantation concentrations, and different process conditions are required for different devices. The existing technology is difficult to master the measurement of ion implantation. The channel effect of ion implantation can affect the electrical parameters of the device, various adverse conditions can also occur when the ion implantation is improper, and along with the continuous change of the size of the semiconductor device, the current ion implantation process carries out ion implantation on an active region to form the bad condition of double traps, which affects the production of the semiconductor device and also forms a barrier to the progress of the semiconductor process.
Disclosure of Invention
To solve the above-mentioned problems occurring in the prior art, the present invention provides,
a system for manufacturing a semiconductor field effect integrated circuit, comprising:
the semiconductor device comprises a P-type semiconductor substrate, a first area, a second area and an insulating plate;
a first region: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed in the first region;
a second region: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
insulating board: insulating plates are respectively arranged on the upper layers of the first area and the second area.
Preferably, the first region is coplanar with the second region, and includes:
the first injection region and the second injection region are injected by ions;
the first injection region is an N + type conductive region;
the second injection region is an N-type conductive region;
the concentration of the first implanted region is higher than the concentration of the second implanted region.
Preferably, an N-type channel is formed between the first and second implanted regions, the channel has a width of 20 nm and a thickness of 5 nm, and the N-type channel is on the P-type semiconductor;
and a silicon dioxide insulating layer with the thickness of 0.01-0.4 micron is formed above the N-type channel.
Preferably, the first region and the second region are respectively provided with an insulating plate on the upper layer, and the insulating plate comprises:
a first insulating layer: formed on the first region; a second insulating layer: formed on the second region;
the first insulating layer is prepared by local oxidation at 800 +/-5 ℃ and under the water vapor pressure of 20 standard atmospheric pressures, and the thickness of the first insulating layer is 0.05-0.1 micrometer;
the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800 + -5 deg.C and has a thickness of 0.1-0.2 μm.
Preferably, the silicon dioxide insulating layer includes:
attaching a photoresist mask on the upper part of the silicon dioxide insulating layer, removing the photoresist mask if the silicon dioxide insulating layer is etched, heating at 800 +/-5 ℃, and forming an additional photoresist mask on the silicon dioxide insulating layer by a standard photoetching method; if the silicon dioxide insulating layer does not have the etching phenomenon, the silicon dioxide insulating layer does not need to be processed; the additional photoresist mask has a thickness of 0.5-1.5 microns.
Preferably, the material of the P-type semiconductor substrate is silicon;
the thickness of the first insulating layer and the second insulating layer is 1 to 20 times of that of the silicon dioxide insulating layer;
and a channel is formed between the first injection region and the second injection region and is made of silicon.
Preferably, step S710: a semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
step S720: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed in the first region;
step S730: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
step S740: insulating plates are respectively arranged on the upper layers of the first area and the second area.
Preferably, in step S730, the step of forming the first region and the second region in a coplanar manner includes:
step S731: the first injection region and the second injection region are injected by ions;
step S732: forming an N + type conductive region in the first implantation region by ion implantation;
step S733: forming an N-type conductive region in the second implantation region by ion implantation;
step S734: making the concentration of the first implantation region higher than that of the second implantation region;
step S735: an N-type channel is formed between the first and second implant regions.
Preferably, in step S734, the forming an N-type channel between the first and second implantation regions includes:
step S7341: forming a first insulating layer on top of the first region, the first insulating layer being made by local oxidation at 800 ± 5 ℃ and a water vapor pressure of 20 standard atmospheres, and having a thickness of 0.05-0.1 μm;
step S7342: forming a second insulating layer on the second region, wherein the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800 +/-5 ℃ and has a thickness of 0.1-0.2 microns;
step S7343: and forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 microns above the N-type channel.
Preferably, in step S7343, the second silicon oxide insulating layer includes:
step S731: attaching a photoresist mask on the upper part of the silicon dioxide insulating layer;
step S732: if the silicon dioxide insulating layer is etched, the photoresist mask is removed, and is heated at a temperature of 800 + -5 deg.C, and an additional photoresist mask having a thickness of 0.5-1.5 μm is formed on the silicon dioxide insulating layer by a standard photolithography method.
Compared with the prior art, the invention has the following advantages:
the invention provides a semiconductor field effect integrated circuit, which is characterized in that two injection regions are used for injecting ions into the semiconductor integrated circuit, an insulating plate is arranged above the ion injection regions, the quality of N-type conductive contact is improved, a silicon dioxide insulating layer is arranged, impurities can be effectively prevented from permeating towards the surface of a substrate, and the reliability and the stability of a device integrated circuit are improved through N-type two ion doping with different concentrations.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a diagram illustrating an exemplary system for fabricating a semiconductor field effect integrated circuit according to an embodiment of the present invention;
FIG. 2 is a diagram of a system for manufacturing a semiconductor field effect integrated circuit according to an embodiment of the present invention;
fig. 3 is a diagram illustrating a step of forming an N-type channel between a first implanted region and a second implanted region in an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it should be understood that they are presented herein only to illustrate and explain the present invention and not to limit the present invention.
The embodiment of the invention provides a system and a method for preparing a semiconductor field effect integrated circuit.
Referring to fig. 1, a system for manufacturing a semiconductor field effect integrated circuit, comprising:
the semiconductor device comprises a P-type semiconductor substrate, a first area, a second area and an insulating plate;
a first region: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed in the first region;
a second region: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
insulating board: insulating plates are respectively arranged on the upper layers of the first area and the second area.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that the preparation system of the semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first area, a second area and an insulating plate. The first region is positioned on the left side of the semiconductor substrate, a first injection region is formed in the first region, the second region is positioned on the right side of the semiconductor substrate, a second injection region is formed in the second region, the first region and the second region are coplanar, and an insulating plate is respectively arranged on the upper layers of the first region and the second region.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, the first region and the second region are divided, ions with different concentrations are implanted for doping, and the implanted ions are directly combined with atoms and molecules on the surface of the material, so that the material has the phenomenon of difficult falling, is not controlled by temperature in the implantation process, and can be used for surface strengthening of the material which cannot be processed by the common method.
In another embodiment, the first region is coplanar with the second region, comprising:
the first injection region and the second injection region are injected by ions;
the first injection region is an N + type conductive region;
the second injection region is an N-type conductive region;
the concentration of the first implanted region is higher than the concentration of the second implanted region.
The working principle of the technical scheme is as follows: in this embodiment, an N + type conductive region is implanted into a first implantation region in the first region, and an N-type conductive region is implanted into a second implantation region in the second region, where the implantation concentration of the first implantation region is higher than that of the second implantation region.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, ions with different concentrations can be conveniently implanted through the two ion implantation areas.
In another embodiment, the first and second implantation regions are implanted by ion implantation, including:
an N-type channel is formed between the first and second implanted regions, the channel having a width of 20 nm and a thickness of 5 nm, and the N-type channel is on the P-type semiconductor upper layer.
And a silicon dioxide insulating layer with the thickness of 0.01-0.4 micron is formed above the N-type channel.
The working principle of the technical scheme is as follows: in the scheme adopted by this embodiment, an N-type channel is formed in the first injection region and the second injection region, a source of the field effect transistor of the N-type channel is connected to an N-type semiconductor, and two electrodes are led out by using metal aluminum to respectively serve as a drain and a source. The channel width is 20 nanometers, the depth is 5-100 nanometers, and an N-type channel is on the P-type semiconductor. And a silicon dioxide insulating layer with the thickness of 0.01-0.4 microns is formed above the N-type channel, and an aluminum electrode is deposited between the drain electrode and the source electrode, namely above the silicon dioxide insulating layer with the thickness of 0.01-0.4 microns, and is used as a gate ohmic contact electrode.
The current of the integrated circuit is measured by testing the turn-on voltage of the integrated circuit, namely the subthreshold value, and the formula is as follows:
wherein ,Io Is the starting current of the integrated circuit, V GS Is the voltage of the gate and source, V T A voltage of strong inversion occurs for the semiconductor substrate,
the proportion of the barrier part of the source region and the channel region is shown, q is the charge carried by the implanted ions, k is the number of the implanted regions, and T is the temperature of the implanted ions.
The current conduction speed can be judged according to the subthreshold swing, and whether the switching performance of the device is good or not is deduced, wherein the formula is as follows:
wherein ,dD Thickness of gate depletion layer, d ox For the thickness of the gate oxide layer, the smaller the value of the swing S of the subthreshold is, the better the device performance is.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, a smaller design size can be obtained by using the N-type channel, the switching speed of the integrated circuit is improved, the integration level of the circuit is facilitated, the power consumption is reduced, and the circuit is compatible with a bipolar circuit.
In another embodiment, the first region and the second region are respectively provided with an insulating plate on top, comprising:
a first insulating layer: formed on the first region; a second insulating layer: formed on the second region;
the first insulating layer is prepared by local oxidation at 800 +/-5 ℃ and under the water vapor pressure of 20 standard atmospheric pressures, and the thickness of the first insulating layer is 0.05-0.1 micrometer;
the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800 + -5 deg.C and has a thickness of 0.1-0.2 μm.
The working principle of the technical scheme is as follows: this embodiment adopts a scheme that a first insulating layer is formed on the upper portion of the first region, a second insulating layer is formed on the upper portion of the second region, and the first insulating layer is made by local oxidation at 800 ± 5 ℃ and under a water vapor pressure of 20 standard atmospheres, and has a thickness of 0.05-0.1 micrometer; the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800 + -5 deg.C and has a thickness of 0.1-0.2 μm.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, the insulating layer is locally oxidized to prevent voltage breakdown, and the insulating layer has good chemical stability and electrical insulation.
In another embodiment, the silicon dioxide insulating layer includes:
attaching a photoresist mask on the upper part of the silicon dioxide insulating layer, removing the photoresist mask if the silicon dioxide insulating layer is etched, heating at 800 +/-5 ℃, and forming an additional photoresist mask on the silicon dioxide insulating layer by a standard photoetching method; if the silicon dioxide insulating layer does not have the etching phenomenon, the silicon dioxide insulating layer does not need to be processed; the additional photoresist mask has a thickness of 0.5-1.5 microns.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that a layer of photoresist mask is attached to the upper part of the silicon dioxide insulating layer, if the silicon dioxide insulating layer is etched, the photoresist mask is removed, the silicon dioxide insulating layer is heated at the temperature of 800 +/-5 ℃, and then ultraviolet light irradiates the surface of the insulating layer attached with a layer of photoresist film through a mask plate by a standard photoetching method to cause the photoresist in an exposure area to generate chemical reaction; dissolving and removing the photoresist in the exposed area or the unexposed area by a developing technology, so that the pattern on the mask is copied to the photoresist film; and finally, transferring the pattern to the insulating layer by utilizing an etching technology. And forming an additional photoresist mask on the silicon dioxide insulating layer; if the silicon dioxide insulating layer does not have the etching phenomenon, the silicon dioxide insulating layer does not need to be processed; the additional photoresist mask has a thickness of 0.5-1.5 microns.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, the photoresist mask is attached to the silicon dioxide insulating layer, so that the problem that the insulating layer loses the insulating effect to cause electrification of an integrated circuit when the silicon dioxide insulating layer is etched can be effectively prevented.
In another embodiment, the material of the P-type semiconductor substrate is silicon;
the thickness of the first insulating layer and the second insulating layer is 1 to 20 times of that of the silicon dioxide insulating layer;
and a channel is formed between the first injection region and the second injection region and is made of silicon.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that the substrate of the P-type semiconductor is made of silicon, and the thickness of the first insulating layer and the second insulating layer is 1 to 20 times that of the silicon dioxide insulating layer; a channel is formed between the first injection region and the second injection region, the channel is made of silicon, and the concentration of ions injected into the channel is 2 multiplied by 10 20 To 3X 10 20 cm -3 。
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, the ion implantation concentration can be accurately and controllably mastered, various devices are changed in size along with the continuous change of the size of the integrated circuit, and the doping concentration and depth can be repeatedly controlled by ion implantation.
In another embodiment, referring to fig. 2, a method for fabricating a semiconductor field effect integrated circuit includes the steps of:
step S710: a semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
step S720: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed in the first region;
step S730: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
step S740: insulating plates are respectively arranged on the upper layers of the first area and the second area.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that the semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first area, a second area and an insulating plate; a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed in the first region; a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar; insulating plates are respectively arranged on the upper layers of the first area and the second area.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, the first region and the second region are divided, ions with different concentrations are implanted for doping, and the implanted ions are directly combined with atoms and molecules on the surface of the material, so that the material is not easy to fall off, and the material is not controlled by temperature in the implantation process, and can be subjected to surface strengthening on the material which cannot be processed by a common method.
In another embodiment, in step S730, the first region and the second region are coplanar, including:
step S731: the first injection region and the second injection region are injected by ions;
step S732: forming an N + type conductive region in the first implantation region by ion implantation;
step S733: forming an N-type conductive region in the second implantation region by ion implantation;
step S734: making the concentration of the first implantation region higher than that of the second implantation region;
step S735: an N-type channel is formed between the first and second implant regions.
The working principle of the technical scheme is as follows: the scheme adopted by this embodiment is that the first implantation region and the second implantation region are implanted by ion implantation, an N + -type conductive region is formed in the first implantation region by ion implantation, an N-type conductive region is formed in the second implantation region by ion implantation, the concentration of the first implantation region is higher than that of the second implantation region, and an N-type channel is formed between the first implantation region and the second implantation region.
And forming an N-type channel in the first injection region and the second injection region, connecting a source electrode of a field effect transistor of the N-type channel to an N-type semiconductor, and leading out two electrodes by using metal aluminum to respectively serve as a drain electrode and a source electrode. The channel width is 20 nanometers, the thickness is 5 nanometers, and an N-type channel is on the P-type semiconductor. And a silicon dioxide insulating layer with the thickness of 0.01-0.4 microns, namely a grid oxide layer, is formed above the N-type channel, and an aluminum electrode is deposited on the silicon dioxide insulating layer between the drain electrode and the source electrode to be used as an ohmic contact electrode of the grid.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, a smaller design size can be obtained by using the N-type channel, the switching speed of the integrated circuit is improved, the integration level of the circuit is facilitated, the power consumption is reduced, and the bipolar circuit is compatible.
In another embodiment, referring to fig. 3, in step S734, forming an N-type channel between the first and second implant regions includes:
step S7341: forming a first insulating layer on top of the first region, the first insulating layer being made by local oxidation at 800 ± 5 ℃ and a water vapor pressure of 20 standard atmospheres, and having a thickness of 0.05-0.1 μm;
step S7342: forming a second insulating layer on the second region, the second insulating layer being formed in a dry oxygen atmosphere at a temperature of 800 ± 5 ℃ and having a thickness of 0.1 to 0.2 μm;
step S7343: and forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 microns, namely a grid oxide layer, above the N-type channel.
The working principle of the technical scheme is as follows: this embodiment adopts a scheme that a first insulating layer is formed on the upper portion of the first region, the first insulating layer is made by local oxidation at 800 ± 5 ℃ and under the water vapor pressure of 20 standard atmospheres, and the thickness is 0.05-0.1 micrometer; forming a second insulating layer on the second region, the second insulating layer being formed in a dry oxygen atmosphere at a temperature of 800 ± 5 ℃ and having a thickness of 0.1 to 0.2 μm; and forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 microns, namely a grid oxide layer, above the N-type channel.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, a smaller design size can be obtained by using the N-type channel, the switching speed of the integrated circuit is improved, the integration level of the circuit is facilitated, the power consumption is reduced, and the circuit is compatible with a bipolar circuit.
In another embodiment, in step S7343, the second silicon oxide insulating layer includes:
step S731: attaching a photoresist mask on the upper part of the silicon dioxide insulating layer;
step S732: if the silicon dioxide insulating layer is etched, the photoresist mask is removed and heated at a temperature of 800 + -5 deg.C, and then an additional photoresist mask having a thickness of 0.5-1.5 μm is formed on the silicon dioxide insulating layer by a standard photolithography method.
The working principle of the technical scheme is as follows: the scheme adopted by the embodiment is that a layer of photoresist mask is attached to the upper part of the silicon dioxide insulating layer; if the silicon dioxide insulating layer is etched, the photoresist mask is removed and heated at a temperature of 800 + -5 deg.C, and then an additional photoresist mask having a thickness of 0.5-1.5 μm is formed on the silicon dioxide insulating layer by a standard photolithography method.
The beneficial effects of the above technical scheme are: by adopting the scheme provided by the embodiment, the photoresist mask is attached to the silicon dioxide insulating layer, so that the problem that the insulating layer loses the insulating effect to cause electrification of an integrated circuit when the silicon dioxide insulating layer is etched can be effectively prevented.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A system for fabricating a semiconductor field effect integrated circuit, comprising:
the semiconductor device comprises a P-type semiconductor substrate, a first area, a second area and an insulating plate;
a first region: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed in the first region;
a second region: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
insulating board: the insulating plates are respectively arranged on the upper layers of the first area and the second area.
2. The system of claim 1, wherein the first region is coplanar with the second region, comprising:
the first injection region and the second injection region are injected by ions;
the first injection region is an N + type conductive region;
the second injection region is an N-type conductive region;
the concentration of the first implanted region is higher than the concentration of the second implanted region.
3. The system of claim 1, wherein the first and second implanted regions are implanted by ion implantation, comprising:
forming an N-type channel between the first injection region and the second injection region, wherein the width of the channel is 20 nanometers, the depth of the channel is 5-100 nanometers, and the N-type channel is arranged on the upper layer of the P-type semiconductor;
and a silicon dioxide insulating layer with the thickness of 0.01-0.4 micrometer is formed above the N-type channel.
4. The system of claim 1, wherein the first region and the second region each have an insulating plate disposed thereon, the system comprising:
a first insulating layer: formed on the first region; a second insulating layer: formed on the second region;
the first insulating layer is prepared by local oxidation at 800 +/-5 ℃ and under the water vapor pressure of 20 standard atmospheric pressures, and the thickness of the first insulating layer is 0.05-0.1 micrometer;
the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800 + -5 deg.C and has a thickness of 0.1-0.2 μm.
5. The system of claim 3, wherein the silicon dioxide insulating layer comprises:
attaching a photoresist mask on the upper part of the silicon dioxide insulating layer, removing the photoresist mask if the silicon dioxide insulating layer is etched, heating at 800 +/-5 ℃, and forming an additional photoresist mask on the silicon dioxide insulating layer by a standard photoetching method; if the silicon dioxide insulating layer does not have the etching phenomenon, the silicon dioxide insulating layer does not need to be processed; the additional photoresist mask has a thickness of 0.5-1.5 microns.
6. The system of claim 1 or 4, comprising:
the P-type semiconductor substrate is made of silicon;
the thickness of the first insulating layer and the second insulating layer is 1 to 20 times of that of the silicon dioxide insulating layer;
and a channel is formed between the first injection region and the second injection region and is made of silicon.
7. A method for manufacturing a semiconductor field effect integrated circuit, comprising the steps of:
step S710: a semiconductor field effect integrated circuit comprises a P-type semiconductor substrate, a first region, a second region and an insulating plate;
step S720: a first region is arranged on the left side of the semiconductor substrate, and a first injection region is formed in the first region;
step S730: a second region is arranged on the right side of the semiconductor substrate, a second injection region is formed in the second region, and the first region and the second region are coplanar;
step S740: insulating plates are respectively arranged on the upper layers of the first area and the second area.
8. The method as claimed in claim 7, wherein the step S730, wherein the step of forming the first region and the second region are coplanar comprises:
step S731: the first injection region and the second injection region are injected by ions;
step S732: forming an N + type conductive region in the first implantation region by ion implantation;
step S733: forming an N-type conductive region in the second implantation region by ion implantation;
step S734: making the concentration of the first implantation region higher than that of the second implantation region;
step S735: and forming an N-type channel between the first injection region and the second injection region.
9. The method as claimed in claim 7 or 8, wherein in step S734, forming an N-type channel between the first and second implanted regions comprises:
step S7341: forming a first insulating layer on top of the first region, the first insulating layer being made by local oxidation at 800 ± 5 ℃ and a water vapor pressure of 20 normal atmospheres, and having a thickness of 0.05-0.1 μm;
step S7342: forming a second insulating layer on the second region, wherein the second insulating layer is formed in a dry oxygen atmosphere at a temperature of 800 +/-5 ℃ and has a thickness of 0.1-0.2 microns;
step S7343: and forming a silicon dioxide insulating layer with the thickness of 0.01-0.4 microns above the N-type channel.
10. The method of claim 7, wherein in step S7343, the second insulating silicon oxide layer comprises:
step S731: attaching a photoresist mask on the upper part of the silicon dioxide insulating layer;
step S732: if the silicon dioxide insulating layer is etched, the photoresist mask is removed, and is heated at a temperature of 800 + -5 deg.C, and an additional photoresist mask having a thickness of 0.5-1.5 μm is formed on the silicon dioxide insulating layer by a standard photolithography method.
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