JPH09133928A - Thin-film transistor substrate for liquid-crystal display device and its manufacture - Google Patents
Thin-film transistor substrate for liquid-crystal display device and its manufactureInfo
- Publication number
- JPH09133928A JPH09133928A JP27048196A JP27048196A JPH09133928A JP H09133928 A JPH09133928 A JP H09133928A JP 27048196 A JP27048196 A JP 27048196A JP 27048196 A JP27048196 A JP 27048196A JP H09133928 A JPH09133928 A JP H09133928A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- display device
- crystal display
- liquid crystal
- transistor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 43
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 30
- 239000010409 thin film Substances 0.000 title claims description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 5
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 46
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 6
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 230000004913 activation Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 11
- 230000003213 activating effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nonlinear Science (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Liquid Crystal (AREA)
- Mathematical Physics (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は液晶表示装置用薄膜
トランジスタ基板およびその製造方法に係り、より詳し
くは、レーザビーム照射による活性化の際にこのレーザ
ビームの全透過が可能な絶縁層がゲート電極上に形成さ
れていて、ソース／ドレイン形成のためのイオン注入時
にゲート電極が損傷されることを防止する液晶表示装置
用薄膜トランジスタ基板およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a liquid crystal display device and a method of manufacturing the same, and more particularly, to an insulating layer capable of transmitting a laser beam when activated by irradiation with a laser beam. The present invention relates to a thin film transistor substrate for a liquid crystal display device, which is formed on the substrate and prevents damage to a gate electrode during ion implantation for forming a source / drain, and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】一般に、液晶表示装置は薄膜トランジス
タおよび画素電極による多数の画素単位が行列の形態で
形成されており、ゲートラインおよびデータラインがそ
れぞれ画素行と画素列に沿って形成されている薄膜トラ
ンジスタ基板と、共通電極が形成されているカラーフィ
ルタ基板およびその間に封じ入れている液晶物質を含ん
でいる。2. Description of the Related Art Generally, in a liquid crystal display device, a large number of pixel units including thin film transistors and pixel electrodes are formed in a matrix, and gate lines and data lines are formed along pixel rows and pixel columns, respectively. It includes a substrate, a color filter substrate on which a common electrode is formed, and a liquid crystal material enclosed between them.
【０００３】このとき、前記薄膜トランジスタ基板およ
びそのゲート電極は、ゲート駆動ドライブからのゲート
駆動信号がゲートラインを介して入力されアクティブ層
にチャンネルを形成させる。これによってデータ駆動ド
ライブからのデータ信号が前記データラインを通じてソ
ース電極に伝達され、半導体層とドレイン電極を経て画
素電極に伝達される。At this time, a gate drive signal from a gate drive drive is input to the thin film transistor substrate and the gate electrode thereof through a gate line to form a channel in the active layer. Accordingly, the data signal from the data driving drive is transmitted to the source electrode through the data line and then to the pixel electrode through the semiconductor layer and the drain electrode.
【０００４】このような液晶表示装置はアクティブ層を
多結晶シリコンを用いて形成することができる。このと
き、多結晶シリコンで形成したアクティブ層にソース／
ドレイン領域を形成するために不純物イオンを注入して
活性化する方法として、工程中の温度に基づいて高温工
程と低温工程とに分けることができる。まず、高温工程
は高いイオン電流あるいは高い基板温度、すなわち２０
０℃ないし３００℃におけるイオンシャワー注入技術を
用いる方法である。この方法では、イオンシャワー注入
の際にフォトレジストマスクの使用が難しく金属マスク
を使用する工程が必要になり、これによって製造工程が
複雑で生産費用が多くかかるという短所がある。In such a liquid crystal display device, the active layer can be formed by using polycrystalline silicon. At this time, the source / source is added to the active layer formed of polycrystalline silicon.
The method of implanting and activating impurity ions to form the drain region can be divided into a high temperature step and a low temperature step based on the temperature during the step. First, the high temperature process involves high ion current or high substrate temperature, that is, 20
This is a method using an ion shower implantation technique at 0 ° C to 300 ° C. This method has a disadvantage in that it is difficult to use a photoresist mask during ion shower implantation, and a step of using a metal mask is required, which complicates the manufacturing process and increases the production cost.
【０００５】次に、低温工程は低い温度、すなわち１０
０℃以下の基板温度でイオン注入を行い、この後レーザ
を用いて活性化する方法である。このようなレーザを用
いた活性化方法では、レーザ照射を行う際にゲート電極
が露出しているため、急激な熱膨張によるヒルロックが
発生する。特に、ゲート電極がイオン注入工程を経た後
ゲート電極内に不純物が流入されるとき、レーザ波長に
対する吸収係数が急激に増加してヒルロックの発生がさ
らに激しくなるという問題点がある。Next, the low temperature process is performed at a low temperature, that is, 10
This is a method in which ion implantation is performed at a substrate temperature of 0 ° C. or lower, and thereafter, activation is performed using a laser. In the activation method using such a laser, since the gate electrode is exposed when performing laser irradiation, hill lock occurs due to rapid thermal expansion. In particular, when impurities are introduced into the gate electrode after the gate electrode has undergone the ion implantation process, the absorption coefficient for the laser wavelength sharply increases, causing hillocks to become more severe.
【０００６】[0006]
【発明が解決しようとする課題】本発明の目的は、低い
基板温度でアクティブ層のソース／ドレイン領域にイオ
ン注入を行う低温工程を用いることにより製造コストを
低減するとともに、レーザビームの照射により活性化を
行う際に、ゲート電極の損傷を防止することが可能な液
晶表示装置用薄膜トランジスタ基板およびその製造方法
を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to reduce manufacturing cost by using a low temperature process in which source / drain regions of an active layer are ion-implanted at a low substrate temperature, and to activate by laser beam irradiation. An object of the present invention is to provide a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same, which can prevent the gate electrode from being damaged when the film is formed.
【０００７】[0007]
【課題を解決するための手段】本発明に係る液晶表示装
置用薄膜トランジスタ基板は、基板上に形成されている
多結晶シリコン膜と、多結晶シリコン膜上に形成されて
いるゲート絶縁膜と、ゲート絶縁膜上に形成されている
ゲート電極と、ゲート電極上に形成され、ゲート電極の
損傷を防止する絶縁膜とを含む。A thin film transistor substrate for a liquid crystal display device according to the present invention comprises a polycrystalline silicon film formed on the substrate, a gate insulating film formed on the polycrystalline silicon film, and a gate. It includes a gate electrode formed on the insulating film and an insulating film formed on the gate electrode to prevent damage to the gate electrode.
【０００８】ここで、絶縁膜として、レーザビームが透
過可能な絶縁物質を用いて形成することができ、さらに
照射されるレーザビームのエネルギーバンドキャップよ
り大きいバンドキャップを有する絶縁物質で形成するこ
とが好ましい。具体的には、二酸化ケイ素（ＳｉＯ2 ）
または窒化ケイ素（ＳｉＮｘ）で形成することができ
る。Here, the insulating film can be formed using an insulating material that can transmit a laser beam, and can be formed using an insulating material having a band cap larger than the energy band cap of the laser beam to be irradiated. preferable. Specifically, silicon dioxide (SiO 2 )
Alternatively, it can be formed of silicon nitride (SiNx).
【０００９】このことにより、多結晶シリコン膜で形成
された基板上のアクティブ層にレーザビームを照射する
ことによって不純物イオンの注入を行う際に、ゲート電
極上に位置する絶縁膜によって、注入されたイオンはゲ
ート電極の表面まで至ることなく、また活性化を行うた
めに照射されたレーザビームはこの絶縁膜を通過してゲ
ート電極の表面で全反射されることとなる。このことか
ら、ゲート電極の損傷を防止することができる。As a result, when the impurity ions are implanted by irradiating the active layer on the substrate formed of the polycrystalline silicon film with the laser beam, the impurity ions are implanted by the insulating film located on the gate electrode. Ions do not reach the surface of the gate electrode, and the laser beam irradiated for activation passes through this insulating film and is totally reflected on the surface of the gate electrode. Therefore, damage to the gate electrode can be prevented.
【００１０】さらに、本発明に係る液晶表示装置用薄膜
トランジスタ基板の製造方法は、基板上に多結晶シリコ
ン膜によるアクティブ層を形成する工程と、多結晶シリ
コン膜によるアクティブ層上にゲート絶縁膜を形成する
工程と、ゲート絶縁膜上に金属層を積層する工程と、金
属層上に金属層の損傷を防止する絶縁膜を積層する工程
と、金属層と絶縁膜とを同時にパターニングする工程
と、アクティブ層のソース／ドレイン領域に不純物イオ
ンを注入する工程と、ソース／ドレイン領域にイオン注
入された不純物をレーザビームを用いてアニーリングす
る工程とを含む。Further, in the method of manufacturing a thin film transistor substrate for a liquid crystal display device according to the present invention, a step of forming an active layer of a polycrystalline silicon film on the substrate and a gate insulating film formed on the active layer of the polycrystalline silicon film. A step of stacking a metal layer on the gate insulating film, a step of stacking an insulating film on the metal layer to prevent damage to the metal layer, a step of simultaneously patterning the metal layer and the insulating film, and It includes the steps of implanting impurity ions into the source / drain regions of the layer and the step of annealing the impurities implanted into the source / drain regions with a laser beam.
【００１１】ここで、アニーリングする工程で用いられ
るレーザビームとして、ＸｅＣｌを、用いることができ
る。Here, XeCl can be used as the laser beam used in the annealing step.
【００１２】[0012]
【発明の実施の形態】以下、本発明の好ましい実施例を
添付図面に基づいて詳細に説明する。図１は本発明の一
実施形態に従う液晶表示装置用薄膜トランジスタ基板を
示す断面図であり、図２ないし図８は本発明の実施形態
に従う液晶表示装置用薄膜トランジスタ基板の製造工程
を示す断面図である。Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention, and FIGS. 2 to 8 are sectional views showing a manufacturing process of the thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention. .
【００１３】まず、図２に示すように、基板２上に多結
晶シリコン膜を積層してアクティブ層４を形成する。次
に、図３に示すように、多結晶シリコン膜によるアクテ
ィブ層４上に酸化ケイ素（ＳｉＯ2 ）を用いてゲート絶
縁膜６を形成する。次に、図４に示すように、ゲート絶
縁膜６上にアルミニウム（Ａｌ）で金属層８を積層す
る。First, as shown in FIG. 2, a polycrystalline silicon film is laminated on a substrate 2 to form an active layer 4. Next, as shown in FIG. 3, a gate insulating film 6 is formed on the active layer 4 made of a polycrystalline silicon film by using silicon oxide (SiO 2 ). Next, as shown in FIG. 4, a metal layer 8 is laminated on the gate insulating film 6 with aluminum (Al).
【００１４】次に、図５に示すように、金属層８上に絶
縁膜１０を積層する。次に、図６に示すように、金属層
８と絶縁膜１０とを同時にパターニングする。次に、図
７に示すように、ｎ+ 不純物をイオン注入１２してイオ
ン注入領域４−１を形成する。Next, as shown in FIG. 5, an insulating film 10 is laminated on the metal layer 8. Next, as shown in FIG. 6, the metal layer 8 and the insulating film 10 are simultaneously patterned. Next, as shown in FIG. 7, n + impurities are ion-implanted 12 to form an ion-implanted region 4-1.
【００１５】次に、図８に示すように、アクティブ層４
にイオン注入された不純物をレーザビーム１４の照射に
よってアニーリングする。絶縁膜１０はバンドギャップ
が８．０ｅＶ程度であるＳｉＯ２で形成する。これは、
アニーリングを行うために照射する代表的なレーザビー
ムであるＸｅＣｌの波長が３０８ｎｍであるため、これ
をエネルギーの大きさで換算すると４．０ｅＶである。
従って、これよりバンドギャップが大きい絶縁膜１０を
形成することにより、レーザビームの照射によるアニー
リングの際にゲート電極８が損傷されることを防止でき
る。Next, as shown in FIG.
The impurities ion-implanted into the substrate are annealed by irradiation with the laser beam 14. The insulating film 10 is formed of SiO2 having a band gap of about 8.0 eV. this is,
Since the wavelength of XeCl, which is a typical laser beam irradiated for performing annealing, is 308 nm, it is 4.0 eV when converted in terms of energy level.
Therefore, by forming the insulating film 10 having a band gap larger than that, it is possible to prevent the gate electrode 8 from being damaged during the annealing by the irradiation of the laser beam.
【００１６】また、絶縁膜１０としてバンドギャップエ
ネルギーが５ｅＶであるＳｉＮｘを用いることも可能で
ある。It is also possible to use SiNx having a bandgap energy of 5 eV as the insulating film 10.
【００１７】[0017]
【発明の効果】以上説明したように、本発明ではアクテ
ィブ層のソース／ドレイン領域に不純物イオンの注入を
行う際に、注入を行う不純物イオンがゲート電極に至る
ことを抑制することができ、ソース／ドレイン領域に注
入されたイオンを活性化する際に、照射されるレーザビ
ームを透過させることによってゲート電極の損傷を防止
できるという効果がある。As described above, according to the present invention, when the impurity ions are implanted into the source / drain regions of the active layer, it is possible to prevent the implanted impurity ions from reaching the gate electrode. When activating the ions implanted in the / drain region, there is an effect that the gate electrode can be prevented from being damaged by transmitting the irradiated laser beam.
【図１】本発明の一実施形態に従う液晶表示装置用薄膜
トランジスタ基板を示す断面図である。FIG. 1 is a cross-sectional view showing a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
【図２】本発明の一実施形態に従う液晶表示装置用薄膜
トランジスタ基板の製造工程を示す断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
【図３】本発明の一実施形態に従う液晶表示装置用薄膜
トランジスタ基板の製造工程を示す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing process of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
【図４】本発明の一実施形態に従う液晶表示装置用薄膜
トランジスタ基板の製造工程を示す断面図である。FIG. 4 is a cross-sectional view showing a manufacturing process of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
【図５】本発明の一実施形態に従う液晶表示装置用薄膜
トランジスタ基板の製造工程を示す断面図である。FIG. 5 is a cross-sectional view showing a manufacturing process of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
【図６】本発明の一実施形態に従う液晶表示装置用薄膜
トランジスタ基板の製造工程を示す断面図である。FIG. 6 is a cross-sectional view showing a manufacturing process of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
【図７】本発明の一実施形態に従う液晶表示装置用薄膜
トランジスタ基板の製造工程を示す断面図である。FIG. 7 is a cross-sectional view showing a manufacturing process of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
【図８】本発明の一実施形態に従う液晶表示装置用薄膜
トランジスタ基板の製造工程を示す断面図である。FIG. 8 is a cross-sectional view showing a manufacturing process of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
２ 基板 ６ ゲート絶縁膜 ８ 金属層（ゲート電極） １０ 絶縁膜 2 substrate 6 gate insulating film 8 metal layer (gate electrode) 10 insulating film
Claims (11)
と、 前記多結晶シリコン膜上に形成されているゲート絶縁膜
と、 前記ゲート絶縁膜上に形成されているゲート電極と、 前記ゲート電極上に形成され、前記ゲート電極の損傷を
防止する絶縁膜と、を含む液晶表示装置用薄膜トランジ
スタ基板。1. A polycrystalline silicon film formed on a substrate, a gate insulating film formed on the polycrystalline silicon film, a gate electrode formed on the gate insulating film, and the gate. A thin film transistor substrate for a liquid crystal display device, comprising: an insulating film formed on an electrode to prevent damage to the gate electrode.
縁物質で形成されていることを特徴とする、請求項１に
記載の液晶表示装置用薄膜トランジスタ基板。2. The thin film transistor substrate for a liquid crystal display device according to claim 1, wherein the insulating film is formed of an insulating material that can transmit a laser beam.
ネルギーバンドギャップより大きいバンドギャップを有
する絶縁物質で形成されていることを特徴とする、請求
項１に記載の液晶表示装置用薄膜トランジスタ基板。3. The thin film transistor substrate for a liquid crystal display device according to claim 1, wherein the insulating film is formed of an insulating material having a bandgap larger than an energy bandgap of an irradiated laser beam.
形成されていることを特徴とする、請求項１に記載の液
晶表示装置用薄膜トランジスタ基板。4. The thin film transistor substrate for a liquid crystal display device according to claim 1, wherein the insulating film is formed of silicon dioxide (SiO 2 ).
成されていることを特徴とする、請求項１に記載の液晶
表示装置用薄膜トランジスタ基板。5. The thin film transistor substrate for a liquid crystal display device according to claim 1, wherein the insulating film is formed of silicon nitride (SiNx).
ブ層を形成する工程と、 前記多結晶シリコン膜によるアクティブ層上にゲート絶
縁膜を形成する工程と、 前記ゲート絶縁膜上に金属層を積層する工程と、 前記金属層上に前記金属層の損傷を防止する絶縁膜を積
層する工程と、 前記金属層と前記絶縁膜とを同時にパターニングする工
程と、 前記アクティブ層のソース／ドレイン領域に不純物イオ
ンを注入する工程と、 前記ソース／ドレイン領域にイオン注入された不純物を
レーザビームを用いてアニーリングする工程と、を含む
液晶表示装置用薄膜トランジスタ基板の製造方法。6. A step of forming an active layer of a polycrystalline silicon film on a substrate, a step of forming a gate insulating film on the active layer of the polycrystalline silicon film, and laminating a metal layer on the gate insulating film. A step of stacking an insulating film on the metal layer to prevent damage to the metal layer, a step of simultaneously patterning the metal layer and the insulating film, and impurities in the source / drain regions of the active layer. A method of manufacturing a thin film transistor substrate for a liquid crystal display device, which comprises a step of implanting ions, and a step of annealing the impurities implanted in the source / drain regions with a laser beam.
縁物質で形成することを特徴とする、請求項６に記載の
液晶表示装置用薄膜トランジスタ基板の製造方法。7. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 6, wherein the insulating film is formed of an insulating material that allows a laser beam to pass therethrough.
ネルギーバンドギャップより大きいバンドキャップを有
する絶縁物質で形成することを特徴とする、請求項６に
記載の液晶表示装置用薄膜トランジスタ基板の製造方
法。8. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 6, wherein the insulating film is formed of an insulating material having a band cap larger than an energy band gap of a laser beam irradiated. .
形成することを特徴とする、請求項６に記載の液晶表示
装置用薄膜トランジスタ基板の製造方法。9. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 6, wherein the insulating film is formed of silicon dioxide (SiO 2 ).
形成することを特徴とする、請求項６に記載の液晶表示
装置用薄膜トランジスタ基板の製造方法。10. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 6, wherein the insulating film is formed of silicon nitride (SiNx).
ザビームとしてＸｅＣｌを用いることを特徴とする、請
求項６に記載の液晶表示装置用薄膜トランジスタ基板の
製造方法。11. The method of manufacturing a thin film transistor substrate for a liquid crystal display device according to claim 6, wherein XeCl is used as a laser beam used in the annealing step.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1995P35200 | 1995-10-12 | ||
| KR1019950035200A KR100188090B1 (en) | 1995-10-12 | 1995-10-12 | Fabrication method of thin film transistor panel for lcd |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005172379A Division JP4312741B2 (en) | 1995-10-12 | 2005-06-13 | Thin film transistor substrate for liquid crystal display device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09133928A true JPH09133928A (en) | 1997-05-20 |
| JP3774278B2 JP3774278B2 (en) | 2006-05-10 |
Family
ID=19430017
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27048196A Expired - Fee Related JP3774278B2 (en) | 1995-10-12 | 1996-10-14 | Method for manufacturing thin film transistor substrate for liquid crystal display device |
| JP2005172379A Expired - Fee Related JP4312741B2 (en) | 1995-10-12 | 2005-06-13 | Thin film transistor substrate for liquid crystal display device and manufacturing method thereof |
| JP2008232509A Withdrawn JP2009048199A (en) | 1995-10-12 | 2008-09-10 | Thin film transistor substrate for liquid crystal display device and method for manufacturing the same |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005172379A Expired - Fee Related JP4312741B2 (en) | 1995-10-12 | 2005-06-13 | Thin film transistor substrate for liquid crystal display device and manufacturing method thereof |
| JP2008232509A Withdrawn JP2009048199A (en) | 1995-10-12 | 2008-09-10 | Thin film transistor substrate for liquid crystal display device and method for manufacturing the same |
Country Status (3)
| Country | Link |
|---|---|
| JP (3) | JP3774278B2 (en) |
| KR (1) | KR100188090B1 (en) |
| TW (1) | TWI246620B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6309917B1 (en) | 1999-05-10 | 2001-10-30 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor manufacturing method and thin film transistor |
| CN115497816A (en) * | 2022-10-19 | 2022-12-20 | 晋芯电子制造(山西)有限公司 | Preparation system and method of semiconductor field effect integrated circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101781175B1 (en) * | 2015-08-31 | 2017-09-22 | 가천대학교 산학협력단 | Junctionless field-effect transistor having ultra-thin low-crystalline-silicon channel and fabrication method thereof |
| CN109920731B (en) * | 2019-03-20 | 2021-03-19 | 上海华虹宏力半导体制造有限公司 | Polycrystalline silicon thin film transistor and manufacturing method thereof |
-
1995
- 1995-10-12 KR KR1019950035200A patent/KR100188090B1/en not_active IP Right Cessation
-
1996
- 1996-09-07 TW TW085110952A patent/TWI246620B/en not_active IP Right Cessation
- 1996-10-14 JP JP27048196A patent/JP3774278B2/en not_active Expired - Fee Related
-
2005
- 2005-06-13 JP JP2005172379A patent/JP4312741B2/en not_active Expired - Fee Related
-
2008
- 2008-09-10 JP JP2008232509A patent/JP2009048199A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6309917B1 (en) | 1999-05-10 | 2001-10-30 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor manufacturing method and thin film transistor |
| US6420760B2 (en) | 1999-05-10 | 2002-07-16 | Matsushita Electric Industrial Co., Ltd. | Thin film transistor manufacturing method and thin film transistor |
| CN115497816A (en) * | 2022-10-19 | 2022-12-20 | 晋芯电子制造(山西)有限公司 | Preparation system and method of semiconductor field effect integrated circuit |
| CN115497816B (en) * | 2022-10-19 | 2023-10-17 | 弘大芯源(深圳)半导体有限公司 | Semiconductor field effect integrated circuit and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4312741B2 (en) | 2009-08-12 |
| KR970024303A (en) | 1997-05-30 |
| TWI246620B (en) | 2006-01-01 |
| JP3774278B2 (en) | 2006-05-10 |
| JP2009048199A (en) | 2009-03-05 |
| JP2005326867A (en) | 2005-11-24 |
| KR100188090B1 (en) | 1999-07-01 |
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