TWI246620B - A thin film transistor for liquid crystal display and a method for manufacturing the same - Google Patents
A thin film transistor for liquid crystal display and a method for manufacturing the same Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 150000002500 ions Chemical class 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 229910004205 SiNX Inorganic materials 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000006866 deterioration Effects 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 239000004576 sand Substances 0.000 claims description 3
- 238000005496 tempering Methods 0.000 claims description 3
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 2
- 239000010408 film Substances 0.000 claims 2
- 239000011810 insulating material Substances 0.000 claims 2
- 239000000203 mixture Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000006731 degradation reaction Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 2
- 230000004913 activation Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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Abstract
Description
1246620 A7 五、發明說明（） 發明說明 發明之背景： (請先閱讀背面之注意事項再填寫本頁) ⑴發明之領域： 本發明係大致上有關於一種用於液晶顯示器之薄膜電 晶體以及其製造方法，更明確而言，係用於一種薄膜電晶 體’其中一陣列基板包括有在一閘極電極上之一絕緣層， 並在離子致動製程期間允許雷射光束之透射，藉由阻止植 入到一源極區域以及一汲極區域之離子損害到該閘極電極 ，而防止該閘極電極劣化。 ⑵先前技藝之說明： 一液晶顯示器(LCD)係由藉由一密封於其中之液晶材 料所分隔之兩片玻璃所組成。於一玻璃基板上之薄膜電晶 體(TFT)陣列具有複數個像素。各像素包括有一像素電極、 一於矩陣形式而鄰近該像素電極之薄膜電晶體、以及許多 位址和資料線，該等線係與各個像素形成爲一體以驅動並 控制該像素。一濾色器基板係另一塊玻璃板，其具有濾色 器’各個濾色器係面對於該TFT陣列基板之各個電極，並 且該等濾色器係由共通電極所覆蓋。 經濟部智慧財產局員工消費合作社印製 該TFT陣列基板以及該閘極電極係經由該閘極線接收 來自該閘極驅動器之閘極驅動信號，並且因而在該半導體 之一主動層上形成一通道。來自該資料驅動器之資料信號 係因此經由該資料線傳送至該源極電極。因此所施加之信 號最終係經由該半導體層以及該汲極電極而到達各個像素 電極。 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1246620 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 在此種LCD中，該主動層可由多晶矽所製成，並且離 子植入以及致動的製程可藉由兩種方法其中之一而實行； 其中一種是低溫方法而另外一種是高溫方法。 在該高溫製程中，植入之離子係藉由在大約900°C之 高溫致動製程所致動。在該低溫製程中，此種高溫製程無 法用於玻璃基板。該植入之離子則由一雷射光束所致動。 此種雷射致動製程可能帶來一種已知爲小丘(hillock) 的現象。因爲如此，當施加雷射光束時，該閘極電極變成 曝露，並且在該曝露之閘極電極產生劇烈的熱生成。如果 在該離子植入之製程期間，雜質係被導入該閘極電極中， 則此種缺點變得更爲嚴重，導致對應於該對照射之雷射光 束之吸收係數的劇烈增加。 發明之槪述： 如上所述之觀點，本發明之一目的爲提供一種TFT陣 列基板，其中具有一大的能帶間隙之絕緣層係形成於一閘 極電極上，以允許雷射光束之透射，以便防止在離子植入 源極區域以及汲極區域期間，離子會損害該閘極電極。 爲了達成上述目的，根據本發明之一較佳實施例，一 TFT陣列基板係由形成於一基板上之一多晶矽層所構成。 一閘極絕緣層係形成於該多晶矽層上。一閘極電極係形成 於該閘極絕緣層上，以及一絕緣層係形成於該閘極電極上 以防止該閘極電極劣化。 該TFT之陣列基板係藉由將一多晶矽層形成於一基板 上而製成。一閘極絕緣係形成於多晶矽層上。一金屬層係 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) . 丁 -ϋ mmml i^i ϋ i_l ^ V ·ϋ —Bi ·ϋ 1 ·ϋ ^1 _ 1246620 A7 B7 五、發明說明（） (請先閱讀背面之注意事項再填寫本頁) 沈積於該閘極絕緣層上。一絕緣層係沈積於該金屬層上以 允許雷射光束之透射’但防止閘極電極劣化。該金屬層係 與該絕緣層同時被形成圖樣。離子係植入該等形成圖樣的 層之兩側以產生一源極區域以及一汲極區域，並且該植入 的離子係利用一雷射光束來加以回火。 圖式之簡單說明： 第1圖顯示根據本發明之一 TFT陣列基板之橫剖面圖 ;以及 第2A圖至2G圖顯示根據本發明用於製造TFT陣列 基板之製程順序。 主要部份代表符號之簡要說明： 經濟部智慧財產局員工消費合作社印製 2基板 4主動層 4-1離子植入區域 6閘極絕緣層 8金屬層 10絕緣層 12 N+離子植入 14雷射光束 較佳實施例之詳細說明： 以下將參照附圖說明本發明之一較佳實施例。 第1圖顯示本發明之一 TFT陣列基板之剖面圖，而第 2A至2G圖顯示用以製造此TFT陣列基板的製程順序。 第2A圖至2G圖中根據本發明之製程步驟之所產生的 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 經濟部智慧財產局員工消費合作社印制衣 1246620 _____B7____ 五、發明說明（） 基板係如下所述。 該製程係由將一多晶砂層沈積於一基板2上以製成一 主動層4而開始，如第2A圖中所示。 一閘極絕緣層6係利用Si02沈積於該多晶矽層上，如 第2B圖中所不。 下一個製程步驟係藉由將鋁(A1)沈積於該絕緣層6上 而實行，以製成一金屬層8，如第2C圖中所示。 接下來，一絕緣層10係沈積於該金屬層8上，如第 2D圖中所示，而且該金屬層8以及該絕緣層10而後係大 致同時被形成圖樣，如第2E圖中所示。 如第2F圖中所示，N+離子植入12係實施以產生一離 子植入區域4-1。 如弟2G圖所不’上述步驟係藉由照射一^雷射光束14 而將植入之離子從該主動層4回火而完成。 該絕緣層10係由Si02所形成，具有一大約8.0eV的 能帶間隙，其係被發現足以防止閘極電極之劣化。這是因 爲大多數在回火步驟中所使用的典型的雷射光束XeCl具 有大約308mn之波長，其能量係爲4.0eV，而且此具有大 約8.0eV之絕緣層10可使非致動之雷射光束透射至該閘極 電極，但是該閘極金屬反射大部份的雷射能量。 另一方面，可使用具有5eV之能帶間隙能量的SiNx 作爲該絕緣層10。此可防止植入於該主動層之源極以及汲 極區域中的離子被傳送至該閘極電極，並且具有在該源極 和汲極區域之離子致動步驟期間，防止閘極電極因吸收雷 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)1246620 A7 V. INSTRUCTIONS () DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION: (Please read the note on the back and then fill out this page) (1) Field of the Invention: The present invention relates generally to a thin film transistor for a liquid crystal display and The manufacturing method, more specifically, is for a thin film transistor in which an array substrate includes an insulating layer on a gate electrode and allows transmission of the laser beam during the ion actuation process by blocking Ions implanted into a source region and a drain region damage the gate electrode and prevent the gate electrode from deteriorating. (2) Description of the prior art: A liquid crystal display (LCD) is composed of two sheets of glass separated by a liquid crystal material sealed therein. A thin film electromorph (TFT) array on a glass substrate has a plurality of pixels. Each pixel includes a pixel electrode, a thin film transistor adjacent to the pixel electrode in a matrix form, and a plurality of address and data lines that are integral with each pixel to drive and control the pixel. A color filter substrate is another glass plate having a color filter 'each color filter surface for each electrode of the TFT array substrate, and the color filters are covered by a common electrode. The Ministry of Economic Affairs Intellectual Property Office employee consumption cooperative prints the TFT array substrate and the gate electrode receives a gate driving signal from the gate driver via the gate line, and thus forms a channel on one active layer of the semiconductor . The data signal from the data drive is thus transmitted to the source electrode via the data line. Therefore, the applied signal eventually reaches the respective pixel electrodes via the semiconductor layer and the drain electrode. 4 The paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1246620 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 5, invention description () In this LCD, the active layer can be polycrystalline The process of ion implantation and actuation can be performed by one of two methods; one of which is a low temperature method and the other is a high temperature method. In this high temperature process, the implanted ions are actuated by a high temperature actuation process at about 900 °C. In this low temperature process, such a high temperature process cannot be used for a glass substrate. The implanted ions are caused by a laser beam. Such a laser-actuated process may introduce a phenomenon known as a hillock. Because of this, when a laser beam is applied, the gate electrode becomes exposed, and intense heat generation occurs at the exposed gate electrode. If impurities are introduced into the gate electrode during the ion implantation process, this disadvantage becomes more severe, resulting in a drastic increase in the absorption coefficient corresponding to the pair of irradiated laser beams. Summary of the Invention: As described above, it is an object of the present invention to provide a TFT array substrate in which an insulating layer having a large band gap is formed on a gate electrode to allow transmission of a laser beam In order to prevent ions from damaging the gate electrode during ion implantation of the source region and the drain region. In order to achieve the above object, according to a preferred embodiment of the present invention, a TFT array substrate is formed by a polysilicon layer formed on a substrate. A gate insulating layer is formed on the polysilicon layer. A gate electrode is formed on the gate insulating layer, and an insulating layer is formed on the gate electrode to prevent degradation of the gate electrode. The array substrate of the TFT is formed by forming a polysilicon layer on a substrate. A gate insulating layer is formed on the polysilicon layer. A metal layer 5 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the notes on the back and fill out this page). Ding-ϋ mmml i^i ϋ i_l ^ V · ϋ —Bi ·ϋ 1 ·ϋ ^1 _ 1246620 A7 B7 V. Inventive Note () (Please read the note on the back and fill out this page) Deposited on the gate insulation. An insulating layer is deposited on the metal layer to allow transmission of the laser beam 'but to prevent degradation of the gate electrode. The metal layer is patterned simultaneously with the insulating layer. Ionization is implanted on both sides of the patterned layers to create a source region and a drain region, and the implanted ion system is tempered using a laser beam. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a TFT array substrate according to the present invention; and Figs. 2A to 2G are views showing a process sequence for fabricating a TFT array substrate according to the present invention. Brief description of the main part of the symbol: Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printed 2 substrate 4 active layer 4-1 ion implantation area 6 gate insulation layer 8 metal layer 10 insulation layer 12 N + ion implantation 14 laser DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a cross-sectional view showing a TFT array substrate of the present invention, and Figs. 2A to 2G are diagrams showing a process sequence for fabricating the TFT array substrate. The paper scales produced in accordance with the process steps of the present invention in Figures 2A to 2G apply to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). A7 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed Clothing 1246620 _____B7____ V. INSTRUCTIONS () The substrate is as follows. The process begins by depositing a layer of polycrystalline sand on a substrate 2 to form an active layer 4, as shown in Figure 2A. A gate insulating layer 6 is deposited on the polysilicon layer by SiO 2 as shown in Fig. 2B. The next process step is carried out by depositing aluminum (A1) on the insulating layer 6 to form a metal layer 8, as shown in Fig. 2C. Next, an insulating layer 10 is deposited on the metal layer 8, as shown in Fig. 2D, and the metal layer 8 and the insulating layer 10 are then substantially simultaneously patterned, as shown in Fig. 2E. As shown in Fig. 2F, the N+ ion implant 12 is implemented to produce an ion implantation region 4-1. The above steps are accomplished by illuminating the implanted ions from the active layer 4 by illuminating a laser beam 14. The insulating layer 10 is formed of SiO 2 and has an energy band gap of about 8.0 eV which is found to be sufficient to prevent deterioration of the gate electrode. This is because most of the typical laser beam XeCl used in the tempering step has a wavelength of about 308 nm and its energy is 4.0 eV, and this insulating layer 10 having about 8.0 eV can make a non-actuated laser. The beam is transmitted to the gate electrode, but the gate metal reflects most of the laser energy. On the other hand, SiNx having an energy band gap energy of 5 eV can be used as the insulating layer 10. This prevents ions implanted in the source and drain regions of the active layer from being transferred to the gate electrode and having the gate electrode prevented from being absorbed during the ion actuation step of the source and drain regions Ray 7 This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) (please read the notes on the back and fill out this page)
1246620 A7 B7 五、發明說明（） 射光束能量而劣化的功效。 應瞭解的是各種其它的修正對於熟知此項技藝者將是 明顯而能輕易完成的’且不背離本發明之範疇以及精神。 因此所附之申請專利範圍的範疇並非意在限制於在此所述 之說明，而是申請專利範圍係被解釋成可含蓋本發明中所 有之可專利之新穎的特徵’包括熟知相關本發明之技藝者 所視爲等效之所有特徵。 (請先閱讀背面之注意事項再填寫本頁) t 訂---------· 經濟部智慧財產局員Η消費合作社印製 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）1246620 A7 B7 V. INSTRUCTIONS () The effect of degrading the beam energy. It will be appreciated that various other modifications will be apparently and readily apparent to those skilled in the art without departing from the scope and spirit of the invention. Therefore, the scope of the appended claims is not intended to be limited to the description herein, but the scope of the claims is to be construed as covering all of the patentable novel features of the invention. All features that the artist considers equivalent. (Please read the notes on the back and fill out this page) t Order---------· Ministry of Economic Affairs Intellectual Property Bureau Η Consumer Cooperative Print 8 This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm)
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950035200A KR100188090B1 (en) | 1995-10-12 | 1995-10-12 | Fabrication method of thin film transistor panel for lcd |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TWI246620B true TWI246620B (en) | 2006-01-01 |
Family
ID=19430017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW085110952A TWI246620B (en) | 1995-10-12 | 1996-09-07 | A thin film transistor for liquid crystal display and a method for manufacturing the same |
Country Status (3)
| Country | Link |
|---|---|
| JP (3) | JP3774278B2 (en) |
| KR (1) | KR100188090B1 (en) |
| TW (1) | TWI246620B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3318285B2 (en) | 1999-05-10 | 2002-08-26 | 松下電器産業株式会社 | Method for manufacturing thin film transistor |
| KR101781175B1 (en) * | 2015-08-31 | 2017-09-22 | 가천대학교 산학협력단 | Junctionless field-effect transistor having ultra-thin low-crystalline-silicon channel and fabrication method thereof |
| CN109920731B (en) * | 2019-03-20 | 2021-03-19 | 上海华虹宏力半导体制造有限公司 | Polycrystalline silicon thin film transistor and manufacturing method thereof |
| CN115497816B (en) * | 2022-10-19 | 2023-10-17 | 弘大芯源(深圳)半导体有限公司 | Semiconductor field effect integrated circuit and preparation method thereof |
-
1995
- 1995-10-12 KR KR1019950035200A patent/KR100188090B1/en not_active IP Right Cessation
-
1996
- 1996-09-07 TW TW085110952A patent/TWI246620B/en not_active IP Right Cessation
- 1996-10-14 JP JP27048196A patent/JP3774278B2/en not_active Expired - Fee Related
-
2005
- 2005-06-13 JP JP2005172379A patent/JP4312741B2/en not_active Expired - Fee Related
-
2008
- 2008-09-10 JP JP2008232509A patent/JP2009048199A/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09133928A (en) | 1997-05-20 |
| JP2005326867A (en) | 2005-11-24 |
| KR970024303A (en) | 1997-05-30 |
| JP3774278B2 (en) | 2006-05-10 |
| JP2009048199A (en) | 2009-03-05 |
| JP4312741B2 (en) | 2009-08-12 |
| KR100188090B1 (en) | 1999-07-01 |
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