JPH11354627A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power IC of high integration density which does not generate malfunctions for a peripheral circuit of an output element, even if a surge input to the output element is generated. SOLUTION: High resistivity semiconductor layers 17, 14, 15, 16 are formed on a low resistivity semiconductor substrate 2, and embedding layers 24, 21, 32, 34 are formed in the upper part of the high resistivity semiconductor layers 17, 14, 15, 16. Furthermore, wells 41, 31 to 35, base regions 61, 62, 63, 64 inside the wells 32 to 35, electrode regions 81 to 88, etc., are formed in the upper part of the embedding layers 24, 21, 32, 34 in a power IC. Since current amplification ratio (hfe ) of parasitic bipolar transistors 221, 222, for which a first embedding layer 22 is an emitter, the semiconductor substrate 2 is a base and second embedding layers 21, 23 are a collector, is small, isolation is possible with only a trench isolation region 110.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor, a bipolar transistor, an IGBT (Insulated Gate Bipolar Transistor).
Power IC or IPD (Intelligent Power Device) in which devices such as nsistors or thyristors are integrated on the same chip.
The present invention relates to a semiconductor device called e), and more particularly to a semiconductor integrated circuit in which each device is separated by trench isolation. In particular, the present invention relates to a dynamic element isolation technique when a surge voltage is applied to an element in an output stage from a load side of a power IC (or IPD).

[0002]

2. Description of the Related Art As shown in FIG. 20, an n-type MOS transistor (hereinafter referred to as "nMOS") portion 122, a pnp-type Bipolar transistor section 123, trench gate type power MO
Power IC with separated and formed SFET sections 125 and 127
It has been known. In a conventional power IC of this kind, n ⁺ buried layers (NBL) 21, 22, 23 and p necessary for each device configuration are formed on the upper surface of a p-type substrate 1 having a resistivity of about 0.5 Ω · cm to 5 Ω · cm. Well regions (PWL) 41, 42, 4
3 and n-well regions (NWL) 31, 32 to 35 are formed.

The p-type substrate 1 has a p-well region 4
2, 43 and p ⁺ contact regions 74, 77 are connected to the ground potential at two p-type substrate contact portions 124, 126, and the potential is fixed. As a result, p
Mold substrate 1 and devices 122, 1 formed on the upper surface thereof
Parasitic diodes formed between the n-type semiconductor regions of the semiconductor devices 23, 125, and 127 are prevented from being in a forward direction, that is, a conductive state.

Further, the p-type substrate contact portions 124 and 12
6 is a parasitic npn bipolar transistor 200, 2 formed between each device 122, 123, 125, 127.
By thickening the 10 base width W _B of each device 122,
It also functions as an area for preventing mutual interference of the elements 23, 125, and 127. That is, the parasitic npn bipolar transistor base width W _B of 200 and 210 by a certain thickness, a buffer area for lowering the current amplification factor h _fe, parasitic npn bipolar transistor 200 and 210 to prevent work easily This region also has the function of In order to make the current amplification factor h _fe smaller than a predetermined value, the p-type substrate contact portion 124,
126 needs to keep its width at a relatively large value of about 20 to 70 μm. For example, for a 1A class transistor, the current amplification factor h _fe is suppressed to about 0.01 times or less, and the parasitic npn bipolar transistor 200,
It is necessary to avoid being affected by 210. Since the control transistor mounted on the power IC is affected by even a smaller current, the current amplification factor h _fe must be suppressed to a smaller value.

In particular, the transistors at the output stage such as the trench gate type power MOSFET units 125 and 127 shown in FIG. 20 are in an operating environment which is easily affected by external surge noise. That is, the output stage transistor 12
5,127 n ⁺ buried layer 22 serving as a buried drain region,
23 is generally connected to external electrode terminals (output terminals) of the semiconductor integrated circuit via n-type sinkers (NSK) 51 and 52, and thus causes a potential change due to external surge noise. When the surge noise from the external electrode terminal has a negative potential, the parasitic npn bipolar transistor 2
The n ⁺ buried layers 22 and ^{2 in the} drain region serving as the emitter from the ground potential of the p-type substrate 1 serving as the base of
Since the potential of 3 becomes low, the parasitic npn bipolar transistor is turned on, and there is a possibility that an adjacent device may malfunction. For example, when the surge noise of the negative potential is applied to the n ⁺ buried layer 22 serving as a buried drain region of the transistor of the output stage, the emitter of the n ⁺ embedded layer 22, based on a p-type substrate 1, n ⁺ buried Base current i _b of parasitic npn bipolar transistor 200 having layer 21 as a collector
Flows. Then, the parasitic npn bipolar transistor 2
00 of n ⁺ buried layer 21 is a base region of the adjacent pnp-type bipolar transistor 123 serving as a collector, toward the n ⁺ buried layer 22 serving as the emitter of the parasitic npn bipolar transistor 200 i _b · h _fe times The collector current _ic flows. That is, there is a possibility that the parasitic npn bipolar transistor 200 is turned on, the base potential of the pnp bipolar transistor 123 fluctuates, and the circuit malfunctions.

Similarly, a trench gate type power MOSFE
T127 and trench gate type power MOSFET 125
Is turned on, the trench gate type power MO
The drain potential of the SFET 127 changes. The influence on the circuit operation by the parasitic npn bipolar transistor as described above may affect not only between adjacent devices but also over a wide range.

When a surge noise of a negative potential is applied to the n ⁺ buried layer of the transistor in the output stage, a countermeasure for preventing the influence on other devices adjacent to the transistor in the output stage is a parasitic npn. The _{purpose is} to reduce the current amplification factor h _fe of the bipolar transistor. Specifically, as described above, a sufficient distance between the devices, a reduction in the resistance of the p-type substrate 1, or a p-type substrate contact portion 12 for suppressing fluctuations in the ground potential.
There is a method of arranging more 4,126. However, the method of lowering the resistance of the p-type substrate 1 lowers the withstand voltage between the p-type substrate 1 and the n ⁺ buried layers 21, 22, 23. For this reason, conventionally, each device 122, 123, 125, 12
A method of ensuring a sufficient distance between the seven has been mainly used.

FIG. 21 shows another example of the structure of a conventional power IC. This is different from FIG. 20 in that the dummy collector portion 128 formed by the n ⁺ buried layer 24, the n well region 36, and the n ⁺ contact region 94 and connected to the power supply potential is connected to the power MOSF.
It has a structure formed between ET125 and ET127. The parasitic npn bipolar transistor 21 formed between the power MOSFETs 125 and 127 in FIG.
0 is divided by the dummy collector unit 128 and a new parasitic np
forming n bipolar transistors 211 and 212,
Direct parasitic n between power MOSFETs 125 and 127
A pn bipolar transistor is not generated. In the case of this structure, the parasitic npn bipolar transistors 211 and 212 are connected to the n ⁺ buried layer 24 of the dummy collector portion.
Gate type power MOSFET1
N ⁺ buried layers 22, ² serving as drain regions 25, 127
3 for the formed as an emitter, the drain potential of one of the power MOSFET when the surge noise of the negative voltage is applied decreases the base current i _b flows, one of the parasitic npn bipolar transistor is turned on Also, since a current flows between the dummy collector unit 128, the other parasitic npn bipolar transistor does not turn on. Therefore, the other power MO
The drain current of the SFET does not flow, and no operation interference occurs between the power MOSFETs.

[0009]

The trench isolation technique composed of a trench sidewall oxide film and a trench buried polysilicon, etc., has a so-called static (static) element isolation which is not affected by a surge voltage or the like from an external environment. It has had some success. However, as described above, in a power IC having a structure in which a parasitic npn bipolar transistor is formed based on a p-type substrate connected to the ground potential and using the n ⁺ buried layer of the device on the upper surface as a collector and an emitter. However, there is a problem in dynamic (dynamic) element isolation performance when a negative potential surge noise is applied to a specific device (particularly, an element at an output stage). At this time, the base current of the parasitic npn bipolar transistor flows from the p-type substrate, and the parasitic npn bipolar transistor is turned on, which may cause malfunction of a circuit around the specific device.

Therefore, when the impurity density of the p-type substrate is increased to improve the dynamic element isolation performance and prevent the influence of the parasitic npn bipolar transistor, the n ⁺ buried layer existing at the bottom of the device region and the p-type A new problem arises in that the withstand voltage between the substrate and the substrate is reduced.

On the other hand, if a dummy collector portion is newly provided as shown in FIG. 21 in order to avoid the reduction of the withstand voltage, there is a problem that the area of the element isolation region is increased although the dynamic element isolation performance is improved. Occurs.

In other words, if devices having potential fluctuation layers are to be densely arranged, the base thickness of the parasitic npn bipolar transistors 200 and 210 formed by the p-type substrate 1 must be reduced, and the parasitic npn bipolar transistors _Will increase the current amplification factor h _fe . As a result, there is a problem that the high integration density of the power IC and the improvement of the dynamic element isolation performance, that is, the reduction of the current amplification factor h _fe of the parasitic npn bipolar transistor are incompatible with each other.

An object of the present invention is to propose a novel technique for overcoming this trade-off relationship, and to provide a semiconductor integrated circuit in which the current amplification factor h _fe of the parasitic npn bipolar transistor is low and the area of the element isolation region does not increase. To provide.

Another object of the present invention is to provide a semiconductor integrated circuit having a high withstand voltage and excellent dynamic (dynamic) separation between adjacent elements.

Still another object of the present invention is to provide a high-voltage and high-density integrated circuit which does not affect circuit elements around the output stage element even if a surge voltage is applied to the output stage element. It is to provide a semiconductor integrated circuit.

Still another object of the present invention is to provide a semiconductor integrated circuit which is inexpensive and has high reliability such as surge resistance.

Still another object of the present invention is to provide a semiconductor integrated circuit capable of preventing operation interference between devices due to a parasitic bipolar transistor even if the devices are arranged at a high density without requiring a special technique or a manufacturing process. Another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit which can be easily realized.

[0018]

In order to achieve the above object, a first feature of the present invention is that a semiconductor substrate of a first conductivity type and low resistivity is separated from each other by a trench isolation region on the semiconductor substrate. A first and a second semiconductor layer having a higher resistivity than the disposed semiconductor substrate; and a second conductive layer disposed on the first semiconductor layer and having a lower resistivity than the first and second semiconductor layers. The first buried layer of the mold and the first semiconductor layer are disposed separately from each other in the trench isolation region, are disposed above the second semiconductor layer, and are lower than the first and second semiconductor layers. A second buried layer of a second conductivity type having a resistivity, a first well disposed above the first buried layer, and the first well separated from each other by a trench isolation region And the second
And a first well having at least one main electrode region on the surface of the first well.
And a semiconductor integrated circuit such as a power IC having at least a second semiconductor element having at least one main electrode region on the surface of the second well. Here, the first conductivity type and the second conductivity type are opposite to each other. For example, if the first conductivity type is n-type,
The conductivity type is p-type. If the first conductivity type is p-type, the second conductivity type is p-type.
The conductivity type is n-type. The “at least one main electrode region on the surface of the first well” refers to an FET of the FET. It means a source region and a drain region, or a collector region and an emitter region of a bipolar transistor. Similarly, “at least one main electrode region on the surface of the second well” means a source region, a drain region, a collector region, an emitter region, or the like. The first and second semiconductor layers may be of the first conductivity type or the second conductivity type. It is sufficient if the semiconductor layer has a high resistivity that is depleted at a certain voltage. The first well and the second well may be of the first conductivity type or the second conductivity type. In addition, the first and second
The conductivity types of the wells may be the same conductivity type or the opposite conductivity types. The conductivity type of these wells may be appropriately selected according to the design specifications of the semiconductor integrated circuit.

In the first aspect of the present invention, the current amplification factor h _fe of a parasitic bipolar transistor having a first buried layer as an emitter, a semiconductor substrate as a base, and a second buried layer as a collector is a base. Since the resistivity of the semiconductor substrate of the first conductivity type is low, it is small. In addition, the semiconductor substrate and the first and second
By sandwiching the first and second semiconductor layers having high resistivity between the buried layer and the buried layer, the withstand voltage due to the direct formation of a pn junction between the low-resistivity semiconductor substrate and the buried layer with low resistivity Drop can be prevented. For this reason, a surge voltage is applied to an element in the output stage without arranging a special region such as a p-type substrate contact portion or a dummy collector portion composed of a p-well region / p ⁺ contact region described in the prior art. In this case, the influence on peripheral circuit elements can be suppressed. As a result, highly reliable device isolation can be achieved only with a trench isolation region having a simple structure and easy miniaturization, and high integration density can be easily achieved.

The resistivity of the first and second semiconductor layers according to the first feature of the present invention is preferably 50 Ω · cm or more, and the upper limit may be selected within a range allowed by the current semiconductor epitaxy technology. . For example, if extremely high-purity vapor phase epitaxy is performed, 6000 Ω · cm to 10,000
Although about Ω · cm can be realized, usually about 500 Ω · cm or more is not necessary. The thickness of the first and second semiconductor layers may be determined in consideration of the withstand voltage required for the power IC. For example, the thickness may be about 3 to 20 μm, more specifically, about 5 to 8 μm.

Further, depending on the rating of each semiconductor element mounted on the semiconductor integrated circuit, for example, the current amplification factor h _fe of the parasitic bipolar transistor is preferably set to 0.01 times or less. Of course, in a semiconductor device for a small signal, it is preferable to further reduce the current amplification factor h _fe .

According to a first feature of the present invention, the first buried layer is electrically connected to an external electrode terminal of the semiconductor integrated circuit via a second conductivity type low resistivity sinker. It is effective. “Electrically coupled” is intended to include not only a case where they are directly connected to each other but also a case where they are electrically connected to each other through another region or another element.
For example, a contact region of the sinker may be present above the sinker, and a metal wiring layer or the like, and in some cases, an element such as a resistor between the external electrode terminal and the contact region may be allowed. is there.

The first semiconductor device is a semiconductor device of an output stage, and the first buried layer is the first semiconductor device of the present invention when electrically connected to an external load of the semiconductor integrated circuit. The features have a more advantageous effect. In this case, the second semiconductor element may be a semiconductor element at the output stage, a circuit for driving and controlling the semiconductor element at the output stage, a protection circuit,
Furthermore, a small-signal semiconductor element constituting another sensor circuit or the like may be used.

A second feature of the present invention is that a first conductive type semiconductor substrate in a floating state and first and second conductive type first and second semiconductor substrates disposed on the semiconductor substrate in a trench isolation region are separated from each other. Embedded layer, a first well disposed above the first embedded layer, and the first well are separated from each other in a trench isolation region, and A second well disposed on the top, a first semiconductor element having at least one main electrode region on the surface of the first well, and a second semiconductor having at least one main electrode region on the surface of the second well And a semiconductor integrated circuit having at least a semiconductor element. Here, the first conductivity type and the second conductivity type are opposite to each other. Further, "at least one main electrode region" means a source region or a drain region of an FET, or a collector region or an emitter region of a bipolar transistor. The first well and the second well may be of the first conductivity type or the second conductivity type. The conductivity types of the first and second wells may be the same conductivity type or the opposite conductivity types. The conductivity type of the well may be appropriately selected according to the design specifications of the semiconductor integrated circuit.

According to the second feature of the present invention, since the semiconductor substrate serving as the base of the parasitic bipolar transistor is in a floating state, there is no inflow path of the base current of the parasitic bipolar transistor formed between each device, and the parasitic The bipolar transistor does not turn on. For this reason, even if a special region such as a p-type substrate contact portion or a dummy collector portion described in the related art is not disposed, the influence on peripheral circuit elements when a surge voltage is applied to an element at an output stage. Can be suppressed. As a result, even if each device is arranged at a high density using only the trench isolation region which has a simple structure and is easily miniaturized, operation interference between devices due to the parasitic bipolar transistor can be prevented. Therefore, according to the second feature of the present invention, since the circuit does not malfunction due to the influence of the external circuit or the like, a highly reliable semiconductor integrated circuit with high integration density can be realized.

A third feature of the present invention is a method for manufacturing a semiconductor integrated circuit including at least the following steps. That is, the method of manufacturing a semiconductor integrated circuit according to the third aspect of the present invention comprises the steps of: (a) forming a first conductive type low-resistivity semiconductor substrate on a first conductive type lower-resistivity semiconductor substrate in order; A step of successively epitaxially growing a first epi layer of the type, a second epi layer of the second conductivity type, and a third epi layer of the first conductivity type, (b) only in a predetermined portion of the third epi layer, A step of selectively forming a well of the second conductivity type; (c) forming a trench (trench) penetrating the third epi layer, the second epi layer, and the first epi layer; Forming at least a trench isolation region by filling with an insulator such as polysilicon. Here, the first conductivity type and the second conductivity type are opposite to each other. By forming the trench isolation region, the second epi layer is divided into a plurality of buried layers that are substantially electrically independent of each other.

One of the buried layers is an emitter,
The other one is a collector, and the current amplification factor h _fe of a parasitic bipolar transistor based on a semiconductor substrate is reduced by the presence of a low-resistivity semiconductor substrate functioning as a base. In addition, since the first epitaxial layer having a high resistivity is interposed between the semiconductor substrate and the first and second buried layers, a pn junction is directly formed between the semiconductor substrate having the first conductivity type and low resistivity and the buried layer. A reduction in breakdown voltage due to the formation can be prevented. This first
The resistivity of the epi layer is preferably 50 Ω · cm or more, and the upper limit may be selected within a range allowed by the current semiconductor epitaxy technology. For example, when extremely high-purity vapor phase epitaxy is performed, the resistivity of the first epi layer is 600
About 0 Ω · cm to 10000 Ω · cm can be realized.
The thickness of the first epi layer may be determined in consideration of the withstand voltage required for the power IC. For example, a value of about 3 to 20 μm may be selected as the thickness of the first epi layer.

As can be understood from the above description, the method of manufacturing a semiconductor integrated circuit according to the third feature of the present invention is different from the conventional method of manufacturing a semiconductor integrated circuit in that the first conductivity type high resistivity Only the number of procedures for forming the first epi layer is increased. However, since this additional procedure can be performed as part of continuous epitaxy, there is no substantial increase in steps. Further, the step of forming a special region such as a p-type substrate contact portion or a dummy collector portion described in the related art is not required, and the process is simplified. Further, a special region such as a p-type substrate contact portion and a dummy collector portion is not required, and the isolation by a simple trench isolation region is sufficient.
The technical difficulties in photolithography have also been alleviated,
High integration density is facilitated. Therefore, according to the third feature of the present invention, it is possible to realize a semiconductor integrated circuit which can prevent the influence of the parasitic bipolar transistor even if the integration density is increased, without requiring a special technique or a manufacturing process. Since the process is easy, the production yield is high, the production period is shortened, and the production cost is reduced.

[0029]

As described above, according to the present invention, the parasitic n composed of the buried layer and the semiconductor substrate which are separated from each other is provided.
The current amplification factor h _fe of the pn bipolar transistor is low,
In addition, a semiconductor integrated circuit in which the area of the element isolation region does not increase can be provided.

According to the present invention, it is possible to provide a semiconductor integrated circuit having a high withstand voltage and excellent dynamic isolation between adjacent elements.

According to the present invention, there is provided a semiconductor integrated circuit having a high withstand voltage and a high integration density which does not affect a circuit element around an element in the output stage even when a surge voltage is applied to the element in the output stage. Can be provided.

According to the present invention, a semiconductor integrated circuit which is inexpensive and has high reliability such as surge resistance can be provided.

According to the present invention, a semiconductor integrated circuit capable of preventing operation interference between devices due to a parasitic bipolar transistor even when the devices are arranged at a high density and integrated without requiring a special technique or a manufacturing process. It is possible to provide a method of manufacturing a semiconductor integrated circuit which can be easily realized.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals. However,
The drawings are schematic, the relationship between thickness and plane dimensions,
It should be noted that the ratio of the thickness of each layer is different from the actual one. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view illustrating a power IC according to an embodiment. As shown in FIG. 1, the power IC according to the first embodiment of the present invention has a resistivity of 50 mΩ · cm to 500 m.
Ω · cm p ⁺ semiconductor substrate (hereinafter “p ⁺ substrate”
2), a resistivity of about 50 to 500 Ω · cm,
A thickness of 5 to 8 [mu] m p ^- there is a layer 14 to 17, on its, nMOS unit 322, pnp-type bipolar transistor 323, the trench gate type power MOSFET 3
25, 327 are formed. However, in some cases, the resistivity of the p ⁻ layers 14 to 17 may be about 500 Ω · cm or more.

Each of these devices is isolated by an element isolation region 110 made of a trench sidewall oxide film 10 and a trench buried polysilicon 11. The trench gate type power MOSFET units 325 and 327 are high-breakdown-voltage / high-current MOSFETs serving as output-stage semiconductor elements. nMO
S section 322, pnp type bipolar transistor section 323
Are these output stage trench gate type power MOS
It shows a part of small-signal circuit elements used for circuits for driving and controlling the FET units 325 and 327, protection circuits, sensors, and the like.

That is, the p ⁻ layers 14-1 on the p ⁺ substrate 2
7, n ⁺ buried layers (NBL) 24, 21, 22, 2
3 are formed, and the n ⁺ buried layers 24, 21, 22, 23
P-well region (PWL) required for each device configuration
41 and n-well regions (NWL) 31, 32 to 35 are formed. Trench gate type power MOSFET unit 3
25,327 p-type base regions 61,62,63,64
Among them, n ⁺ source regions 84, 85, 87, 88 and p ⁺ contact regions 75, 76, which serve as back gate regions,
78 and 79 are formed. Further, a trench gate oxide film 12 and a trench gate polysilicon 13 are formed on the inner walls of the trenches formed in p-type base regions 61, 62, 63, 64, and the p-type base region facing trench gate oxide film 12 is formed. Channels are formed on the surfaces of 61, 62, 63 and 64. Then, n ⁺ buried layers 22 and 23 serving as buried drain regions and n ⁺ drain contact region 8
6 and 91 are connected to each other by n-type sinkers (NSK) 51 and 52.

On the other hand, nMOS portion 322 has n ⁺ source region 81, n ⁺ drain region 82, and p ⁺ contact region 71 formed on the surface of p well region 41.
A gate electrode 9 is formed on the surface of p well region 41 between n ⁺ source region 81 and n ⁺ drain region 82 of nMOS portion 322 via a gate oxide film.

The pnp-type bipolar transistor section 323 is formed on the p ⁺
It has a collector region 72, a p ⁺ emitter region 73, and an n ⁺ base region 83.

Although not shown, an insulating film such as an interlayer insulating film is formed on the surface of each device region. The connection between the devices is made by n ⁺ source regions 81, 8
4, 85, 87, 88, n ⁺ drain regions 82, 86,
91, p ⁺ collector region 72, p ⁺ emitter region 73,
A contact hole is provided in the insulating film above the n ⁺ base region 83, and the contact hole is electrically connected through an aluminum wiring or the like. Power MOSFET 3
Drain electrodes made of a metal such as aluminum (Al) are provided in n ⁺ drain contact regions 86 and 91 formed on the upper portions of the 25 and 327 n-type sinkers 51 and 52, respectively. And the like, are connected to external electrode terminals of the semiconductor integrated circuit (power IC). Further, the external electrode terminal is connected to an external load of the semiconductor integrated circuit. For the sake of simplicity, these contact holes,
Metal electrodes, metal wiring (aluminum wiring), and the like are not shown in the drawings, and only some of the connections are shown.

Unlike the prior art shown in FIGS. 20 and 21, in the power IC according to the first embodiment of the present invention, the power IC is formed on n ⁺ buried layers 21 to 24 whose potential varies. The separation of each device is performed by the element isolation region 11.
It goes with only 0. The resistivity of the p ⁺ substrate 2 is 0.5 Ω · of the resistivity of the p-type substrate 1 shown in FIGS.
cm to 5 Ω · cm.

Next, the operation of the power IC according to the first embodiment of the present invention will be described. Between the adjacent bipolar transistor 323 and the power MOSFET 325, p
⁺ Substrate 2 based, the n ⁺ embedded layer 22 of the power MOSFET325 emitter, the parasitic npn bipolar transistor 221 to the collector of the n ⁺ buried layer 21 of the bipolar transistor 323 is formed. In addition, adjacent power MOSFETs 325 and 327
Between the base and p ⁺ substrate 2, power MOSFET
325 emitters n ⁺ buried layer 22, the power MOSFE
Parasitic npn using n ⁺ buried layer 23 of T327 as collector
A bipolar transistor 222 is formed. As described in the description of the related art, lowering the current amplification factor h _fe of the parasitic npn bipolar transistors 221 and 222 can be achieved by reducing the parasitic npn bipolar transistors 221 and 22.
It is important in preventing the effects of (2). In the first embodiment of the present invention, since the resistivity of the p ⁺ substrate 2 is set lower than that of the p-type substrate 1 used in the prior art, the parasitic np
The base resistances of the n bipolar transistors 221 and 222 decrease, and as a result, the current amplification factor h _fe decreases. For example, a resistivity of 50 mΩ · cm to 500 mΩ · c
By using a p ⁺ substrate of m
Current amplification factor h _fe is 0.0
It can be about 1. When the resistivity of the p-type substrate 1 decreases, the width of the depletion layer between the n ⁺ buried layer and the p-type substrate 1 decreases in the conventional technology, and the breakdown voltage decreases. In one embodiment, p ⁺ substrate 2 and n ⁺
Since the p ^- layers 14, 15, 16, and 17 are provided between the buried layers, the width of the depletion layer can be secured to a predetermined value, and the breakdown voltage required for the power IC can be secured. For example, p with a resistivity of about 50 to 500 Ω · cm and a thickness of 5 to 8 μm
^- Pressure 50V by providing a layer 14, 15, 16, 17
The degree can be secured. As a result, the element isolation region 1 composed of the trench sidewall oxide film 10 and the trench buried polysilicon is formed.
Interference in circuit operation can be suppressed without using a special part such as a dummy collector other than 10. Therefore, high-density arrangement of devices becomes possible, and power IC
Chip size can be reduced. In general, since the width of the element isolation region 110 can be formed to be about 2 μm, a significant reduction in size can be realized as compared with the element isolation region of 20 to 70 μm in the related art.

Next, a method of manufacturing the power IC according to the first embodiment of the present invention will be described with reference to the process sectional views of FIGS.

(A) As shown in FIG. 2A, p ⁺ having an impurity density of about 4 × 10 ¹⁶ cm ^{−3 to} 1.5 × 10 ¹⁸ cm ^−3.
On the substrate 2, boron (B) of about impurity density 1x10 ¹⁴ cm ^-3 to 5x10 ¹⁴ cm ^-3 as a dopant p ^- epitaxial layer thickness of 5 to 8μ (first epitaxial layer) 3
grow m. Further, an impurity density of 1 × 1 is formed on the p ⁻ epitaxial growth layer (first epi layer) 3 using arsenic (As) or antimony (Sb) as a dopant.
0 ¹⁷ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ , thickness 3 to 6μ
n ⁺ epitaxial growth layer m (second epitaxial layer) 4, and B the impurity concentration 1x10 ¹⁵ cm ^-3 to 5x10 ¹⁵ cm ^-3 approximately as a dopant, thickness 8 to 10 [mu] m p-type epitaxial growth layer (the third epitaxial layer) 5 is continuously vapor-phase epitaxially grown. This vapor phase epitaxial growth
Monosilane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), trichlorosilane (SiH ₃₎
Cl), silicon tetrachloride (SiCl ₄ ), etc.
Using hydrogen (H ₂ ) as carrier gas, substrate temperature 1
What is necessary is just to grow at 050 degreeC-1200 degreeC. Atmospheric pressure epitaxy or decompression epitaxy may be used,
It is preferable to grow continuously in the same chamber.
As the dopant gas, diborane (B ₂ H ₆ ), arsine (AsH ₃ ), stibine (SbH ₃ ), or the like may be used.

(B) Next, a predetermined mask such as a photoresist, an oxide film, and a metal film is formed by photolithography, and the acceleration energy is 150 to 200 KeV, and the dose is 1 × 10 ¹² cm ^{−2 to} 3 × 10 ¹² cm ^−2. Boron ( ¹¹ B ⁺ ) is selectively ion-implanted into the region where the p-well region is to be formed. Further, the mask used for the ¹¹ B ⁺ ion implantation is removed, a new mask is formed, and the acceleration energy is 150 to 200 KeV and the dose is 1 × 10 ¹² cm ^−2.
Phosphorus ( ³¹ P ⁺ ) is ion-implanted into a region where an n-well region is to be formed at approximately 3 × 10 ¹² cm ⁻² . Moreover, removing the mask used for the ³¹ P ⁺ ion implantation into the n-well region forming area, newly formed masks, acceleration energy 150 to 200 KeV, dose 5x10 ¹³ cm ^-2
31 P ⁺ is ion-implanted into the region where the n-type sinker is to be formed at about 1 × 10 ¹⁶ cm ⁻² . Thereafter, the mask used for the ion implantation of ³¹ P ⁺ into the region where the n-type sinker is to be formed is removed, and a predetermined annealing is performed. As shown in FIG. 2B, each device is placed in the p-type epitaxial growth layer 5. A p-well region 41, n-well regions 31, 32,
37, 38 and n-type sinkers 51, 52 are selectively formed. In order to form the n-type sinkers 51 and 52 having a large aspect ratio as shown in FIG.
High-energy multi-stage ion implantation of ¹¹ B ⁺ may be performed in steps of V, 3 MeV, 5 MeV, and 8 MeV, and then predetermined annealing may be performed. If there is concern about damage due to high energy ion implantation, the silicon wafer may be tilted at a predetermined angle and channeling ion implantation may be performed.

Thereafter, n well regions 32, 3
A mask having an opening (window) is formed on the surface of each of the layers 7 and 38, and an acceleration energy of 150 to 200 KeV, a dose of about 5 × 10 ¹² cm ^{−2 to 1} × 10 ¹³ cm ⁻² and ¹¹ B
⁺ Ions are implanted through this opening (window). Then, if the mask used for the ion implantation is removed and predetermined annealing is performed, as shown in FIG. 2B, the p base regions 61, 62, 6 are formed in the n well regions 32, 37, 38.
3, 64 are formed. In this annealing, of course, the substrate temperature and the annealing time are set so that the p base regions 61, 62, 63, and 64 have a predetermined diffusion depth. The depth of the p base regions 61, 62, 63, 64 is
Since it depends on the channel length of the trench gate type power MOSFET, for example, 1 μm or more is required.

(C) Next, a silicon nitride film (Si ₃ N ₄ film) 6 is formed on the entire surface by CVD, and photolithography and RIE (reactive ion etching) are performed.
Is used to perform patterning as shown in FIG.
Then the the Si ₃ N ₄ film 6 is patterned as a mask, a predetermined etching of trench grooves 171, for example CF _4, SF _6, RIE method using a SiCl ₄ or the like of the gas or the like as shown in FIG. 3 (d) Formed by Trench groove 1
The depth of 71 is set to reach the p ⁺ substrate 2, and 17 μm or more is required. For example, if HBr + NF ₃ + O ₂ + He is R
If used as an etching gas for IE, silicon and S
Since a selectivity with the i ₃ N ₄ film 6 of about 10 is obtained, the thickness of the Si ₃ N ₄ film 6 may be about 2 μm in order to etch silicon by 17 μm. If cracks or the like when the thick Si ₃ N ₄ film 6 is formed become a problem,
A multilayer film may be formed using a composite film such as an i ₃ N ₄ film and an oxide film. By this etching, the p ^- epi layer 3 becomes the p ^- layer 14,
The n ⁺ epi layer 4 is separated into n ⁺ buried layers 21, 22, 23, and 24. Further, the n-well 37 is separated into n-wells 33 and 34 and an n-well 38
Are part of the n-well 35.

(D) Next, as shown in FIG. 4E, the trench sidewall oxide film 1 is formed on the inner wall of the trench 171 by thermal oxidation.
Then, a high resistivity polysilicon 11 not doped with impurities is deposited on the surface of the trench side wall oxide film 10 by using the CVD method.
Is filled in the trench groove 171 to form the element isolation region 11.
0 is formed. The width of the element isolation region 110 is 2-3 μm.
It is about. Subsequently, as shown in FIG. 4F, a field oxide film 18 is formed on the trench groove 171 by using the Si ₃ N ₄ film 6 used for etching the trench groove 171 as a mask for selective oxidation.

(E) Next, the Si ₃ N ₄ film 6 used as a selective oxidation mask is removed, and the exposed p-well region 4 is removed.
1. On the surfaces of n-well regions 31, 32, 33, 34, 35 and n-type sinkers 51, 52, a gate oxide film 8 having a thickness of 50 to 150 nm is formed by thermal oxidation as shown in FIG. Form. Further, a thickness of 300
A polysilicon film 9 having a thickness of about 700 nm is formed by a CVD method. The polysilicon film is patterned by photolithography and RIE as shown in FIG. 5H to form a gate electrode 9. And this gate electrode 9
As a mask, ⁷⁵ As ⁺ is self-aligned with an acceleration energy of 80 to 100 KeV and a dose of 1 × 10 ¹⁵ cm.
^At about ⁻² to 1 × 10 ¹⁶ cm ⁻² , ions are implanted into a portion where the n ⁺ source region and the n ⁺ drain region of the nMOS are to be formed. This ⁷⁵ As ⁺ ion implantation is performed on the n-wells 31 and 3.
2, 33, 34, 35 and n-type sinkers 51, 52 are also selectively performed using a mask such as a photoresist. That is, a predetermined mask is formed by using a photolithography method, and an n ⁺ base contact region forming portion of a pnp type bipolar transistor portion, an n ⁺ source region and an n ⁺ drain contact region forming portion of a trench gate type power MOSFET portion are formed. Also, at the same time when the n ⁺ source region and the n ⁺ drain region of the nMOS are to be formed, ⁷⁵ As
⁺ Is ion-implanted.

Further, a mask such as another photoresist is formed by photolithography, and the acceleration energy is 35 to 50 KeV and the dose is 1 × 10 ¹⁵ cm ^{−2 to} 1
At about x10 ¹⁶ cm ^-2 , ¹¹ B ⁺ or ⁴⁹ BF ₂ ⁺ was converted to nM
OS p ⁺ contact region formation portion, pnp type bipolar transistor portion p ⁺ emitter region formation portion, p
⁺ Planned collector region formation, trench gate type power M
Ions are implanted into a portion of the OSFET where ap ⁺ contact region is to be formed.

Thereafter, the mask used for the ion implantation of ¹¹ B ⁺ or ⁴⁹ BF ₂ ⁺ is removed, and predetermined annealing is performed, so that the n ⁺ source region 81 is formed in the p well 41 as shown in FIG. , N ⁺ drain region 82, p ⁺ contact region 71, p ⁺ emitter region 73, p ⁺ collector region 72, n ⁺ base contact region 83 in n well 31, n ⁺ source region 84, p ⁺ contact in p base region 61 The region 75, the n ⁺ source region 87 and the p ⁺ contact region 76 in the p base region 62, the n ⁺ source region 85, the p ⁺ contact region 78 in the p base region 63, and the n
^{A +} source region 88, a p ⁺ contact region 79, an n ⁺ drain contact region 86 is formed in the n-type sinker 51, and an n ⁺ drain contact region 91 is formed in the n-type sinker 52.

(F) Next, the p-well 4 is formed using the CVD method.
1. After the Si ₃ N ₄ film 7 is deposited on the surface of the n-wells 31 to 35 and the like, the Si ₃ N ₄ film 7 is patterned by photolithography and RIE as shown in FIG. Then, using this Si ₃ N ₄ film 7 as a mask, n
The wells 32 to 35 are etched by RIE, and a trench 172 for forming a trench gate of the trench gate type power MOSFET portion is dug. The depth of the trench 172 is required to be deep enough to penetrate the depth of the p base regions 61, 62, 63, 64 of the trench gate type power MOSFET, and is, for example, 1 μm or more. For example, if HBr + NF ₃ + O ₂ + He is used as an etching gas, the selectivity between silicon and the Si ₃ N ₄ film 7 can be about 10, so the thickness of the Si ₃ N ₄ film 6 is required to etch silicon by 1 μm. Should be about 100 nm.

(G) Next, a sacrificial oxide film is formed on the inner wall of the trench 172, and the sacrificial oxide film is removed to remove damage and contamination by the RIE method. Then, a trench gate oxide film 12 having a thickness of 25 to 100 nm is formed on the inner wall of the trench 172 by a thermal oxidation method as shown in FIG. Further, an impurity-doped polysilicon (doped polysilicon) 13 is formed on the trench gate oxide film 12 on the side wall of the trench.
Deposit by VD method. By filling the trench trench 172 with the doped polysilicon to be the trench gate portion polysilicon 13 in this manner, the gate electrode 13 of the trench gate type power MOSFET is formed as shown in FIG. Subsequently, as shown in FIG. 7K, an oxide film 99 is formed on the trench 172 using the Si ₃ N ₄ film 7 used for etching the trench 172 as a mask for selective oxidation. Thereafter, as shown in FIG. 7 (l), the Si ₃ N ₄ film 7 used as a selective oxidation mask is removed.

(H) Then, the entire surface is made of SiO
_{A second} interlayer insulating film 100 is deposited. By forming a contact hole in the interlayer insulating film, the source electrode 19 is formed so as to short-circuit the n ⁺ source region 81 and the p ⁺ contact region 71. Further, a contact hole is opened in the interlayer insulating film, and as shown in FIG. 8, the drain electrode 20 for the n ⁺ drain region 82, the collector electrode 24 for the p ⁺ collector region 72, and p ⁺ the emitter electrode 25 with respect to the emitter region 73, n ⁺ base
The base electrode 26 is formed on the contact region 83. Also, the n ⁺ source region 84 and the p ⁺ contact region 7
5. The source electrode 27 is connected to the n ⁺ source region 85 so that the n ⁺ source region 87 and the p ⁺ contact region 76 are short-circuited.
And p ⁺ contact region 78, n ⁺ source region 88 and p ⁺
The source electrode 47 is short-circuited with the contact region 79.
To form Further, the n ⁺ drain contact region 86,
For 91, drain electrodes 28 and 48 are formed, respectively. Then, as shown in FIG. 8, a back surface electrode 29 of Al or gold (Au) is formed on the back surface of the p ⁺ substrate 2. Then, a surface passivation film such as a PSG film, a BPSG film, or a silicon nitride film (Si ₃ N ₄ film) is formed (the surface passivation film is not shown).

(I) Then, the p ⁺ substrate 2 having undergone these procedures is mounted on a predetermined package, and a predetermined assembling step such as bonding is performed.
Is completed. When the p ⁺ substrate 2 is mounted on a package, the back electrode 29 is of course connected to a metal plate at the ground potential by solder or conductive paste. In some cases, the back electrode 29 is omitted and p
^{+ The} substrate 2 may be in contact with a ground potential metal plate via solder.

First Modification The power IC according to the first embodiment of the present invention is not limited to all elements (devices) constituting the power IC.
It is not necessary that the region have an n ⁺ buried layer (NBL).
FIG. 9 is a schematic cross-sectional view showing a modified example (first modified example) of such a power IC according to the first embodiment of the present invention.

As shown in FIG. 9, the power IC according to the first modification of the first embodiment of the present invention has a resistivity of 50 m.
A p ⁺ substrate having a resistivity of about 50 to 500 Ω · cm and a thickness of 5 to 8 μm is formed on a p ⁺ substrate 2 of Ω · cm to 500 mΩ · cm.
^- There is a layer 14 to 17, on its, in part, n ⁺ buried layer 21, 22, 23 are formed. That is, the n ⁺ buried layers 21, 22, 23 are formed only in the element (device) regions where the pnp bipolar transistor section 323 and the trench gate power MOSFET sections 325, 327 are formed.
Is formed, but no n ⁺ buried layer is formed in the element (device) region forming the nMOS portion 322. On the p ⁻ layer 17, a p-well region (PWL) 41 necessary for the configuration of the nMOS portion 322 is formed directly. On the other hand, p ^- on the layer 14, 15 and 16, n ⁺ buried layer 21, 22 and 23 are formed, the n ⁺ buried layer 21,
22 and 23, a pnp bipolar transistor section 323 and a trench gate type power MOSFET section 32
N-well region (NWL) 3 necessary for the configuration of 5,327
1, 32 to 35 are formed. nMOS section 322,
The fact that the pnp bipolar transistor section 323 and the trench gate type power MOSFET sections 325 and 327 are separated by the element isolation region 110 composed of the trench side wall oxide film 10 and the trench buried polysilicon 11 is shown in FIG.
Is the same as The basic structures of the nMOS section 322, the pnp bipolar transistor section 323, and the trench gate power MOSFET sections 325 and 327 are the same as those in FIG.

As shown in FIG. 9, also in the power IC according to the first modification of the first embodiment of the present invention, the adjacent bipolar transistor 323 and power MOSFET are connected.
Between T325 and p ⁺ substrate 2, power MO
Emitters n ⁺ buried layer 22 of SFET325, parasitic npn bipolar transistor 221 to the collector of the n ⁺ buried layer 21 of the bipolar transistor 323 is formed. A parasitic npn bipolar between the adjacent power MOSFET 325 and the power MOSFET 327 has the p ⁺ substrate 2 as a base, the n ⁺ buried layer 22 of the power MOSFET 325 as an emitter, and the n ⁺ buried layer 23 of the power MOSFET 327 as a collector. Transistor 222
Are formed. In the first modification of the first embodiment of the present invention, since the resistivity of the p ⁺ substrate 2 is set lower than that of the p-type substrate 1 used in the conventional technique, the parasitic npn
The base resistance of the bipolar transistors 221 and 222 decreases, and as a result, the current amplification factor h _fe decreases.
Further, since there are p ⁻ layers 14, 15, 16 between p ⁺ substrate 2 and n ⁺ buried layers 21, 22, 23, the width of the depletion layer can be secured to a predetermined value, and the withstand voltage required for the power IC is ensured. Can be secured. As a result, without using a special part such as a dummy collector, the element isolation region 1 composed of the trench sidewall oxide film 10 and the trench buried polysilicon is used.
With only 10, the interference of the circuit operation can be suppressed.

As described above, the n ⁺ buried layer (NB
L), the current amplification factor h _fe of the parasitic npn bipolar transistor caused by the partial n ⁺ buried layer is suppressed to a certain value or less while securing a predetermined withstand voltage. You can do it. Therefore, it is possible to arrange devices at high density while securing a predetermined withstand voltage, and to reduce the chip size of the power IC.

In the method of manufacturing the power IC according to the first modification of the first embodiment of the present invention, it is necessary to selectively form an n ⁺ buried layer. Slightly more complicated than the process. However, except for this point, it is basically the same.

That is, as shown in FIG. 2 (a), p ⁺ having an impurity density of about 4 × 10 ¹⁶ cm ^{−3 to} 1.5 × 10 ¹⁸ cm ^−3.
On the substrate 2, p-type impurity of approximately impurity density 1x10 ¹⁴ cm ^-3 to 5x10 ¹⁴ cm ^-3 as a dopant p such B
^An epitaxial growth layer (first epi layer) 3 is grown to a thickness of 7 to 12 μm, and the p ⁺ substrate 2 is once taken out of the growth chamber. Then, Fotorejito by photolithography, oxide film, to form a predetermined mask metal film such as an n-type impurity ions ⁷⁵ As ⁺ or the like through this mask, an acceleration energy 80 to 100 KeV, dose 3x10 ¹⁵ The mask is removed by ion implantation at about cm ^{−2 to 2} × 10 ¹⁶ cm ⁻³ . Then, the p ⁺ substrate 2 is heated to a temperature of 1
By annealing at about 100 ° C. to 1200 ° C., n ⁺ buried layers 21, 22 and 23 are selectively formed in p ⁻ epitaxial growth layer (first epi layer) 3. After that, the p ⁺ substrate 2 is again inserted into the growth chamber, and the impurity density is 1 × 10 ¹⁵ cm ^{−3 to} 5 using p-type impurities such as B as a dopant.
A p-type epitaxial growth layer (third epi layer) 5 having a thickness of about 10 ¹⁵ cm ^-3 and a thickness of 8 to 10 μm may be grown. Subsequent steps are basically the same as the steps shown in FIG.

[0062] Alternatively, on the p ⁺ substrate 2 as shown in FIG. 2 (a), p ^- epitaxial layer (first epitaxial layer) 3
Is grown to a thickness of 5 to 8 μm, and subsequently, an impurity density of 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 5 is formed on the p ⁻ epitaxial growth layer 3 by using an n-type impurity such as As or Sb as a dopant.
^{It is} also possible to adopt a method in which an n ⁺ epitaxial growth layer (second epi layer) 4 having a thickness of about ²⁰ cm ⁻³ and a thickness of about 3 to 6 μm is grown, and the p ⁺ substrate 2 is once taken out of the growth chamber.
In this case, subsequently, n ⁺ a predetermined mask such as an oxide film on the epitaxial growth layer 4 is formed by using this mask, the n ⁺ epitaxial layer 4 by RIE or the like p
^- it is selectively removed until the epitaxial growth layer 3 is exposed, n ⁺ buried layer 21, 22, 23 are formed. Thereafter, the p ⁺ substrate 2 is inserted again into the growth chamber,
Impurity concentration of 1 × 10
^{About 15} cm ^{-3 to} 5 × 10 ¹⁵ cm ^-3 , thickness 8 to 13μ
What is necessary is just to grow the m-type p-type epitaxial growth layer (third epilayer) 5. In this case, if necessary, the surface of the p-type epitaxial growth layer (third epi layer) 5 may be planarized by using a CMP method (chemical mechanical polishing method) or the like. Thereafter, the steps shown in FIG. 2B and thereafter may be performed.

Second Modification Example The semiconductor element at the output stage mounted on the power IC according to the first embodiment of the present invention is not necessarily U-type as shown in FIG.
Gate type power MOSFET having a U-shaped groove
It need not be T. The semiconductor element (power semiconductor element) in the output stage is a DMOS (double diffusion M) having no trench.
A power MOSFET such as an OSFET (Double-diffused MOSFET) or a VMOS (V-grooved MOSFET) having a gate in a V-shaped groove may be used. Further, a planar (horizontal) power MOSFET may be used. Further, a power semiconductor element other than the power MOSFET may be used. FIG. 10 shows a modification (second modification) of the power IC according to the first embodiment of the present invention.
It is a typical sectional view showing the case where an IGBT is used for a semiconductor element of an output stage.

As shown in FIG. 10, the power IC according to the second modification of the first embodiment of the present invention has a resistivity of 50%.
On a p ⁺ substrate 2 of mΩ · cm to 500 mΩ · cm, p ⁻ layers 14 to 17 having a resistivity of about 50 to 500 Ω · cm and a thickness of 5 to 8 μm are arranged, and an nMOS portion 32
2, pnp bipolar transistor section 323, IGB
T portions 329 and 330 are formed. Each of these devices is isolated by an element isolation region 110 composed of a trench sidewall oxide film 10 and a trench buried polysilicon 11.

That is, the p ⁻ layers 14-1 on the p ⁺ substrate 2
7, n ⁺ buried layers (NBL) 24, 21, 22, 2
3 are formed, and the n ⁺ buried layers 24, 21, 22, 23
P-well region (PWL) required for each device configuration
41 and n-well regions (NWL) 31, 39, 40 are formed. IGBT portions 329 and 330 are formed in n-well regions 39 and 40. That is, p-type base regions 61, 62, 63, 64 are provided in n-well regions 39, 40.
Are provided, and the p-type base regions 61, 62, 63, 6
4 includes n ⁺ emitter regions 55, 56, 57, 58 and p ⁺ contact regions 75, 7 serving as back gate regions.
6, 78, 79 are formed. Further, a trench gate oxide film 12 and a trench gate polysilicon 13 are formed on the inner walls of the trenches formed in p-type base regions 61, 62, 63, 64, and the p-type base region facing trench gate oxide film 12 is formed. Channels are formed on the surfaces of 61, 62, 63 and 64. Then, a trench gate portion 12/1 near the center of each of n well regions 39 and 40 is provided.
3 are provided with p ⁺ collector regions 59 and 60, respectively. Although not shown, the IGBT unit 32
An insulating film such as an interlayer insulating film is formed on the surface of 9,330. Then, the n ⁺ emitter region 55 and the p ⁺ contact region 75, the n ⁺ emitter region 56 and the p ⁺ contact region 76, the n ⁺ emitter region 57 and the p ⁺ contact region 78, n ⁺ emitter region 58 and p ⁺ contact region 79
And an emitter electrode are provided so as to short-circuit each. In addition, a collector electrode is provided via a contact hole in an insulating film above p ⁺ collector regions 59 and 60.

The nMOS section 322 and the pnp type bipolar transistor section 323 are the same as those shown in FIG.

Between the adjacent bipolar transistor 323 and the IGBT 329, the p ⁺ substrate 2 is
Emitters n ⁺ buried layer 22 of BT329, parasitic npn bipolar transistor 221 to the collector of the n ⁺ buried layer 21 of the bipolar transistor 323 is formed. Further, between the adjacent IGBTs 329 and 330, the p ⁺ substrate 2 is used as a base, and the n ⁺
The buried layer 22 is an emitter, and the n ⁺ buried layer 2 of the IGBT 330 is
A parasitic npn bipolar transistor 222 having a collector 3 is formed. Power MOSF shown in FIG.
IGBT p ⁺ collector regions 59 and 60 compared to ET
Is not a structure directly connected to the n ⁺ buried layers 22 and 23. However, the voltage fluctuation rate dV is applied to the collector electrode of the IGBT.
If a large surge voltage of / dt is applied, the potentials of the n ⁺ buried layers 22 and 23 fluctuate capacitively (spikes).
Parasitic npn bipolar transistors 221 and 222 affect peripheral circuit elements as in FIG.

Therefore, the second embodiment of the first embodiment of the present invention
In the modification of (1), the resistivity of the p ⁺
The base resistances of the pn bipolar transistors 221 and 222 are lowered, and the current amplification factor h _fe is set to a small value. In the second modification of the first embodiment of the present invention, the p ⁻ layers 14, 15, 1 between the p ⁺ substrate 2 and the n ⁺ buried layer are provided.
6 and 17, the width of the depletion layer can be secured to a predetermined value.
Withstand voltage required for the power IC can be secured. As a result, it is possible to suppress interference in circuit operation due to disturbance from a capacitively-coupled (spike-like) external circuit with a simple configuration including only the element isolation region 110 composed of the trench sidewall oxide film 10 and the trench buried polysilicon. Can be.
Therefore, high-density integrated arrangement of devices such as IGBTs on the power IC becomes possible, and the chip size of the power IC can be reduced.

Third Modification FIG. 11 shows a power IC according to the first embodiment of the present invention.
FIG. 13 is a schematic cross-sectional view showing a case where a junction type static induction transistor (SIT) is used for a semiconductor element in an output stage as a modification (third modification) of (a). This junction type SIT is a notched gate type SIT, and a high frequency power SIT.
It is.

As shown in FIG. 9, the power IC according to the third modification of the first embodiment of the present invention has a resistivity of 50%.
On a p ⁺ substrate 2 of mΩ · cm to 500 mΩ · cm, p ⁻ layers 14 to 17 having a resistivity of about 50 to 500 Ω · cm and a thickness of 5 to 8 μm are arranged, and an nMOS portion 32
2. A pnp bipolar transistor section 323 and cut-gate SIT sections 331 and 327 are formed. Each of these devices is isolated by an element isolation region 110 composed of a trench sidewall oxide film 10 and a trench buried polysilicon 11.

That is, the p ⁻ layers 14-1 on the p ⁺ substrate 2
7, n ⁺ buried layers (NBL) 24, 21, 22, 2
3 are formed, and the n ⁺ buried layers 24, 21, 22, 23
P-well region (PWL) required for each device configuration
41 and n-well regions (NWL) 31, 46, 47, 4
8, 49 are formed. The n ⁺ buried layers 22 and 23
It functions as a buried drain region of the SIT portions 331 and 327. The n ⁺ buried drain regions 22 and 23 and the n ⁺ drain regions 89 and 90 near the surface are connected to an n-type sinker (N
SK) 51 and 52. Drain electrodes are connected to the surfaces of the n ⁺ drain regions 89 and 90 (in the cross-sectional view of FIG. 11, the drain electrodes are not shown and only the connections are shown). And SIT
Parts 331 and 327 are formed in n-well regions 46, 47, 48 and 49 above buried drain regions 22 and 23. And n-well regions 46, 47, 48, 49
N ⁺ source regions 65 and 66 are provided near the surface of
Source electrodes are connected to the surfaces of the n ⁺ source regions 65 and 66 (in the cross-sectional view of FIG. 11, the source electrodes are not shown and only the connection is shown). U grooves (trench) are formed so as to sandwich these n ⁺ source regions 65 and 66, and p ⁺ gate regions 92 and 9 are formed on the side walls of each trench.
3 are provided. An insulating film 9 is provided at the bottom of each trench.
7, 98 are buried, and ap ⁺ gate region 9 is
Gate electrode 95, so as to make ohmic contact with
96 are arranged. Insulating film 9 at the bottom of each trench
7, 98 are films for reducing the gate-drain capacitance and improving the high frequency characteristics.

[0072] The impurity concentration of the n-well region 46, 47, 48, 49, only the built-in potential between the p ⁺ gate regions 92 and 93 · n-well region 46, 47, 48, 49, p ⁺ gate region 92 opposed And p ⁺ gate region 9
A channel region formed therebetween and 2, and if the channel region formed therebetween in the p ⁺ gate region 93 and the p ⁺ gate region 93 opposing it is devised to depletion (pinch-off), normally・ Off-type SIT. The impurity density of n well regions 46, 47, 48, and 49 is slightly increased, and p ⁺ gate regions 92, 93 and n well region 4
6, 47, 48, and 49, only the p ⁺ gate regions 92 and the p ⁺ gate regions 9
If you do not deplete between the three, normally
It becomes an ON type SIT. In the normally-on type SIT, when a negative voltage is applied to the gate electrode 95 so that the pn junction is reverse-biased, the channel between the n ⁺ source regions 65 and 66 and the buried drain regions 22 and 23 is depleted. Pinch off. In the normally-off type SIT, the gate electrode 95
If a positive voltage is applied so that the pn junction becomes forward biased, the n ⁺ source regions 65 and 66 and the buried drain region 2
A conduction state is established between 2 and 23.

The nMOS section 322 and the pnp type bipolar transistor section 323 are the same as those shown in FIG.

Between the adjacent bipolar transistor 323 and the notched gate SIT 331, the p ⁺ substrate 2 is used as a base, the n ⁺ buried layer 22 of the notched gate SIT 331 is an emitter, and the n ^{+ of the} bipolar transistor 323 is n ^+. A parasitic npn bipolar transistor 221 having the buried layer 21 as a collector is formed. Further, the adjacent cut gate type SIT unit 331 and the cut gate type SIT
Between the IT portion 327, the p ⁺ substrate 2 is used as a base, the n ⁺ buried layer 22 of the cut gate type SIT portion 331 is used as an emitter, and the n ⁺ buried layer 23 of the cut gate type SIT portion 327 is provided.
Npn bipolar transistor 2 having a collector
22 are formed. In the third modification of the first embodiment of the present invention, since the resistivity of p ⁺ substrate 2 is set low, parasitic npn bipolar transistors 221 and 22 are formed.
2, the base amplification resistance _hfe is reduced. Also, the third embodiment of the first embodiment of the present invention
P In the variation between the p ⁺ substrate 2 and the n ⁺ buried layer ^- layer 1
4, 15, 16, and 17, the width of the depletion layer can be secured at a predetermined value, and the withstand voltage required for the power IC can be secured. As a result, an element isolation region 11 composed of trench sidewall oxide film 10 and trench buried polysilicon is formed.
The interference of the circuit operation can be suppressed with a simple configuration of only 0. Therefore, devices such as SIT can be arranged at a high density, and the chip size of the power IC can be reduced.

In FIG. 11, nMOS section 322, pn
Instead of the p-type bipolar transistor section 323, the notch gate type SIT sections 331 and 327 in the output stage are driven.
A small signal SIT for controlling may be provided, and a cut-gate SIT unit 331, 3 may be provided by another small signal circuit.
27 may be driven and controlled. Further, the n ⁺ drain region 8 of the cut gate type SIT portions 331 and 327
The p ⁺ anode region instead of 9,90, by providing the n ⁺ cathode region in place of the n ⁺ source regions 65 and 66,
Although a notch gate type electrostatic induction thyristor (SI thyristor) is used, it is needless to say that the technical idea of the present invention can be applied also in this case. More preferably, p ⁺
A double gate SI thyristor in which the second gate is arranged near the anode region may be used. Double gate type SI
If a thyristor is used as a power semiconductor element at the output stage, a power IC with higher efficiency, higher breakdown voltage, and higher reliability can be provided. As described above, the power IC according to the first embodiment of the present invention can be variously modified.

(Second Embodiment) FIG. 12 shows a second embodiment of the present invention.
Schematic sectional view showing a power IC according to a second embodiment.
It is. As shown in FIG. 12, the first embodiment of the present invention
The power IC according to the state is in a floating state (floating state).
P-type with a resistivity of 0.5Ω · cm to 5Ω · cm Semiconduct
N on a body substrate (hereinafter referred to as “p-type substrate”) 1
MOS section 422, pnp type bipolar transistor section 4
23, trench gate type power MOSFET unit 425,
427 are formed. The resistivity of this semiconductor substrate 1 is
P higher than 5Ω · cm^-Substrate may be used, 0.5Ω · c
p lower than m⁺It can be a substrate. Each of these devices
422, 423, 425, 427 are trench sidewall oxidation
Between the elements composed of the film 10 and the trench-embedded polysilicon 11
It is separated by a separation region 110. Trench gate type
The power MOSFET sections 425 and 427 are semiconductors at the output stage.
It is a MOSFET with a high breakdown voltage and a large current as an element. nM
OS section 422, pnp type bipolar transistor section 42
3 is a trench gate type power MO at the output stage.
Circuit and protection for driving and controlling the SFET units 425 and 427
Some of the circuit elements used in circuits, sensors, etc. are shown.
It is.

That is, the n ⁺ buried layer (NBL) 24,
21, 22 and 23 are formed, and the n ⁺ buried layers 24 and 2 are formed.
A p-well region (PWL) 41 and n-well regions (NWL) 31, 3 required for each device configuration are formed on 1, 22, 23.
2 to 35 are formed. Trench gate type power M
OSFET portions 425, 427 p-type base regions 61, 6
2, 63, 64, n ⁺ source regions 84, 85, 8
7, 88 and p ⁺ contact regions 75, 76, 78, 79 serving as back gate regions are formed. further,
A trench gate oxide film 12 and a trench gate polysilicon 13 are formed on the inner walls of the trenches formed in the p-type base regions 61, 62, 63, 64. 62, 63, 64
A channel is formed on the surface of the substrate. The n ⁺ buried layers 22 and 23 serving as buried drain regions and the n ⁺ drain contact regions 86 and 91 are formed by an n-type sinker (NSK).
They are connected to each other by 51 and 52.

On the other hand, nMOS portion 422 has n ⁺ source region 81, n ⁺ drain region 82, and p ⁺ contact region 71 formed on the surface of p well region 41.
A gate electrode 9 is formed on the surface of p well region 41 between n ⁺ source region 81 and n ⁺ drain region 82 of nMOS portion 422 via a gate oxide film.

Then, pnp type bipolar transistor portion 423 is formed by p ⁺ formed on the surface of n well region 31.
It has a collector region 72, a p ⁺ emitter region 73, and an n ⁺ base region 83.

Although not shown, an insulating film such as an interlayer insulating film is formed on the surface of each device region. The connection between the devices is made by n ⁺ source regions 81, 8
4, 85, 87, 88, n ⁺ drain regions 82, 86,
91, p ⁺ collector region 72, p ⁺ emitter region 73,
A contact hole is provided in the insulating film above the n ⁺ base region 83, and the contact hole is electrically connected through an aluminum wiring or the like. Power MOSFET 4
Drain electrodes made of a metal such as Al are provided in the n ⁺ drain contact regions 86 and 91 formed on the upper portions of the 25 and 427 n-type sinkers 51 and 52. And connected to external electrode terminals of the semiconductor integrated circuit (power IC). Further, the external electrode terminal is connected to an external load of the semiconductor integrated circuit. For simplicity, in the cross-sectional view of FIG. 12, these contact holes, metal electrodes, metal wiring (aluminum wiring), and the like are not shown, and only some of the connections are shown.

The power I according to the second embodiment of the present invention
Although the illustration of the package C is omitted, the back surface of the p-type substrate 1 is fixed to an insulating plate (package pedestal) or a floating potential metal plate (lead frame) with an insulating adhesive or the like. Have been. Note that p
PSG film, BPSG film, or Si
₃ N ₄ backside passivation film may be disposed such film.

Unlike the prior art shown in FIGS. 20 and 21, the power IC according to the second embodiment of the present invention is formed on n ⁺ buried layers 21 to 24 whose potential varies. The separation of each device is performed by the element isolation region 11.
It goes with only 0. In the power IC according to the second embodiment of the present invention, an important point in the configuration is that the potential of the p-type substrate 1 is not fixed but is in a floating state. Also, typically, the p-well region 41 of the nMOS 422, p ⁺ contact region 71 in the p-well region 41
Is connected to the GND potential to operate. Therefore, FIG.
Because in the two to separate the p-type substrate 1 and the p-well region 41, the point forming the n ⁺ buried layer 24 during this time is different from the prior art power IC of FIG. 20.

Next, a trench gate type power MOSFE
The operation will be described by taking as an example a case where a negative surge is applied from the n ⁺ drain contact region 86 of T425 and the n ⁺ buried layer 22 has a negative potential. As shown in FIG. 12, in the power IC according to the second embodiment of the present invention, the base between the adjacent bipolar transistor 423 and power MOSFET 425 is based on the p-type substrate 1,
Parasitic npn bipolar transistor 23 having n ⁺ buried layer 22 of power MOSFET 425 as an emitter and n ⁺ buried layer 21 of bipolar transistor 423 as a collector
1 is formed. In addition, the adjacent power MOSFE
A parasitic npn bipolar transistor 232 having the p-type substrate 1 as a base, the n ⁺ buried layer 22 of the power MOSFET 425 as an emitter, and the n ⁺ buried layer 23 of the power MOSFET 427 as a collector is formed between T425 and the power MOSFET 427. ing. In the second embodiment of the present invention, the parasitic bipolar transistor 23
The potential of the n ⁺ buried layer 22, which is the emitter of
Even when the potential becomes lower than the D potential, the path through which the base current of the parasitic bipolar transistor 231 flows is not formed because the p-type substrate 1 is in a floating state.
Therefore, the base current of parasitic bipolar transistor 231 does not flow, and parasitic bipolar transistors 231 and 231 do not flow.
Neither is turned on, and there is no possibility of interference between devices. That is, even if a negative surge is applied to the transistor in the output stage, all the parasitic bipolar transistors based on the p-type substrate 1 are not turned on, and the influence of the parasitic bipolar transistor on the whole semiconductor integrated circuit is reduced. Can be prevented.

Further, without using a special part such as a dummy collector other than the element isolation region 110 made of the trench sidewall oxide film 10 and the trench buried polysilicon,
Separation between devices is possible. In other words, element isolation can be performed only by the element isolation region 110 having a small required area, and no interference occurs in circuit operation even when devices are arranged at high density. Therefore, according to the power IC according to the second embodiment of the present invention, the chip size can be significantly reduced.

The power I according to the second embodiment of the present invention
Since the width of the element isolation region 110 of C can be formed at about 2 μm, the chip size can be reduced to about 20% or less as compared with the related art. As described above, it should be noted that the element isolation region in the related art was 20 to 70 μm. It will be appreciated that significant miniaturization can be achieved.

Next, a method of manufacturing a power IC according to a second embodiment of the present invention will be described with reference to the process sectional views of FIGS.

[0087] (i) As shown in FIG. 13 (a), on a p-type substrate 1 of about impurity concentration 3x10 ¹⁵ cm ^-3 to 4x10 ¹⁶ cm ^-3, the impurity density 1x10, As or Sb as a dopant ¹⁷ cm ^{- 3} to 5x10 ²⁰ cm ^-3 of about n
⁺ Deposit an epitaxial growth layer (first epi layer) 4,
Further, on the n ⁺ epitaxial growth layer (first epi layer) 4, an impurity density of 1 × 10 ¹⁵ cm ^{−3 with} B as a dopant is used.
To 5x10 ¹⁵ cm ^-3 approximately, p-type epitaxial layer having a thickness of 8 to 10 [mu] m (second epitaxial layer) 5 is continuously grown and formed. This epitaxial growth uses SiH ₄ , SiH ₂ Cl ₂ , SiH ₃ Cl, SiCl ₄ or the like as a source gas, H ₂ as a carrier gas, and a substrate temperature of 1 ° C.
The growth may be performed at 050 ° C. to 1200 ° C., but is preferably performed continuously in the same growth chamber.

(B) Next, a predetermined mask is formed by photolithography, and the acceleration energy is 150 to 200 KeV and the dose is 1 × 10 ¹² cm ^{−2 to} 3 × 10
^At about ¹² cm ⁻² , ¹¹ B ⁺ is ion-implanted into a region where a p-well region is to be formed. Further, the mask used for the ¹¹ B ⁺ ion implantation is removed, another mask is formed, and the acceleration energy 1
50 to 200 KeV, the ³¹ P ⁺ at a dose of 1x10 ¹² cm ^-2 to 3x10 ¹² cm approximately ^-2 n-well region formation region, ion implantation. Further, the mask used for the ion implantation of ³¹ P ⁺ into the region where the n-well region is to be formed is removed, and another mask is formed.
To 200 KeV, dose amount 5 × 10 ¹³ cm ^{−2 to} 1 ×
³¹ P ⁺ is ion-implanted into a region where an n-type sinker is to be formed at approximately 10 ¹⁶ cm ⁻² . After that, the mask used for the ion implantation of ³¹ P ⁺ into the region where the n-type sinker is to be formed is removed, and a predetermined annealing is performed. As shown in FIG. P-well region 41 and n-well regions 31, 32, 3 necessary for formation
7, 38 and n-type sinkers 51 and 52 are selectively formed.

Thereafter, n well regions 32, 3
A mask having a window portion is formed on the surface of each of the masks 7 and 38, the acceleration energy is 150 to 200 KeV, and the dose is 5 × 10 5.
¹¹ B ⁺ is ion-implanted through this window at about ¹² cm ^{−2 to 1} × 10 ¹³ cm ⁻² . Then, if the mask used for the ion implantation is removed and predetermined annealing is performed, FIG.
As shown in FIG. 3B, the n-well regions 32, 37, 38
P base regions 61, 62, 63 and 64 are formed therein.

(C) Next, a Si ₃ N ₄ film 6 is formed on the entire surface by using the CVD method,
Using the E method, patterning is performed as shown in FIG. Then, using the patterned Si ₃ N ₄ film 6 as a mask, as shown in FIG.
Is formed by predetermined etching such as RIE.
Since the depth of the trench 171 is necessary until the depth reaches the p-type substrate 1, silicon must be etched to 11 μm or more. For example, if HBr + NF ₃ + O ₂ + He is R
As the etching gas used for the IE, silicon and Si
_Since the selectivity with the ₃ N ₄ film 6 is about 10, the thickness of the Si ₃ N ₄ film 6 may be about 1.1 μm in order to etch silicon at 11 μm. By this etching, the n ⁺ epi layer 4 becomes the n ⁺ buried layers 21, 22, 23, and 24.
Is separated into Further, n-well 37 is composed of n-wells 33 and 3
4 and a part of the n-well 38 becomes the n-well 35.

(D) Next, as shown in FIG. 15E, a trench sidewall oxide film 10 is formed on the inner wall of the trench 171 by thermal oxidation, and then the surface of the trench sidewall oxide film 10 is formed by CVD using a CVD method. The element isolation region 110 is formed by depositing polysilicon 11 not doped with impurities and filling the trench 11 with the high resistivity polysilicon 11. The width of the element isolation region 110 is about 2 to 3 μm. Subsequently, as shown in FIG.
Using the Si ₃ N ₄ film 6 used for etching 71 as a mask for selective oxidation, a field oxide film 18 is formed on the trench groove 171.

(E) Next, the Si ₃ N ₄ film 6 used as a mask for selective oxidation is removed, and the exposed p-well region 4 is removed.
1. On the surfaces of the n-well regions 31, 32, 33, 34, and 35 and the n-type sinkers 51 and 52, as shown in FIG. Form. Further, a thickness of 300
A polysilicon film 9 having a thickness of about 700 nm is formed by a CVD method. The polysilicon film is patterned by using the photolithography method and the RIE method as shown in FIG. And this gate electrode 9
As a mask, ⁷⁵ As ⁺ is self-aligned with an acceleration energy of 80 to 100 KeV and a dose of 1 × 10 ¹⁵ cm.
^At about ⁻² to 1 × 10 ¹⁶ cm ⁻² , ions are implanted into a portion where the n ⁺ source region and the n ⁺ drain region of the nMOS are to be formed. This ⁷⁵ As ⁺ ion implantation is performed on the n-wells 31 and 3.
2, 33, 34, 35 and n-type sinkers 51, 52 are also selectively performed using a mask such as a photoresist. That is, a predetermined mask is formed by using a photolithography method, and an n ⁺ base contact region forming portion of a pnp type bipolar transistor portion, an n ⁺ source region and an n ⁺ drain contact region forming portion of a trench gate type power MOSFET portion are formed. Also, ⁷⁵ As ⁺ is ion-implanted.

Further, a mask of another photoresist is formed by using a photolithography method, and an acceleration energy of 3
5 to 50 KeV, dose amount 1 × 10 ¹⁵ cm ^{−2 to} 1 ×
At about 10 ¹⁶ cm ^-2 , ¹¹ B ⁺ or ⁴⁹ BF ₂ ⁺ is added to nMO
S ⁺ p ⁺ contact region formation portion, pnp type bipolar transistor portion p ⁺ emitter region formation portion, p ⁺
Planned collector region formation, trench gate type power MO
Ions are implanted into a portion of the SFET where ap ⁺ contact region is to be formed.

Thereafter, the mask used for the ion implantation of ¹¹ B ⁺ or ⁴⁹ BF ₂ ⁺ is removed, and predetermined annealing is performed. As a result, the n ⁺ source region 81 is formed in the p well 41 as shown in FIG. , N ⁺ drain region 82, p ⁺ contact region 71, p ⁺ emitter region 73, p ⁺ collector region 72, n ⁺ base contact region 83 in n well 31, n ⁺ source region 84, p ⁺ contact in p base region 61 In the region 75 and the p base region 62, the n ⁺ source region 87 and the p ⁺
Contact region 76, p base region 63 to the n ⁺ source region 85, p ⁺ contact region 78, p base region 64 to the n ⁺ source region 88, p ⁺ contact region 79, n ⁺ drain n-type sinker 51 contact region 86, An n ⁺ drain contact region 91 is formed in n type sinker 52.

(F) Next, the p-well 4 is formed using the CVD method.
1. After depositing the Si ₃ N ₄ film 7 on the surfaces of the n-wells 31 to 35 and the like, the Si ₃ N ₄ film 7 is patterned by photolithography and RIE as shown in FIG. Then, the n-wells 32 to 35 are etched by RIE using the Si ₃ N ₄ film 7 as a mask,
The trench 172 is dug. The depth of the trench 172 depends on the channel length of the trench gate type power MOSFET, and needs to be 1 μm or more. For example, HBr + NF ₃ + O ₂
If + He is used as an etching gas, silicon and S
Since a selectivity of about 10 with respect to the i ₃ N ₄ film 7 can be obtained, in order to etch silicon by 1 μm, the Si ₃ N ₄ film 6
Should be about 100 nm.

(G) Next, a trench gate oxide film 12 having a thickness of 25 to 100 nm is formed on the inner wall of the trench 172 by a thermal oxidation method as shown in FIG. Further, on the trench gate oxide film 12 on the side wall of the trench, doped polysilicon to be the trench gate polysilicon 13 is deposited by a CVD method. Thus, by filling the doped trench 13 with the doped polysilicon 13,
As shown in FIG. 17 (j), a trench gate type power MO
The gate electrode 13 of the SFET is formed. Continuing on, FIG.
8 (k), an oxide film 99 is formed on the trench 172 using the Si ₃ N ₄ film 7 used for etching the trench 172 as a mask for selective oxidation.
Thereafter, as shown in FIG. 18 (l), the Si ₃ N ₄ film 7 used as a selective oxidation mask is removed.

(H) Then, the whole surface is formed by SiO
_{A second} interlayer insulating film 100 is deposited. By opening a contact hole in this interlayer insulating film, n ⁺ source region 81 and p ⁺ contact region 71 are short-circuited to form source electrode 19. Further, as shown in FIG. 19, a contact hole is opened in the interlayer insulating film, the drain electrode 20 is provided for the n ⁺ drain region 82, the collector electrode 24 is provided for the p ⁺ collector region 72, and p ⁺ An emitter electrode 25 is formed for the emitter region 73, and a base electrode 26 is formed for the n ⁺ base contact region 83. or,
The source electrode 27 is short-circuited between the n ⁺ source region 84 and the p ⁺ contact region 75, the n ⁺ source region 87 and the p ⁺ contact region 76, the n ⁺ source region 85 and the p ⁺ contact region 78, and the n ⁺ source region. Source electrode 47 is formed to short-circuit 88 and p ⁺ contact region 79. Further, drain electrodes 28 and 48 are formed for n ⁺ drain contact regions 86 and 91, respectively.
Then, a surface passivation film such as a PSG film, a BPSG film, or a Si ₃ N ₄ film is formed (the surface passivation film is not shown). Further, a back surface passivation film such as a PSG film, a BPSG film, or a Si ₃ N ₄ film may be formed on the back surface of the p-type substrate 1.

(I) Then, the p-type substrate 1 having undergone these procedures is mounted in a predetermined package, and a predetermined assembling step such as bonding is performed, whereby the power IC of the present invention is completed. When mounting a p-type substrate on a package,
Of course, the back surface of the mold substrate is fixed on an insulating plate or a metal plate having a floating potential with an insulating adhesive or the like.

(Other Embodiments) As described above, the present invention has been described with reference to the first and second embodiments.
The discussion and drawings that form part of this disclosure should not be understood as limiting the invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

Although some modifications are shown in the first embodiment of the present invention, these modifications are the same in the second embodiment of the present invention. That is, the semiconductor element at the output stage mounted on the power IC according to the second embodiment of the present invention is not necessarily a trench gate type power MO.
Not limited to SFET, D without VMOS or trench
A MOS or a planar MOSFET may be used. Furthermore, a power semiconductor element such as an IGBT, SIT, or SI thyristor may be used. Also, SIT may be provided in part or all as a circuit element for driving and controlling the power semiconductor element in the output stage.

The power IC according to the first embodiment
In the structure of p, the p ^- epitaxial growth layer 3 is formed on the p ⁺ substrate 1.
Although the (p ⁻ layers 14 to 17) are formed, the same operation is performed when an i layer (intrinsic semiconductor layer) or an n ⁻ epitaxial growth layer is formed instead of the p ⁻ epitaxial growth layer 3.

Further, it is needless to say that the effects of the present invention can be achieved even if the device structure and the manufacturing method thereof described above are all replaced with semiconductors of the opposite conductivity type. Further, the descriptions of the first and second embodiments are exemplifications, and it is easy to include a portion in which only the conductivity type of a predetermined portion of these descriptions is replaced with a semiconductor of the opposite conductivity type to the above description. You can understand. For example, when a pMOS is formed instead of an nMOS, all the conductivity types of the nMOS portion including the well of the nMOS may be replaced with semiconductors of the opposite conductivity type.

As described above, it should be understood that the present invention includes various embodiments not described herein. Therefore, the present invention is limited only by the matters specifying the invention described in the claims that are reasonable from this disclosure.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a power IC according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view for explaining the method for manufacturing the power IC according to the first embodiment of the present invention (part 1).

FIG. 3 is a process sectional view for describing the method for manufacturing the power IC according to the first embodiment of the present invention (part 2).

FIG. 4 is a process sectional view for explaining the method for manufacturing the power IC according to the first embodiment of the present invention (part 3).

FIG. 5 is a process sectional view for explaining the method for manufacturing the power IC according to the first embodiment of the present invention (part 4).

FIG. 6 is a process sectional view for explaining the method for manufacturing the power IC according to the first embodiment of the present invention (part 5).

FIG. 7 is a process sectional view for explaining the method for manufacturing the power IC according to the first embodiment of the present invention (part 6).

FIG. 8 is a process sectional view for describing the method for manufacturing the power IC according to the first embodiment of the present invention (part 7).

FIG. 9 is a schematic sectional view of a power IC according to a first modification of the first embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view of a power IC according to a second modification of the first embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of a power IC according to a third modification of the first embodiment of the present invention.

FIG. 12 is a power IC according to a second embodiment of the present invention.
FIG. 3 is a schematic sectional view of FIG.

FIG. 13 is a power IC according to a second embodiment of the present invention.
It is a process sectional view for explaining the manufacturing method (No. 1).

FIG. 14 is a power IC according to a second embodiment of the present invention.
It is a process sectional view for explaining the manufacturing method of (2).

FIG. 15 is a power IC according to a second embodiment of the present invention.
It is a process sectional view for explaining the manufacturing method of (3).

FIG. 16 is a power IC according to a second embodiment of the present invention.
It is a process sectional view for explaining the manufacturing method (part 4).

FIG. 17 is a power IC according to a second embodiment of the present invention.
It is a process sectional view for explaining the manufacturing method (part 5).

FIG. 18 is a power IC according to a second embodiment of the present invention.
FIG. 11 is a process sectional view for describing the manufacturing method (part 6).

FIG. 19 is a power IC according to a second embodiment of the present invention.
FIG. 14 is a process sectional view for describing the method of manufacturing (No. 7).

FIG. 20 is a cross-sectional view of a conventional power IC.

FIG. 21 is a sectional view of another conventional power IC.

[Explanation of symbols]

Reference Signs List 1 p substrate 2 p ⁺ substrate 3 p ^- epi layer (first epi layer) 4 n ⁺ epi layer (second epi layer) 5 p epi layer (third epi layer) 6, 7 silicon nitride film (Si ₃ N ₄₎ 8, 12 Gate oxide film 9 Gate electrode 10 Trench side wall oxide film 11 Trench buried polysilicon 13 Trench gate portion polysilicon 14-17 p ^- layer 18 Field oxide film 19, 27, 47 Source electrode 20, 28, 48 Drain electrode 21 to 24 n ⁺ buried layer 24 collector electrode 25 emitter electrode 26 base electrode 29 back electrode 30 to 40 n well 41 to 45 p well 51, 52 n-type sinker 55 to 58 n ⁺ emitter region 59, 60, 72 p ⁺ collector region 61~64 p base region 65,66,81,84,85,87,88 n ⁺ source region 69~71,74~79 p ⁺ Conta DOO region 73 p ⁺ emitter region 82,89,90 n ⁺ drain region 83 n ⁺ base contact region 86 and 91 n ⁺ drain contact region 92 and 93 p ⁺ gate region 94 n ⁺ contact regions 97, 98 and 99 an insulating film 100 Interlayer insulating film 171 First trench groove 172 Second trench groove

Claims (7)

[Claims] 1. A semiconductor substrate having a first conductivity type and a low resistivity, and first and second semiconductor layers having a higher resistivity than the semiconductor substrate disposed on the semiconductor substrate and separated from each other by a trench isolation region. A first semiconductor layer disposed on the first semiconductor layer;
A first buried layer of a second conductivity type having a lower resistivity than that of the first semiconductor layer, and the first semiconductor layer are arranged separately from each other in the trench isolation region; And a second buried layer of a second conductivity type having a lower resistivity than the first and second semiconductor layers; and a first well disposed above the first buried layer. The first well is disposed separately from each other in the trench isolation region, and a second well disposed above the second buried layer; and at least one at a surface of the first well. A semiconductor integrated circuit having at least a first semiconductor element having a main electrode region and a second semiconductor element having at least one main electrode region on a surface of the second well. 2. A semiconductor substrate of a first conductivity type in a floating state, first and second buried layers of a second conductivity type disposed on the semiconductor substrate so as to be separated from each other by a trench isolation region; A first well disposed above the first buried layer; and the first well disposed separately from each other in the trench isolation region, and disposed above the second buried layer. A second well, a first semiconductor device having at least one main electrode region on a surface of the first well, and a second semiconductor device having at least one main electrode region on a surface of the second well And a semiconductor integrated circuit having at least: 3. The semiconductor integrated circuit according to claim 1, wherein the first and second semiconductor layers have a resistivity of 50 Ω · cm or more. 4. A parasitic bipolar transistor having the first buried layer as an emitter, the semiconductor substrate as a base, and the second buried layer as a collector has a current amplification factor h _fe of 0.01.
4. The semiconductor integrated circuit according to claim 1, wherein the number is twice or less. 5. The semiconductor device according to claim 1, wherein the first buried layer is electrically coupled to an external electrode terminal via a second conductivity type low resistivity sinker. Item 2. The semiconductor integrated circuit according to item 1. 6. The semiconductor device according to claim 1, wherein the first semiconductor element is a semiconductor element at an output stage, and the first buried layer is electrically coupled to an external load. The semiconductor integrated circuit according to claim 1. 7. A method for manufacturing a semiconductor integrated circuit, comprising at least the following steps. (A) On a semiconductor substrate of the first conductivity type and low resistivity,
Continuously epitaxially growing a first epi layer of the first conductivity type, a second epi layer of the second conductivity type, and a third epi layer of the first conductivity type having a higher resistivity than the semiconductor substrate. Only a predetermined portion of the third epi layer is selectively covered with the second
Step of forming a well of conductivity type (c) Forming a trench penetrating the third epi layer, the second epi layer, and the first epi layer, filling the trench with an insulator, and forming a trench isolation region Process