CN102479718B - Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET) - Google Patents

Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET) Download PDF

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CN102479718B
CN102479718B CN201010567043.XA CN201010567043A CN102479718B CN 102479718 B CN102479718 B CN 102479718B CN 201010567043 A CN201010567043 A CN 201010567043A CN 102479718 B CN102479718 B CN 102479718B
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described
conducting channel
region
silicon
implantation
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CN201010567043.XA
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CN102479718A (en
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刘金华
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中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Abstract

The invention provides a manufacturing method of a metal-oxide-semiconductor field effect transistor (MOSFET), comprising the following steps: manufacturing a hard mask on the surface of a silicon substrate on a source region and a drain region before a conductive channel is formed, and carrying out ion implantation at twice from different angles by using the hard mask as a shield in the process for forming the conductive channel through ion implantation to form a nonuniform conductive channel, thus, the doping concentration of the part of the conductive channel near the edge of the drain region is reduced on the premise that the whole doping concentration of the nonuniform conductive channel is not remarkably changed, on the one hand, the short channel effect of the MOSFET is prevented from increasing, and on the other hand, the band-gap tunneling effect and drain leakage current are reduced, shutdown current is reduced, and the service life of the MOSFET device is prolonged.

Description

A kind of manufacture method of mos field effect transistor

Technical field

The present invention relates to a kind of semiconductor making method, particularly a kind of manufacture method of mos field effect transistor.

Background technology

At present, mos field effect transistor (MOSFET) device architecture comprises: as shown in Figure 1, be positioned at the gate oxide 102 on substrate 101 surfaces, the grid 103 of gate oxide 102 tops, the conducting channel 104 that the substrate surface of gate oxide below forms, lay respectively at source electrode 106 and drain electrode 107 in grid 103 both sides substrates, and nitrogen oxide (silica and the silicon nitride) side wall 105 (Spacer) that is looped around gate lateral wall.Nitrogen oxide side wall 105 can be protected grid 103 on the one hand, and source, the drain electrode that can prevent from the other hand forming source electrode 106 and drain electrode 107 injected and too approached with conducting channel 104 and produce leakage current, even conducting between source electrode 106 and drain electrode 107.Some is overlapping for conducting channel 104 and drain electrode 107, after grid 103 making alives, PN junction in drain electrode 107 and 101 formation of substrate, conducting channel 104 near drain electrode 107 marginal portions can cause leakage current (Gate Induced Drain Leakage, GIDL) due to the effect generation grid of electric field.GIDL is an important component part of leakage current, can cause MOSFET power consumption to rise, and affect MOSFET device lifetime.Research shows, higher near the doping content of the conducting channel 104 of drain electrode 107 marginal portions, the depletion width of PN junction is less, and (Band-to-Band tunneling) is also larger for interband tunnelling, and GIDL also can increase thereupon.In prior art, if formed in the process of conducting channel at Implantation, reduce equably the whole doping content of conducting channel 104, although can reduce GIDL,, because the whole doping content of conducting channel 104 reduces, can increase significantly the short-channel effect of conducting channel, as everyone knows, to MOSFET device, need to reduce short-channel effect as far as possible.Therefore, under the prerequisite that as far as possible reduces short-channel effect, suppress the leakage current that GIDL produces, thereby improve the MOSFET life-span, reduce close current (Off Current) and become problem demanding prompt solution in the manufacture of MOSFET device.

Summary of the invention

In view of this, the technical problem that the present invention solves is: conducting channel is higher near the doping content of the marginal portion of drain electrode, it is larger that interband tunnelling and grid cause leakage current, therefore can shorten MOSFET device lifetime, increase close current, if but reduce the doping content of whole piece conducting channel, can significantly increase the short-channel effect of MOSFET device.

For addressing the above problem, technical scheme of the present invention is specifically achieved in that

A manufacture method for mos field effect transistor, provides the wafer with N-shaped or p-type doped silicon substrate, and source region and drain region are set in described silicon substrate, and the method comprises:

Described surface of silicon metallization medium layer;

Dielectric layer described in patterning, exposes the surface of silicon between source region and drain region, as gate window;

Using the dielectric layer of patterning as hard mask, to twice Implantation of described gate window, the zone line of the described gate window of the first doping and near source region, the close drain region of the described gate window of not adulterating when wherein primary ions is injected; When another secondary ion injects, the second doping is described near drain region and all or part of described zone line and close source region, described near formation first area, drain region conducting channel, the overlapping region of described twice Implantation forms the 3rd region conducting channel, forms the doping content of first area conducting channel lower than the non-uniform doping conducting channel of the doping content of the 3rd region conducting channel in gate window;

On described gate window surface, deposit successively after gate oxide and polysilicon layer, polysilicon layer described in cmp, until expose described dielectric layer to form grid;

Remove the dielectric layer of patterning;

At described gate lateral wall, form side wall, take grid and side wall as mask, adopt Implantation mode in silicon substrate, to form source electrode and drain electrode.

Described dielectric layer is silicon dioxide layer or silicon nitride layer, or the combination of silicon dioxide layer and silicon nitride layer.

The thickness range of described first medium layer is that 100 nanometers are to 2000 nanometers.

Described the second etching adopts dry etching or wet etching.

The ion beam that described primary ions is injected departs to source region, the number of degrees scope of described ion beam and described surface of silicon normal angle is 7~45 degree, implantation dosage scope is 1E11~1E14 every square centimeter, and Implantation Energy scope is 2~100 kilo electron volts.

The proportion that described first area conducting channel area accounts for the described non-homogeneous conducting channel gross area is to be greater than 0 to be less than or equal to 1/3; The scope that described the 3rd region conducting channel area accounts for the ratio of the described non-homogeneous conducting channel gross area is to be more than or equal to 1/3 to be less than 1.

In described non-uniform doping conducting channel, the percentage range that the doping content of first area conducting channel is compared the doping content of the 3rd region conducting channel is 60~80%.

As seen from the above technical solutions, the manufacture method of a kind of mos field effect transistor provided by the invention, the dielectric layer of patterning of take is hard mask, by twice Implantation, form non-uniform doping conducting channel, under the prerequisite of whole doping content that does not significantly reduce non-homogeneous conducting channel, reduced the doping content of conducting channel near the marginal portion of drain electrode, avoid increasing on the one hand the short-channel effect of MOSFET, reduce on the other hand interband tunneling effect and grid and cause leakage current, reduce close current, improve MOSFET device lifetime.

Accompanying drawing explanation

Fig. 1 is the cross-sectional view of prior art MOSFET;

Fig. 2 is the flow chart of MOSFET manufacture method of the present invention;

Fig. 3 a~3h is the cross-sectional view of MOSFET manufacture method of the present invention.

Embodiment

For making object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.

Specific embodiment one

A manufacture method of N-type MOSFET, below in conjunction with accompanying drawing 3a~3h, describes the concrete steps of manufacturing N-type MOSFET in detail.

Step 201, Fig. 3 a are step 201 cross-sectional view of N-type MOSFET manufacture method of the present invention, as shown in Figure 3 a, the wafer having at the silicon substrate 301 of p-type doping is provided, source region and drain region are set, at silicon substrate 301 surfaces successively deposition of silica layer 302 and silicon nitride layer 303 in silicon substrate 301;

The present embodiment is that to take the manufacture method of N-type MOSFET be example, therefore adopts the silicon substrate 301 of p-type doping; If the manufacture method of P type MOSFET, the silicon substrate that adopts N-shaped to adulterate.

In this step, using silicon dioxide layer 302 and silicon nitride layer 303 composition stepped constructions as first medium layer, wherein, silicon dioxide layer 302 is as the resilient coating of subsequent deposition silicon nitride layer 303, because compare with the lattice constant match degree of silicon substrate 301 and silicon nitride layer 303, silicon dioxide layer 302 more mates with the lattice constant of silicon nitride layer 303, and the growth quality of silicon nitride layer 303 is better; As the thickness range of the silicon dioxide layer 302 of resilient coating be 10 nanometers to 100 nanometers, for example 10 nanometers, 50 nanometers and 100 nanometers; The surperficial Direct precipitation silicon dioxide layer of silicon substrate 301 that can also adulterate in p-type in addition, or silicon nitride layer are as first medium layer; In the present embodiment, the total thickness of described silicon dioxide layer and silicon nitride layer be 100 nanometers to 2000 nanometers, for example 100 nanometers, 1000 nanometers and 2000 nanometers.

Step 202, Fig. 3 b are step 202 cross-sectional view of N-type MOSFET manufacture method of the present invention, as shown in Figure 3 b, the first etching silicon dioxide layer 302 and silicon nitride layer 303 after the first photoetching, expose the surface of silicon between source electrode and drain region, as gate window 304, on silicon substrate 301 surfaces of source electrode and drain region, form the hard mask 302 ' of silicon dioxide layer and the hard mask 303 ' of silicon nitride layer;

In this step, after the first photoetching, the effect of the first etching silicon dioxide layer 302 and silicon nitride layer 303 is patterning first medium layers; Wherein, the first photoetching refers in described silicon nitride surface and applies after photoresist, defines the first photoengraving pattern of gate window through overexposure and developing process on photoresist; The first etching be take the first photoengraving pattern as mask, remove successively silicon nitride layer and silicon dioxide layer not covered by photoresist, expose silicon substrate 301 surfaces between source region and drain region as gate window 304, the hard mask 302 ' of the silicon dioxide layer on drain region and source region silicon substrate 301 surfaces and the hard mask 303 ' of silicon nitride layer are referred to as hard mask.The first etching is dry etching or wet etching, and while adopting dry etching, the etching terminal of the first etching is determined by end point determination method; While adopting wet etching, according to the silicon dioxide layer 302 of deposition and the thickness of silicon nitride layer 303, accurately control the etch period of the first etching.

In this step, gate window 304 has defined the position of non-homogeneous conducting channel, gate oxide and grid, in subsequent step, first the surface of silicon of N-shaped doping grid window 304 correspondences, form non-homogeneous conducting channel, then manufacturing gate oxide layers and grid successively above non-homogeneous conducting channel.

Step 203, Fig. 3 c are step 203 cross-sectional view of N-type MOSFET manufacture method of the present invention, as shown in Figure 3 c, with hard mask for covering, the first Implantation 305 in gate window, the close drain region of doping grid window not, the first Implantation 305 first doping are near the gate window part beyond drain region, in the gate window 304 of silicon substrate, form zone line and close source region that the first conducting channel 306, the first conducting channels 306 have covered gate window 304;

In this step, the number of degrees of ion beam and surface of silicon normal angle are defined as to implant angle, the first Implantation 305 ion beam used departs from (in figure, show as and depart from counterclockwise surface of silicon normal) to source region, the implant angle scope of the first Implantation 305 is that 7 degree are to 45 degree, for example, 7 degree, 20 degree and 45 degree; Implantation dosage scope is 1E11 every square centimeter to 1E14 every square centimeter; Implantation Energy scope is that 2 kilo electron volts (Kev) are to 100Kev.

In this step, the scope that the unadulterated area near drain region of the first Implantation 305 occupies whole gate window area is to be greater than 0 to be less than or equal to 1/3, for example, and 1/10,1/5 and 1/3.

Step 204, Fig. 3 d are step 204 cross-sectional view of N-type MOSFET manufacture method of the present invention, as shown in Figure 3 d, with hard mask for covering the second Implantation 307, the not doped portion gate window forming in the second doping step 203, also the second doped portion or whole the first conducting channel 306 form non-uniform doping conducting channel in the gate window 304 of silicon substrate;

In the present embodiment, the second Implantation 307 ion beam used departs from (in figure, show as and depart from clockwise surface of silicon normal) to drain region, the implant angle scope of the second Implantation 307 be 7 degree to 45 degree, for example, 7 degree, 20 degree and 45 are spent; Implantation dosage scope is 1E11 every square centimeter to 1E14 every square centimeter; Implantation Energy scope is that 2 kilo electron volts (Kev) are to 50Kev.The first conducting channel 306 partial stacks that form in the second Implantation 307 and step 203, finally in the gate window of silicon substrate, form and be divided into trizonal non-uniform doping conducting channel, respectively: during the first Implantation 305, do not adulterate and when the second Implantation 307 the second doping form first area conducting channel 308, during the second Implantation 307, do not adulterate and the first doping forms when the first Implantation second area conducting channel 309, with the 3rd region conducting channel 310 forming in the overlapping region of the first Implantation 305 and the second Implantation 307.In step 203 and 204, the implant angle size of twice Implantation is identical, implantation dosage and Implantation Energy equate, different is, the direction of twice Implantation is different, so controlling twice Implantation is in order to form symmetrical identical first area conducting channel 308 and the second area conducting channel 309 of relative the 3rd region conducting channel 310, thereby can make non-homogeneous conducting channel in the situation that do not distinguish in advance the particular location of source region and drain region, then in subsequent step, according to MOSFET device, need to below the first conducting channel region 308 or below the second conducting channel region, make drain electrode.After step 203 and step 204, the percentage range that the doping content of first area conducting channel 308 is compared the doping content of the 3rd region conducting channel 310 is 60%~80%, for example 60%, 70% and 80%; The percentage range that the doping content of second area conducting channel 309 is compared the doping content that is the 3rd region is 60%~80%, for example 60%, 70% and 80%.From step 203, the proportion that conducting channel 308 areas in first area account for the non-homogeneous conducting channel gross area is greater than zero and is less than or equal to 1/3rd.

If pre-determined the position of drain region, also can be when the second Implantation, make not off-normal of ion beam, or adopt the implant angle that is different from the first Implantation, implantation dosage and Implantation Energy, make zone line and the close source region of the part or all of cover gate window of the second Implantation, only need to guarantee near the doping content of the first area conducting channel of drain region and the percentage of doping content in 60%~80% scope, and the 3rd the region conducting channel area proportion that accounts for the non-homogeneous conducting channel gross area be more than or equal to 1/3 and be less than 1.

Visible, non-uniform doping conducting channel is significantly less than the doping content of the 3rd region conducting channel 310 in the doping content of first area conducting channel 308 and second area conducting channel 309, although the doping content of the conducting channel of the doping content of first area conducting channel 308 and second area conducting channel 309 in compared to existing technology reduces, but, due to first area conducting channel 308 and second area conducting channel 309, in whole conducting channel, area occupied and doping content can be by the implant angles of the first Implantation 305 and the second Implantation 307, implantation dosage and Implantation Energy are controlled, with this, improve ratio and the doping content of the 3rd region conducting channel 310 area occupied, therefore can significantly not reduce the average doping content of whole non-uniform doping conducting channel, avoid the increase of MOSFET device short-channel effect.

It should be noted that the present invention is not limited to the order of step 203 and 204, also can adopt the non-homogeneous conducting channel of sequentially built of step 204 and 203.The Implantation material of making the conducting channel employing of N-type MOSFET is phosphorus (P) or arsenic (As); The Implantation material of making the conducting channel employing of P type MOSFET is boron (B), boron difluoride (BF2) or indium (In).

Step 205, Fig. 3 e are step 205 cross-sectional view of N-type MOSFET manufacture method of the present invention, as shown in Figure 3 d, on non-uniform doping conducting channel, form after gate oxide, at wafer device side deposit spathic silicon, cmp (CMP) polysilicon forms grid 311;

In this step, gate oxide is the oxide of silicon, the dielectric layer of the nitrogen oxide of silicon or other high-ks (not shown in FIG.), and the step that forms gate oxide is prior art, and this repeats no more.

In this step, the thickness requirement of deposit spathic silicon is greater than the gross thickness of the hard mask 302 ' of silicon dioxide layer and the hard mask 303 ' of silicon nitride layer; The terminal that the hard mask 303 ' of the silicon nitride layer of take is CMP, the polysilicon of removing completely on the hard mask 303 ' of silicon nitride layer forms grid; The step that deposit spathic silicon and CMP polysilicon form grid is prior art, and this repeats no more.

Step 206, Fig. 3 f are step 206 cross-sectional view of N-type MOSFET manufacture method of the present invention, and as shown in Fig. 3 f, after the second photoetching, the second etching is removed hard mask;

In this step, the second photoetching refers to, in described wafer device side, applies after photoresist, forms the second photoengraving pattern of cover gate 311 through overexposure and developing process on photoresist; The second etching be take the second photoengraving pattern as mask, removes successively the hard mask 303 ' of silicon nitride layer not covered by photoresist and the hard mask 302 ' of silicon dioxide layer.The second etching can be that dry etching can be also wet etching; Dry etching is with remove successively the hard mask 303 ' of silicon nitride layer and the hard mask 302 ' of silicon dioxide layer containing the plasma gas of fluorine element, as carbon tetrafluoride; Wet etching is removed the hard mask 303 ' of silicon nitride layer by phosphoric acid solution etching, with hydrofluoric acid solution, removes the hard mask 302 ' of silicon dioxide layer.The terminal of the second etching is controlled as prior art, to dry etching, can adopt end point determination method, to wet etching, can calculate the second etch period according to thickness and the wet-etch rate of the hard mask 302 ' of silicon dioxide layer and the hard mask 303 ' of silicon nitride layer, accurately control etching terminal.

Step 207, Fig. 3 g are step 207 cross-sectional view of N-type MOSFET manufacture method of the present invention, as shown in Fig. 3 g, at grid 311 sidewalls, make side wall 312;

In this step, side wall 312 is or the nitrogen oxide of silicon, and the step that forms side wall 312 is prior art, and this repeats no more, and in the manufacturing process of MOSFET, also can omit this step.

Step 208, Fig. 3 h are step 208 cross-sectional view of N-type MOSFET manufacture method of the present invention, and as shown in Fig. 3 h, take grid 311 and side wall 312 is mask, make respectively source electrode 314 and drain electrode 313 in silicon substrate.

In this step, source electrode 314 and drain electrode 313 are N-shaped doping, and the step of making source electrode 314 and drain electrode 313 is prior art, and this repeats no more.

So far, the N-type MOSFET that the present invention proposes makes complete.

The manufacture method of a kind of mos field effect transistor provided by the invention, before forming conducting channel, source electrode and drain region in surface of silicon make hard mask, at Implantation, form in the process of conducting channel, utilize hard mask as covering, carry out at twice Implantation, primary ions is injected the not part of the close drain region of doping grid window, the zone line of the first doping grid window and close source region, another secondary ion injects the second doping near drain region and zone line and part or all of near source region, the overlapping region of twice Implantation forms the 3rd region conducting channel, in the underlapped region of twice Implantation, near formation first area, drain region conducting channel, near source region, forming second area conducting channel.The common doping content of close drain region that forms of first, second, and third region conducting channel is lower than the non-uniform doping conducting channel of other part doping contents.Method provided by the invention, reduced on the one hand the first area conducting channel doping content of close drain electrode, interband tunneling effect is reduced, GIDL also reduces thereupon, improve the MOSFET life-span, because kept the relatively high doping content of the 3rd region conducting channel, suppressed short-channel effect increase on the other hand.

The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.

Claims (7)

1. a manufacture method for mos field effect transistor, provides the wafer with N-shaped or p-type doped silicon substrate, and source region and drain region are set in described silicon substrate, it is characterized in that, the method comprises:
Described surface of silicon metallization medium layer;
Dielectric layer described in patterning, exposes the surface of silicon between source region and drain region, as gate window;
Using the dielectric layer of patterning as hard mask, to twice Implantation of described gate window, the zone line of the described gate window of the first doping and near source region, the close drain region of the described gate window of not adulterating when wherein primary ions is injected; When another secondary ion injects, the second doping is described near drain region and all or part of described zone line and close source region, described near formation first area, drain region conducting channel, the overlapping region of described twice Implantation forms the 3rd region conducting channel, forms the doping content of first area conducting channel lower than the non-uniform doping conducting channel of the doping content of the 3rd region conducting channel in gate window;
On described gate window surface, deposit successively after gate oxide and polysilicon layer, polysilicon layer described in cmp, until expose described dielectric layer to form grid;
Remove the dielectric layer of patterning;
At described gate lateral wall, form side wall, take grid and side wall as mask, adopt Implantation mode in silicon substrate, to form source electrode and drain electrode.
2. method according to claim 1, is characterized in that, described dielectric layer is silicon dioxide layer or silicon nitride layer, or the combination of silicon dioxide layer and silicon nitride layer.
3. method according to claim 1, is characterized in that, the thickness range of described dielectric layer is that 100 nanometers are to 2000 nanometers.
4. method according to claim 1, is characterized in that, adopts dry etching or wet etching to remove the dielectric layer of patterning.
5. method according to claim 1, it is characterized in that, the ion beam that described primary ions is injected departs to described source region, the number of degrees scope of described ion beam and described surface of silicon normal angle is 7~45 degree, implantation dosage scope is 1E11~1E14 every square centimeter, and Implantation Energy scope is 2~100 kilo electron volts.
6. method according to claim 1, is characterized in that, the proportion that described first area conducting channel area accounts for the described non-uniform doping conducting channel gross area is to be greater than 0 to be less than or equal to 1/3; The scope that described the 3rd region conducting channel area accounts for the ratio of the described non-uniform doping conducting channel gross area is to be more than or equal to 1/3 to be less than 1.
7. method according to claim 1, is characterized in that, the percentage range that the doping content of described first area conducting channel is compared the doping content of the 3rd region conducting channel is 60~80%.
CN201010567043.XA 2010-11-29 2010-11-29 Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET) CN102479718B (en)

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CN105895525A (en) * 2014-10-21 2016-08-24 南京励盛半导体科技有限公司 Technological method for preparing back doped regions of semiconductor device
CN106601748A (en) * 2015-10-14 2017-04-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof

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