CN106935502A - Semiconductor structure and its manufacture method - Google Patents
Semiconductor structure and its manufacture method Download PDFInfo
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- CN106935502A CN106935502A CN201511017177.3A CN201511017177A CN106935502A CN 106935502 A CN106935502 A CN 106935502A CN 201511017177 A CN201511017177 A CN 201511017177A CN 106935502 A CN106935502 A CN 106935502A
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- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 161
- 238000000034 method Methods 0.000 title claims abstract description 85
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 128
- 239000010410 layer Substances 0.000 claims description 238
- 150000002500 ions Chemical class 0.000 claims description 82
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 22
- 238000002347 injection Methods 0.000 claims description 22
- 239000007924 injection Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 238000005516 engineering process Methods 0.000 claims description 16
- 239000000243 solution Substances 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 13
- 238000010276 construction Methods 0.000 claims description 12
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000002356 single layer Substances 0.000 claims description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 4
- -1 boron difluoride ion Chemical class 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 18
- 230000009467 reduction Effects 0.000 description 9
- 230000005669 field effect Effects 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A kind of semiconductor structure and its manufacture method, methods described include：There is provided includes the Semiconductor substrate of the first area and second area being disposed adjacent；Patterned mask layer is formed on substrate, the mask layer has positioned at the first inclined-plane of first area；Threshold voltage ion doping technique is adjusted to substrate, the corresponding mask layer in the inclined-plane of ion permeable first forms channel region in substrate.The present invention forms the mask layer with thickness gradient by first area, the channel region formed after ion implanting also has thickness gradient, channel thickness near source region is thicker than channel thickness near drain region, influence due to the channel thickness near source region to carrier mobility is larger, and influence of the channel thickness to carrier mobility near drain region is smaller, so as to reduce the channel thickness near drain region while reducing and carrier mobility is influenceed, and then DIBL effects are restrained effectively, improve the electric property of semiconductor structure.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of semiconductor structure and its manufacture method.
Background technology
In semiconductor fabrication, with the development trend of super large-scale integration, integrated circuit feature chi
Very little lasting reduction.For the reduction of meeting market's demand size, the channel length of MOSFET FETs also phase
Should constantly shorten.However, with the shortening of device channel length, the distance between device source electrode and drain electrode
Shorten therewith, therefore grid is deteriorated therewith to the control ability of raceway groove, grid voltage pinch off (pinch off)
The difficulty of raceway groove is also increasing so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e. institute
Short-channel effect (the SCE of meaning：Short-channel effects) it is easier generation.
The potential barrier that drain terminal is introduced reduces (Drain Induction Barrier Lower, abbreviation DIBL) effect
A kind of common short-channel effect, i.e., when channel length reduces, source-drain voltage increases and causes source region and leakage
When area's PN junction depletion region is close to, the power line in raceway groove can traverse to source region from drain region, and cause source
The problem of barrier height reduction, so that the carrier number of source region injection raceway groove increases, drain terminal electric current increases
Greatly.As the further reduction of channel length, the influence of DIBL effects are increasingly severe, make transistor threshold
Threshold voltage reduction, device voltage gain declines, and then reduces the electric property of semiconductor structure.
For the reduction of more preferable meeting market's demand size, semiconductor technology gradually starts from planar MOSFET
Transistor transient from transistor to the three-dimensional with more high effect, such as fin field effect pipe
(FinFET)。
Although the introducing of fin field effect pipe can to a certain extent suppress DIBL effects partly being led with improving
The electric property of body structure, but, the electric property of the semiconductor structure that prior art is formed still needs to be carried
It is high.
The content of the invention
The problem that the present invention is solved is to provide a kind of semiconductor structure and its manufacture method, improves semiconductor junction
The electric property of structure.
To solve the above problems, the present invention provides a kind of manufacture method of semiconductor structure.Including following step
Suddenly：Semiconductor substrate is provided, the Semiconductor substrate includes the first area and the second area that are disposed adjacent；
Patterned mask layer is formed on the semiconductor substrate, is formed with perpendicular to lining in the hard mask layer
The section shape in basal surface direction is the opening of triangle, and the triangle open mouth includes the first inclined-plane and the
Two inclined-planes, first inclined-plane projection on the semiconductor substrate covers the first area, described
Second area described in second inclined-plane projection covering part on the semiconductor substrate；In the mask layer
It is upper to form the second graph layer for exposing first inclined-plane；With the mask layer and second graph layer as mask
Threshold voltage ion doping technique is adjusted to the Semiconductor substrate, the ion is by second figure
Shape layer is blocked and can form raceway groove in the Semiconductor substrate through the corresponding mask layer in the first area
Area；Remove the mask layer and second graph layer；Grid are formed in the Semiconductor substrate of the first area
Pole structure；Source region and drain region are formed in the Semiconductor substrate of the grid structure both sides.
Optionally, the mask layer is single layer structure.
Optionally, the mask layer is laminated construction, and the top-down etch rate of laminated construction is gradually
Reduce.
Optionally, the material of the mask layer is the one kind in silicon nitride, silicon oxynitride or carbon silicon oxynitride
Or it is various.
Optionally, the thickness of the mask layer isExtremely
Optionally, the technique for forming the mask layer is chemical vapor deposition method.
Optionally, the technique of the graphical mask layer is dry plasma etch technique.
Optionally, the technological parameter of the dry plasma etch technique includes：The pressure of etching cavity is
2mTorr to 200mTorr, etching power is 50W to 3000W, and etching gas are CF4、C4F8、
C4F6、CHF3、CH2F2And CH3One or more gas in F, auxiliary gas is O2、N2、Ar
With one or more gas in He, the gas flow of the etching gas is 0sccm to 500sccm,
The gas flow of the auxiliary gas is 0sccm to 500sccm, and the process time is 5S to 1000S.
Optionally, the technique of the graphical mask layer is wet-etching technology.
Optionally, the technological parameter of the wet-etching technology includes：The etching solution for using is molten for phosphoric acid
Liquid, the volumetric concentration of phosphoric acid is 30% to 95% in the phosphoric acid solution, and technological temperature is 50 DEG C to 200 DEG C,
Process time is 20S to 1000S.
Optionally, the step of threshold voltage ion doping technique is adjusted to the Semiconductor substrate includes：
It is N-type ion through the ion that the corresponding mask layer in first inclined-plane injects to the Semiconductor substrate,
The N-type ion is arsenic ion, and the ion energy of injection is 5Kev to 12Kev, the ion dose of injection
It is 1E12 to 5E13 atom per square centimeters；Or, through the corresponding mask layer pair in first inclined-plane
The ion of the Semiconductor substrate injection is p-type ion, and the p-type ion is boron difluoride ion, note
The ion energy for entering is 3Kev to 10Kev, and the ion dose of injection is 5E12 to 5E14 atom per squares
Centimetre.
Optionally, first inclined-plane projection on the semiconductor substrate covers the first area,
Mask layer positioned at the first area has thickness gradient, and the mask layer positioned at the first area includes
Positioned at the first mask layer region and the second mask layer region at the mask layer two ends, first mask layer
Region is near the center of the opening, and the second mask layer region is described near the edge of the opening
The mask layer thickness in the first mask layer region less than the second mask layer region mask layer thickness, and from
The first mask layer region to the second mask layer region, the thickness of the mask layer gradually increases；
The step of channel region is formed in the Semiconductor substrate includes：Being formed in the Semiconductor substrate has
The channel region of thickness gradient, the channel region includes being located in the corresponding substrate in the first mask layer region
The first channel region, and the second channel region in the corresponding substrate in the second mask layer region,
The channel thickness of first channel region is more than the channel thickness of second channel region, first raceway groove
The Doped ions concentration in area more than second channel region Doped ions concentration, and from first raceway groove
Area to second channel region, the thickness of the channel region is gradually reduced, and Doped ions concentration is gradually reduced.
Optionally, the Doped ions concentration proportion of first channel region and the second channel region is 1：1.5 to
1：5.
Optionally, the step of source region and drain region are formed in the Semiconductor substrate of the grid structure both sides is wrapped
Include：Source region is being formed in the Semiconductor substrate of first channel region, near second raceway groove
Drain region is formed in the Semiconductor substrate in area.
Optionally, the technique for removing the mask layer is wet-etching technology.
Optionally, the solution that the wet-etching technology is used is phosphoric acid solution.
Accordingly, the present invention also provides the semiconductor structure that a kind of use above method is formed, including：Half
Conductor substrate；Grid structure, positioned at the semiconductor substrate surface；Source region and drain region, positioned at the grid
In the Semiconductor substrate of pole structure both sides；Channel region, the semiconductor lining between the source region and drain region
In bottom, the channel region has thickness gradient.
Optionally, the channel region includes the first channel region and the second raceway groove positioned at the channel region two ends
Area, the channel thickness of first channel region more than second channel region channel thickness, and from described
First channel region to second channel region, the thickness of the channel region is gradually reduced.
Optionally, the doping concentration ratio of first channel region and the second channel region is 1：1.5 to 1：5.
Compared with prior art, technical scheme has advantages below：The present invention is by first
The patterned mask layer with the first inclined-plane is formed in the Semiconductor substrate in region, i.e., positioned at described first
The mask layer in region has thickness gradient.Therefore, formed on the mask layer and expose first inclined-plane
Second graph layer, the Semiconductor substrate is adjusted for mask with the mask layer and second graph layer
After whole threshold voltage ion doping technique, the corresponding mask layer in the first inclined-plane is injected into institute described in ion permeable
Stating the depth in the Semiconductor substrate of first area, there is gradient, i.e. channel region to have thickness gradient；Formation source
Behind area and drain region, the channel region is thicker than the thickness of close drain region part near the thickness of region portions, by
It is larger in influence of the channel thickness near source region to carrier mobility, and near the channel thickness in drain region
Influence to carrier mobility is smaller such that it is able to dropped while reducing and carrier mobility is influenceed
The low channel thickness in close drain region, and then the harmful effect of DIBL effects is restrained effectively, improve
The electric property of semiconductor structure.
Brief description of the drawings
Fig. 1 to Fig. 3 be prior art semiconductor structure the embodiment of manufacture method one in each step correspondence tie
Structure schematic diagram；
Fig. 4 to Fig. 9 be semiconductor structure of the present invention the embodiment of manufacture method one in each step counter structure
Schematic diagram；
Figure 10 is the structural representation of another embodiment of manufacture method of semiconductor structure of the present invention.
Specific embodiment
At present, the MOSFET FETs or fin field effect pipe that prior art is formed are mainly symmetry
Transistor.By taking MOSFET FETs as an example, with reference to referring to figs. 1 to Fig. 3, prior art semiconductor
The manufacture method of structure is comprised the following steps：With reference to Fig. 1, there is provided Semiconductor substrate 100, the semiconductor
Substrate 100 includes channel region I and non-channel region II, in the Semiconductor substrate 100 of the non-channel region II
The first graph layer 200 of upper formation；With reference to Fig. 2, with first graph layer 200 as mask, to the ditch
The Semiconductor substrate 100 in road area I is adjusted threshold voltage ion doping technique, in the channel region I
Semiconductor substrate 100 in formed channel region 300；With reference to Fig. 3, the half of the top of the channel region 300
After forming grid structure on conductor substrate 100, in the Semiconductor substrate 100 of the grid structure both sides
Source region 320 and drain region 330 are formed, wherein, the channel region 300 between the source region 320 and drain region 330
It is symmetrical structure, i.e., the channel region 300 of described semiconductor structure is symmetrical channel region.
With the reduction of meeting market's demand size, DIBL effects are increasingly severe, in order to strengthen grid to raceway groove
Control ability, preferably suppress DIBL effects, the thickness of raceway groove is the smaller the better；But carrier mobility
Rate is reduced with the reduction of channel thickness, and reducing channel thickness can cause the electrical of semiconductor devices on the contrary
Can decline.Even if from planar MOSFET transistor to the transistor of the three-dimensional with more high effect
Transition, is still difficult to suppress DIBL effects by reducing channel thickness.
In order to solve the technical problem, the present invention provides a kind of manufacture method of semiconductor structure, including：
Semiconductor substrate is provided, the Semiconductor substrate includes the first area and the second area that are disposed adjacent；
Patterned mask layer is formed in the Semiconductor substrate, is formed with perpendicular to substrate in the hard mask layer
The section shape of surface direction is the opening of triangle, and the triangle open mouth includes the first inclined-plane and second
Inclined-plane, first inclined-plane projection on the semiconductor substrate covers the first area, and described the
Second area described in two inclined-planes projection covering part on the semiconductor substrate；On the mask layer
The second graph layer on first inclined-plane is exposed in formation；With the mask layer and second graph layer for mask pair
The Semiconductor substrate is adjusted threshold voltage ion doping technique, and the ion is by the second graph
Layer is blocked and can form raceway groove in the Semiconductor substrate through the corresponding mask layer in the first area
Area；Remove the mask layer and second graph layer；Grid are formed in the Semiconductor substrate of the first area
Pole structure；Source region and drain region are formed in the Semiconductor substrate of the grid structure both sides.
By forming the patterned mask layer with the first inclined-plane in the Semiconductor substrate of first area,
Mask layer i.e. positioned at the first area has thickness gradient.Therefore, dew is formed on the mask layer
Go out the second graph layer on first inclined-plane, be mask to described half with the mask layer and second graph layer
After conductor substrate is adjusted threshold voltage ion doping technique, the first inclined-plane is corresponding described in ion permeable
It is thick that there is the depth that mask layer is injected into the first area Semiconductor substrate gradient, i.e. channel region to have
Degree gradient；After forming source region and drain region, the channel region near region portions thickness than close drain region portion
The thickness for dividing is thick, and the influence due to the channel thickness near source region to carrier mobility is larger, and is close to
Influence of the channel thickness in drain region to carrier mobility is smaller such that it is able to reducing to carrier mobility
Rate reduces the channel thickness near drain region while influence, and then restrained effectively DIBL effects not
Good influence, improves the electric property of semiconductor structure.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
Fig. 4 to Fig. 9 be semiconductor structure of the present invention the embodiment of manufacture method one in each step counter structure
Schematic diagram.
With reference to Fig. 4, there is provided Semiconductor substrate 400, the Semiconductor substrate 400 includes the He of first area I
Second area II, the Semiconductor substrate 400 of the first area I is used to form channel region.
The material of the substrate 400 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate on insulator or the germanium substrate on insulator to state substrate 400.In the present embodiment,
The substrate 400 is silicon substrate.
In the present embodiment, the Semiconductor substrate 400 is used to form MOSFET FETs.At other
In embodiment, the Semiconductor substrate 400 is additionally operable to form fin field effect pipe (FinFET).
It should be noted that the surface of the Semiconductor substrate 400 is also formed with cushion oxide layer 500.
Because subsequent technique need to form polish stop layer (not shown) in the Semiconductor substrate 400, and
The stress of polish stop layer is larger, when forming the polish stop layer in the Semiconductor substrate 400,
Dislocation easily is caused on the surface of the Semiconductor substrate 400, the cushion oxide layer 500 is for being formation
Cushioning effect is provided during the polish stop layer, it is to avoid institute is directly formed in the Semiconductor substrate 400
The problem of dislocation is produced when stating polish stop layer.
In the present embodiment, the material of the cushion oxide layer 500 is silica, the cushion oxide layer 500
Thickness beExtremelyThe cushion oxide layer 500 can be to be formed using thermal oxidation technology, institute
Stating thermal oxidation technology can be performed using oxidation furnace.
With reference to Fig. 5, mask layer 550 is formed in the Semiconductor substrate 400.
It should be noted that the surface of the Semiconductor substrate 400 is formed with cushion oxide layer 500, it is described to cover
Membrane layers 550 are formed at the surface of the cushion oxide layer 500.
In the present embodiment, the mask layer 550 is used as follow-up adjustment threshold voltage ion doping technique
Mask.
It should be noted that after follow-up completion adjustment threshold voltage ion doping technique, the mask material
Layer 550 need to be removed, therefore the material of the mask layer 550 is easy removed material；Additionally,
The mask layer 550 is located at the surface of the cushion oxide layer 500, in order to ensure to remove the mask
The technique of material layer 550 does not cause loss, the mask layer 550 to the cushion oxide layer 500
Material with the cushion oxide layer 500 is differed.
The mask layer 550 can be single layer structure, and the mask layer 550 can also be folded
Rotating fields, and the top-down etch rate of mask layer 550 of the laminated construction is gradually reduced.
The material of the mask layer 550 is the one kind or many in silicon nitride, silicon oxynitride or carbon silicon oxynitride
Kind.In the present embodiment, the mask layer 550 is single layer structure, the mask layer 550
Material is silicon nitride, and the technique for forming the mask layer 550 is chemical vapor deposition method.
It should be noted that the thickness of the mask layer 550 can not be blocked up, can not be excessively thin.Such as
The thickness of really described mask layer 550 is blocked up, during subsequent ion injection technology, the ion of injection
It is difficult to enter in the predetermined depth of the Semiconductor substrate 400 through the mask layer 550, or even
The ion of injection is difficult to penetrate the mask layer 550, so as to influence the electricity of the semiconductor structure to be formed
Performance；If the thickness of the mask layer 550 is excessively thin, excessively thin mask layer 550 makes described
The thickness gradient of mask layer 550 is smaller, and the thickness gradient of the mask layer 550 is to ion
The depth injected in the Semiconductor substrate 400 produces influence, and excessively thin mask layer 550 is difficult to full
Depth profile demand in Semiconductor substrate 400 described in sufficient ion implanting.Therefore, in the present embodiment, institute
The thickness for stating mask layer 550 isExtremely
With reference to Fig. 6, the graphical mask layer 550 (as shown in Figure 5) forms mask layer 600,
The section shape being formed with the hard mask layer 600 perpendicular to the surface direction of substrate 400 is triangle
Opening 650, the triangle open mouth 650 includes the first inclined-plane 601 and the second inclined-plane 602, described first
Projection of the inclined-plane 601 in the Semiconductor substrate 400 covers the first area I, and described second is oblique
Second area II described in projection covering part of the face 602 in the Semiconductor substrate 400.
In the present embodiment, the mask layer 550 is single layer structure, the mask layer 550
Material is silicon nitride.Therefore, the mask layer 600 is single layer structure, the material of the mask layer 600
It is silicon nitride.
In the present embodiment, the graphical mask layer 550 with formed the technique of mask layer 600 as etc.
Ion dry etch process.The technological parameter of the dry plasma etch technique includes：Etching cavity
Pressure is 2mTorr to 200mTorr, and etching power is 50W to 3000W, and etching gas are CF4、
C4F8、C4F6、CHF3、CH2F2And CH3One or more gas in F, auxiliary gas is O2、
N2, one or more gas in Ar and He, the gas flow of the etching gas for 0sccm extremely
500sccm, the gas flow of the auxiliary gas is 0sccm to 500sccm, the process time be 5S extremely
1000S。
Specifically, the step of forming mask layer 600 includes：On the surface of the mask layer 550
The first graph layer 700 is formed, it is described that first graph layer 700 exposes the first area I and part
Second area II, the first area I for exposing and the part second area II is adjacent and symmetrical；
With first graph layer 700 as mask, the mask material is etched using dry plasma etch technique
Layer 550 until expose the Semiconductor substrate 400, and by the polymerization of the dry plasma etch technique
Thing is controlled, and the section shape formed in the hard mask layer 600 perpendicular to the surface direction of substrate 400 is
The opening 650 of triangle；Remove first graph layer 700.
It should be noted that the etching gas of the graphical mask layer 550 are CF4、C4F8、C4F6、
CHF3、CH2F2And CH3One or more gas in F, the etching gas can be with etching process
Produce polymer and be deposited in the side wall of the opening 650, form inclined side wall, and polymer is more,
Sidewall slope is more obvious, by O2Deng the cooperation of auxiliary gas, sidewall slope angle, formation process are adjusted
The required section shape perpendicular to the surface direction of substrate 400 is the opening 650 of triangle.
In the present embodiment, the material of first graph layer 700 is photoresist.Form the triangle
Behind opening 650, removed photoresist using wet method or cineration technics removes first graph layer 700.
It should be noted that projection covering of first inclined-plane 601 in the Semiconductor substrate 400
The first area I, the i.e. mask layer 600 positioned at the first area I have thickness gradient；It is located at
The mask layer 600 of the first area I is included positioned at the first mask layer area at the two ends of the mask layer 600
Domain A and the second mask layer region B, the first mask layer region A are close to the center of the opening 650,
Edges of the second mask layer region B near the opening 650；The first mask layer region A's
The thickness of mask layer 600 of the thickness of mask layer 600 less than the second mask layer region B, and from institute
The first mask layer region A to the second mask layer region B is stated, the thickness of the mask layer 600 is gradually
Increase.
With reference to Fig. 7 and Fig. 8 is referred to, formed on the mask layer 600 and expose first inclined-plane 601
Second graph layer 710, with the mask layer 600 and second graph layer 710 for mask is served as a contrast to the semiconductor
Bottom 400 is adjusted threshold voltage ion doping technique, and raceway groove is formed in the Semiconductor substrate 400
Area 800 (as shown in Figure 8)；After forming the channel region 800, the mask layer 600 and second is removed
Graph layer 710.
Specifically, the step of channel region 800 are formed in the Semiconductor substrate 400 includes：
The surface of mask layer 600 of the second area II forms second graph layer 710, the second graph layer 710
Expose the first inclined-plane 601 of the mask layer 600；With the mask layer 600 and second graph layer 710
For mask is adjusted threshold voltage ion doping technique, the ion quilt to the Semiconductor substrate 400
The second graph layer 710 blocks and can be through the corresponding mask layer 600 in the first area I, described
Channel region 800 is formed in the Semiconductor substrate 400 of first area I；After forming the channel region 800, go
Except the mask layer 600 and second graph layer 710.
In the present embodiment, the material of the second graph layer 710 is photoresist.Form the channel region 800
Afterwards, removed photoresist using wet method or cineration technics removes the second graph layer 710.Remove the mask layer 600
Technique be wet-etching technology, the solution that the wet-etching technology is used is phosphoric acid solution.
In the present embodiment, the semiconductor structure is N type junction structure or p-type structure.When the semiconductor junction
When structure is N type junction structure, through 600 pairs of semiconductor linings of the corresponding mask layer in first inclined-plane 601
The ion of the injection of bottom 400 is N-type ion, and the N-type ion includes arsenic ion, the ion energy of injection
It is 5Kev to 12Kev, the ion dose of injection is 1E12 to 5E13 atom per square centimeters；When described
When semiconductor structure is p-type structure, through described in the corresponding mask layer in first inclined-plane 601 600 pairs
The ion of the injection of Semiconductor substrate 400 is p-type ion, and the p-type ion is boron difluoride ion, note
The ion energy for entering is 3Kev to 10Kev, and the ion dose of injection is 5E12 to 5E14 atom per squares
Centimetre.
It should be noted that because the mask layer 600 positioned at the first area I has the first inclined-plane 601,
That is, the mask layer 600 positioned at the first area I has thickness gradient；Accordingly, pass through
The corresponding 600 pairs of Semiconductor substrates 400 of mask layer in first inclined-plane 601 are adjusted threshold value electricity
After pressure ion doping technique, the depth that injection ion enters in the Semiconductor substrate 400 of the first area I
Also there is gradient, so as to be formed with thickness gradient in the Semiconductor substrate 400 of the first area I
Channel region 800.
Specifically, if the thickness of the mask layer 600 is larger, injection ion is more difficult through the mask
Layer 600 and enter the Semiconductor substrate 400 in, therefore injection ion enter the Semiconductor substrate 400
Interior depth is smaller, and the doping concentration for injecting ion is relatively low；, whereas if the thickness of the mask layer 600
Degree is smaller, and injection ion is easier to enter in the Semiconductor substrate 400 through the mask layer 600,
Therefore the depth that injection ion enters in the Semiconductor substrate 400 is larger, injects the doping concentration of ion
It is higher.In the present embodiment, the mask layer 600 positioned at the first area I includes being located at the mask layer
First mask layer region A (as shown in Figure 6) at 600 two ends and the second mask layer region B are (such as Fig. 6 institutes
Show), the first mask layer region A is near the inner opening 650 (as shown in Figure 6) of the mask layer 600
Center, the second mask layer region B is near the edge of the mask layer 600 inner opening 650；Institute
State the mask of the thickness less than the second mask layer region B of the mask layer 600 of the first mask layer region A
The thickness of layer 600, and from the first mask layer region A to the second mask layer region B, it is described
The thickness of mask layer 600 gradually increases.Correspondingly, the channel region 800 includes being covered positioned at described first
The first channel region 801 (as shown in Figure 8) in the corresponding substrates 400 of film layer area A, and positioned at institute
State the second channel region 802 (as shown in Figure 8) in the corresponding substrates 400 of the second mask layer region B, institute
State the channel thickness of the channel thickness of the first channel region 801 more than second channel region 802, described the
The Doped ions concentration of one channel region 801 is more than the Doped ions concentration of second channel region 802, and
From first channel region 801 to second channel region 802, the thickness of the channel region 800 gradually subtracts
Small, Doped ions concentration is gradually reduced.
In the present embodiment, the Doped ions concentration ratio of the channel region 802 of first channel region 801 and second
Be worth is 1：1.5 to 1：5.
With reference to Fig. 9, grid structure 900 is formed in the Semiconductor substrate 400 of the top of the first area I；
Source region 950 and drain region 960 are formed in the Semiconductor substrate 400 of the both sides of the grid structure 900.
Specifically, the He of source region 950 is formed in the Semiconductor substrate 400 of the both sides of the grid structure 900
The step of drain region 960, includes：Served as a contrast in the semiconductor near first channel region 801 (as shown in Figure 8)
Source region 950 is formed in bottom 400, in the semiconductor near second channel region 802 (as shown in Figure 8)
Drain region 960 is formed in substrate 400.
With reference to Figure 10, be semiconductor structure of the present invention another embodiment of manufacture method in each step correspondence tie
Structure schematic diagram.The present embodiment is repeated no more with the something in common of a upper embodiment, and the present embodiment is real with upper one
The difference for applying example is：
The patterned mask layer 611 be laminated construction, and the laminated construction mask layer 611 from
Etch rate under above is gradually reduced.In the present embodiment, the material of the mask layer 611 is silicon nitride,
It is any various in silicon oxynitride or carbon silicon oxynitride.
In the present embodiment, the technique of the graphical mask layer 611 is wet-etching technology.The wet method
The technological parameter of etching technics includes：The etching solution for using is phosphoric acid solution, phosphorus in the phosphoric acid solution
Acid volumetric concentration be 30% to 95%, technological temperature be 50 DEG C to 200 DEG C, the process time be 20S extremely
1000S。
Specifically, the step of forming the patterned mask layer 611 includes：In mask layer (figure
Not showing) surface forms the 3rd graph layer 701, and the 3rd graph layer 701 exposes part firstth area
The domain III and part second area IV, the part first area III for exposing and part described
Two region IV are adjacent and symmetrical；With the 3rd graph layer 701 as mask, carved using wet-etching technology
The mask layer 611 is lost until exposing the Semiconductor substrate 401, by each to same of wet-etching technology
Property and the laminated construction the etch rate that is gradually reduced from top to bottom of mask layer 611, described hard
The section shape formed in mask layer 611 perpendicular to the surface direction of substrate 401 is the opening 651 of triangle；
Remove the 3rd graph layer 701.
It should be noted that due to the laminated construction the top-down etch rate of mask layer 611 by
It is decrescence small, when the mask layer 611 of the laminated construction is etched, the mask layer 611 of the laminated construction
Opening size of the opening size of middle last layer more than next layer, so as in the mask layer of whole laminated construction
The section shape formed in 611 perpendicular to the surface direction of substrate 401 is the opening 651 of triangle.
In the present embodiment, the material of the 3rd graph layer 701 is photoresist.Form the triangle
Behind opening 651, removed photoresist using wet method or cineration technics removes the 3rd graph layer 701.
Accordingly, the embodiment of the present invention also provides the semiconductor structure that a kind of use above method is formed.
Please continue to refer to Fig. 9, the schematic diagram of the embodiment of semiconductor structure of the present invention, the semiconductor junction are shown
Structure includes：
Semiconductor substrate 400；
Grid structure 900, positioned at the surface of the Semiconductor substrate 400；
Source region 950, in the Semiconductor substrate 400 of the side of the grid structure 900
Drain region 960, in the Semiconductor substrate 400 of the opposite side of the grid structure 900；
Channel region 800, in the Semiconductor substrate 400 between the source region 950 and drain region 960, institute
Channel region 800 is stated with thickness gradient.
It should be noted that the channel region 800 includes the first ditch positioned at the two ends of the channel region 800
The channel region 802 of road area 801 and second, the channel thickness of first channel region 801 is more than second ditch
The channel thickness in road area 802, the Doped ions concentration of first channel region 801 is more than second ditch
The Doped ions concentration in road area 802, and from first channel region 801 to second channel region 802,
The thickness of the channel region 800 is gradually reduced, and Doped ions concentration is gradually reduced.In the present embodiment, institute
The Doped ions concentration proportion for stating the first channel region 801 and the second channel region 802 is 1：1.5 to 1：5.
In order to inhibit DIBL effects, the thickness of channel region, but carrier mobility need to be reduced with ditch
The reduction of road thickness and reduce and larger near the influence of the channel thickness to carrier mobility of source region, subtract
Small channel thickness can cause the electrical property of semiconductor devices to decline.Accordingly, it is considered to arrive thick near drain region raceway groove
The influence spent to carrier mobility is smaller, by the present invention in that thickness ratio of the channel region near region portions
Thickness near drain region part is thick, i.e., while not influenceing the channel thickness for being close to source region, reduce near leakage
The channel thickness in area such that it is able to reduced while reducing and being influenceed on carrier mobility near drain region
Channel thickness, and then restrained effectively the harmful effect of DIBL effects, improve semiconductor structure
Electric property.
It should be noted that the present invention is illustrated by taking MOSFET FETs as an example, the present invention is also fitted
For fin field effect pipe (FinFET), it is used to suppress the DIBL effects of fin field effect pipe, so as to carry
The electric property of fin field effect pipe high.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (19)
1. a kind of manufacture method of semiconductor structure, it is characterised in that including：
Semiconductor substrate is provided, the Semiconductor substrate includes the first area and the second area that are disposed adjacent；
Patterned mask layer is formed on the semiconductor substrate, is formed with the hard mask layer vertical
Section shape in substrate surface direction is the opening of triangle, and the triangle open mouth includes the first inclined-plane
With the second inclined-plane, first inclined-plane projection on the semiconductor substrate covers the first area,
Second area described in second inclined-plane projection covering part on the semiconductor substrate；
The second graph layer for exposing first inclined-plane is formed on the mask layer；
With the mask layer and second graph layer for mask is adjusted threshold voltage to the Semiconductor substrate
Ion doping technique, the ion is blocked by second graph layer and can be through first area correspondence
Mask layer form channel region in the Semiconductor substrate；
Remove the mask layer and second graph layer；
Grid structure is formed in the Semiconductor substrate of the first area；
Source region and drain region are formed in the Semiconductor substrate of the grid structure both sides.
2. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the mask layer is
Single layer structure.
3. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the mask layer is
Laminated construction, and the top-down etch rate of laminated construction is gradually reduced.
4. the manufacture method of semiconductor structure as claimed in claim 2 or claim 3, it is characterised in that the mask
The material of layer is one or more in silicon nitride, silicon oxynitride or carbon silicon oxynitride.
5. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that the mask layer
Thickness isExtremely
6. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that form the mask
The technique of layer is chemical vapor deposition method.
7. the manufacture method of semiconductor structure as claimed in claim 1, it is characterised in that graphical described to cover
The technique of film layer is dry plasma etch technique.
8. the manufacture method of semiconductor structure as claimed in claim 7, it is characterised in that the plasma is done
The technological parameter of method etching technics includes：The pressure of etching cavity is 2mTorr to 200mTorr, is carved
Erosion power is 50W to 3000W, and etching gas are CF4、C4F8、C4F6、CHF3、CH2F2With
CH3One or more gas in F, auxiliary gas is O2、N2, one kind or many in Ar and He
Gas is planted, the gas flow of the etching gas is 0sccm to 500sccm, the auxiliary gas
Gas flow is 0sccm to 500sccm, and the process time is 5S to 1000S.
9. the manufacture method of semiconductor structure as claimed in claim 3, it is characterised in that graphical described to cover
The technique of film layer is wet-etching technology.
10. the manufacture method of semiconductor structure as claimed in claim 9, it is characterised in that the wet etching
The technological parameter of technique includes：The etching solution for using is phosphoric acid solution, phosphoric acid in the phosphoric acid solution
Volumetric concentration be 30% to 95%, technological temperature be 50 DEG C to 200 DEG C, the process time be 20S extremely
1000S。
The manufacture method of 11. semiconductor structures as claimed in claim 1, it is characterised in that to the semiconductor
The step of substrate is adjusted threshold voltage ion doping technique includes：Through first inclined-plane correspondence
The ion that is injected to the Semiconductor substrate of mask layer be N-type ion, the N-type ion be arsenic from
Son, the ion energy of injection is 5Kev to 12Kev, and the ion dose of injection is 1E12 to 5E13
Atom per square centimeter；
Or, it is P through the ion that the corresponding mask layer in first inclined-plane injects to the Semiconductor substrate
Type ion, the p-type ion is boron difluoride ion, and the ion energy of injection is 3Kev to 10Kev,
The ion dose of injection is 5E12 to 5E14 atom per square centimeters.
The manufacture method of 12. semiconductor structures as claimed in claim 1, it is characterised in that first inclined-plane
Projection on the semiconductor substrate covers the first area, positioned at the mask of the first area
Layer has thickness gradient, and the mask layer positioned at the first area is included positioned at the mask layer two ends
First mask layer region and the second mask layer region, the first mask layer region is near the opening
Center, the second mask layer region is close to the edge of the opening, the first mask layer region
Mask layer thickness less than the second mask layer region mask layer thickness, and from first mask layer
Region to the second mask layer region, the thickness of the mask layer gradually increases；
The step of channel region is formed in the Semiconductor substrate includes：Formed in the Semiconductor substrate
Channel region with thickness gradient, the channel region includes being located at the corresponding lining in the first mask layer region
The first channel region in bottom, and the second raceway groove in the corresponding substrate in the second mask layer region
Area, the channel thickness of the channel thickness more than second channel region of first channel region, described first
The Doped ions concentration of channel region more than second channel region Doped ions concentration, and from described first
Channel region to second channel region, the thickness of the channel region is gradually reduced, and Doped ions concentration is gradually
Reduce.
The manufacture method of 13. semiconductor structures as claimed in claim 12, it is characterised in that first raceway groove
The Doped ions concentration proportion of area and the second channel region is 1：1.5 to 1：5.
The manufacture method of 14. semiconductor structures as claimed in claim 12, it is characterised in that in the grid knot
The step of source region and drain region are formed in the Semiconductor substrate of structure both sides includes：Near first raceway groove
Source region is formed in the Semiconductor substrate in area, is being formed in the Semiconductor substrate of second channel region
Drain region.
The manufacture method of 15. semiconductor structures as claimed in claim 1, it is characterised in that the removal mask
The technique of layer is wet-etching technology.
The manufacture method of 16. semiconductor structures as claimed in claim 14, it is characterised in that the wet etching
The solution that technique is used is phosphoric acid solution.
A kind of 17. semiconductor structures, it is characterised in that including：
Semiconductor substrate；
Grid structure, positioned at the semiconductor substrate surface；
Source region and drain region, in the Semiconductor substrate of the grid structure both sides；
Channel region, in the Semiconductor substrate between the source region and drain region, the channel region has thickness
Degree gradient.
18. semiconductor structures as claimed in claim 17, it is characterised in that the channel region is included positioned at described
First channel region and the second channel region at channel region two ends, the channel thickness of first channel region are more than
The channel thickness of second channel region, the Doped ions concentration of first channel region is more than described the
The Doped ions concentration of two channel regions, and from first channel region to second channel region, it is described
The thickness of channel region is gradually reduced, and Doped ions concentration is gradually reduced.
19. semiconductor structures as claimed in claim 17, it is characterised in that first channel region and the second ditch
The Doped ions concentration proportion in road area is 1：1.5 to 1：5.
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| CN112951917A (en) * | 2021-01-29 | 2021-06-11 | 中国电子科技集团公司第十三研究所 | Gallium oxide field effect transistor and preparation method thereof |
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| CN102365714A (en) * | 2009-01-30 | 2012-02-29 | 先进微装置公司 | Graded well implantation for asymmetric transistors having reduced gate electrode pitches |
| US20140084367A1 (en) * | 2012-09-27 | 2014-03-27 | Silicon Storage Technology, Inc. | Extended Source-Drain MOS Transistors And Method Of Formation |
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| CN101521226A (en) * | 2008-02-26 | 2009-09-02 | 瑞昱半导体股份有限公司 | Metal oxide semiconductor transistor and manufacture method thereof |
| CN102365714A (en) * | 2009-01-30 | 2012-02-29 | 先进微装置公司 | Graded well implantation for asymmetric transistors having reduced gate electrode pitches |
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| CN112951917A (en) * | 2021-01-29 | 2021-06-11 | 中国电子科技集团公司第十三研究所 | Gallium oxide field effect transistor and preparation method thereof |
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