CN102446767A - Manufacturing method of NMOS (N-channel metal oxide semiconductor) transistor - Google Patents
Manufacturing method of NMOS (N-channel metal oxide semiconductor) transistor Download PDFInfo
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- CN102446767A CN102446767A CN2010105119733A CN201010511973A CN102446767A CN 102446767 A CN102446767 A CN 102446767A CN 2010105119733 A CN2010105119733 A CN 2010105119733A CN 201010511973 A CN201010511973 A CN 201010511973A CN 102446767 A CN102446767 A CN 102446767A
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Abstract
The invention discloses a manufacturing method of a NMOS (N-channel metal oxide semiconductor) transistor in the technical field of semiconductors. The manufacturing method comprises the following steps of: providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate and forming a gate positioned on the gate dielectric layer; forming source/drain regions in the semiconductor substrate on the two sides of the gate, implanting fluorine ions and phosphorus ions into the gate during the period of forming the source/drain regions; and after forming the source/drain regions, performing rapid spike annealing and laser pulse annealing in sequence. In the manufacturing method, the fluorine ions enter the gate dielectric layer, and the fluorine ions replace a part of oxygen ions in the gate dielectric layer to form fluorine-silicon groups, which improves quality of the interface between the gate dielectric layer and the semiconductor substrate, so as to improve the hot carrier injection effect.
Description
Technical field
What the present invention relates to is a kind of device making method of technical field of semiconductors, particularly be a kind of manufacturing approach of nmos pass transistor.
Background technology
Along with improving constantly of semiconductor device integrated level; Its characteristic size reduces gradually; Source/drain electrode and source/drain electrode extension area (Source/Drain Extension) correspondingly shoals; The degree of depth of the source/drain junction of current technological level requirement semiconductor device is less than 1000 dusts, and the degree of depth that finally possibly require to tie is at 200 dusts or the littler order of magnitude.
Junction depth reduce the lower heat treatment temperature of requirement; And lower heat treatment temperature is (less than 500 degrees centigrade; Even lower) make the lateral dimension of knot reduce thereupon, the electric field between knot and channel region that reduces to cause device when work, to form of the lateral dimension of said knot forms spike at the edge, boundary of knot and channel region, and promptly the boundary edge at knot and channel region is formed with high electric field; Electronics will receive this high electric field to quicken to be high energy particle in the process that moves; Said high energy particle collision produces electron-hole pair (being called hot carrier), and said hot carrier obtains energy from electric field, can get in gate oxide or the grid; Then influence the threshold voltage control of device and the drift of mutual conductance; Promptly produce HCI (Hot CarrierInjection, hot carrier is injected) effect, thereby cause the rising of threshold voltage, the decline of saturation current and the following degradation of carrier mobility.
The conduction carrier of nmos pass transistor is an electronics, and the transistorized conduction carrier of PMOS is the hole, and the mobility ratio hole of electronics is a lot of greatly; Therefore under same electric field, electronics can obtain bigger energy, under high electric field; Electronics is accelerated and is " hot electron ", and hot hole is difficult to occur.Thus, how to suppress the HCI effect of nmos pass transistor, promptly suppress hot carrier and get into gate oxide or penetrate said gate oxide and get into conducting channel, become those skilled in the art's problem demanding prompt solution.
Current; Industry is to improve the HCI of nmos pass transistor, the optimization method that adopts LDD (Lightly DopedDrain, lightly doped drain injects) ion to inject usually; Utilization reduces the dosage and increase LDD injection energy that the LDD ion injects; Obtain darker LDD knot, reduce transverse electric field intensity, thereby improve HCI.But increase the LDD ion implantation energy, along with the increasing of junction depth, the length of effective channel of device also will reduce, and will increase short-channel effect (Short Channel Effect is called for short SCE) like this, cause the decline of device DC characteristic.Therefore, merely to improve HCI be not enough through changing dosage that the LDD ion injects and energy.
In order to overcome above-mentioned shortcoming, one Chinese patent application number is: 200410089222.1, and name is called: reduce the method that I/O nmos device hot carrier is injected; This technology is at first carried out polysilicon gate etching, carries out polysilicon gate again and reoxidizes, and carries out the LDD rapid thermal annealing then; After the annealing; In LDD, adopt arsenic ion to inject earlier, then in LDD, adopt phosphonium ion to inject, carry out polysilicon side wall deposit and etching at last.But should technology change existing processes, compatible relatively poor with existing technology.
In order to improve the HCI effect of nmos pass transistor, prior art also discloses a kind of technical scheme, annealing after the source/the leakage extended structure forms of nmos pass transistor, so that the foreign ion that low doping source/drain region is injected fully activates and spreads.But in above-mentioned technology, along with dimensions of semiconductor devices continue dwindle, such as in the semiconductor device of 65nm and following size, technique scheme is not enough to suppress hot carrier injection effect, thereby inapplicable.
Summary of the invention
Problem to be solved by this invention is: in the manufacturing process of nmos pass transistor, how to improve the HCI effect.
For addressing the above problem, the present invention provides a kind of manufacturing approach of nmos pass transistor, comprising: Semiconductor substrate is provided; On said Semiconductor substrate, form gate dielectric and be positioned at the grid on the gate dielectric; Formation source/drain region in the Semiconductor substrate of grid both sides, and during formation source/drain region, in said grid, inject fluorine ion and phosphonium ion; Behind formation source/drain region, carry out fast peak annealing and laser pulse annealing successively.
Alternatively, said formation source/drain region comprises successively: the light dope ion injects; In said grid, inject fluorine ion and phosphonium ion; Heavy doping ion is injected.
Alternatively, said formation source/drain region comprises successively: the light dope ion injects; Heavy doping ion is injected; Inject fluorine ion and phosphonium ion in the said grid.
Alternatively, said formation source/drain region comprises successively: in said grid, inject fluorine ion and phosphonium ion; The light dope ion injects; Heavy doping ion is injected.
Alternatively, injection fluorine ion and phosphonium ion comprise in said grid: inject phosphonium ion at said grid earlier, in said grid, inject fluorine ion then.
Alternatively, injection fluorine ion and phosphonium ion comprise in said grid: inject fluorine ion and phosphonium ion simultaneously at said grid.
Alternatively, in said grid, inject fluorine ion simultaneously and phosphonium ion comprises: directly inject PF at said grid
3And PF
5In a kind of or its combination.
Alternatively, the temperature peak scope of said fast peak annealing is 900 ℃ to 1070 ℃, and annealing time is 5 seconds to 60 seconds.
Alternatively, the temperature peak scope of said laser pulse annealing is 1200 ℃ to 1300 ℃.
Compared with prior art; The present invention has the following advantages: the present invention injects fluorine ion in grid, and makes the part fluorine ion diffuse into gate dielectric through the fast peak annealing process, has activated the fluorine ion in the gate dielectric through laser pulse annealing again; Make fluorine ion replace the partial oxygen ion in the gate dielectric; Thereby form the fluorine silicon group,, and then make the interface of gate dielectric and Semiconductor substrate become fine and close more simultaneously because fluorine ion is repaired the function of chemical bond; Improved the interface quality between gate dielectric and Semiconductor substrate; Stop to form charge trap, prevent lightly-doped source under making alive/drain region gathering electric charge, thereby improved the HCI effect of nmos pass transistor greatly.
Description of drawings
Fig. 1 is the schematic flow sheet of the transistorized manufacturing approach of embodiment 1NMOS;
Fig. 2 to Fig. 9 is the sketch map that forms nmos pass transistor according to flow process shown in Figure 1;
Figure 10 is the schematic flow sheet of the transistorized manufacturing approach of embodiment 2NMOS;
Figure 11 is the schematic flow sheet of the transistorized manufacturing approach of embodiment 3NMOS.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part; HCI is owing in nmos pass transistor, there is stronger transverse electric field, makes the charge carrier ionization that in the process that transports, bumps to produce extra electron hole pair; In portion of hot charge carrier injection grid oxide layer or the grid, thereby produce the HCI effect.
Therefore, when making semiconductor device, for preventing above-mentioned generation of defects.The manufacturing approach of nmos pass transistor provided by the invention comprises: Semiconductor substrate is provided; On said Semiconductor substrate, form gate dielectric and be positioned at the grid on the gate dielectric; Formation source/drain region in the Semiconductor substrate of grid both sides, and during formation source/drain region, in said grid, inject fluorine ion and phosphonium ion; Behind formation source/drain region, carry out fast peak annealing and laser pulse annealing successively.The present invention adds fluorine ion in grid; And make the part fluorine ion diffuse into gate dielectric through the fast peak annealing process, activated the fluorine ion in the gate dielectric through laser pulse annealing again, make fluorine ion replace the partial oxygen ion in the gate dielectric; Thereby form the fluorine silicon group; Repair the function of chemical bond simultaneously owing to fluorine ion, and then make the interface of gate dielectric and Semiconductor substrate become fine and close more, improved the interface quality between gate dielectric and Semiconductor substrate; Thereby improved the HCI of nmos pass transistor greatly, and can good and existing process compatible.
Embodiment 1
As shown in Figure 1, the manufacturing approach of nmos pass transistor may further comprise the steps in the present embodiment:
S100 provides Semiconductor substrate;
S101 forms gate dielectric and is positioned at the grid on the gate dielectric on said Semiconductor substrate;
S102 carries out the light dope ion and injects in the Semiconductor substrate of grid both sides, form lightly-doped source/drain region;
S103 injects fluorine ion and phosphonium ion in said grid;
S104 carries out heavy doping ion and injects in the Semiconductor substrate of grid both sides, form heavy-doped source/drain region;
S105 carries out fast peak annealing and laser pulse annealing successively.
With reference to figure 2, at first execution in step S100 provides Semiconductor substrate 200.Wherein, said Semiconductor substrate 200 for the silicon that is formed with semiconductor device, the silicon-on-insulator (SOI) that is formed with semiconductor device, or be body silicon.
Then execution in step S101 forms gate dielectric 201 and is positioned at the grid 202 on the gate dielectric 201 on said Semiconductor substrate 200, and gate dielectric 201 constitutes grid structure with grid 202, forms structure as shown in Figure 3.
Said gate dielectric 201 is silicon dioxide or silicon oxynitride, and it forms technology can be chemical vapor deposition method.
Said grid 202 is polysilicon or multicrystalline silicon compounds; It forms technology can adopt any prior art well known to those skilled in the art; As when adopting chemical vapour deposition technique, can be low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition.
Then execution in step S102 carries out the light dope ion and injects in the Semiconductor substrate 200 of grid 202 both sides, forms lightly-doped source/drain region 203.In the prior art, it is to be mask with gate dielectric 201 with grid 202 that the light dope ion of nmos pass transistor injects, and in Semiconductor substrate 200, carries out the light dope ion and injects, formation unactivated lightly-doped source/drain region 203a Semiconductor substrate 200 in.Because this zone is N type MOS transistor zone, the dopant ion that said light dope ion injects can be phosphonium ion or arsenic ion etc.
When the ion of light dope ion injection was phosphonium ion, the energy range that ion injects was 1KeV to 20KeV, and the dosage range that ion injects is 1E14/cm
2To 1E15/cm
2
When the ion of light dope ion injection was arsenic ion, the energy range that ion injects was 2KeV to 35KeV, and the dosage range that ion injects is 1E14/cm
2To 1E15/cm
2
Further, in step S102, before or after carrying out the injection of light dope ion, can also carry out the injection of bag-like region ion and form unactivated bag-like region 204a, form structure as shown in Figure 4.What need explanation is the ionic conduction type opposite that ion that said bag-like region ion injects and light dope ion inject.Accordingly; Before or after light dope ion in step S102 injects, also having carried out the bag-like region ion injects; After forming the technology of unactivated bag-like region 204a; Then in step S102, also comprise through spike annealing at a slow speed forming bag-like region 204 and lightly-doped source/drain region 203 of activating, form structure as shown in Figure 5.
In addition; In the embodiment of above-mentioned manufacturing nmos pass transistor; Spike annealing technology is after injection of light dope ion and bag-like region ion implantation step, to carry out at a slow speed; But not as limit, in other embodiments, spike annealing technology also can divide secondary to carry out at a slow speed; Promptly after light dope ion implantation step, carry out the first time of spike annealing step and after bag-like region ion implantation step, carry out the second time of spike annealing step at a slow speed at a slow speed, should too much not limit protection scope of the present invention at this.
Follow execution in step S103; In said grid 202, inject phosphonium ion 207 and fluorine ion 208, form structure as shown in Figure 6, wherein ● expression phosphonium ion 207; ★ representes fluorine ion 208; Sketch map just here, can not represent phosphonium ion 207 and fluorine ion 208 reality implantation dosage and inject the degree of depth, this should be not too much restriction protection scope of the present invention.
Said injection phosphonium ion 207 is to inject phosphonium ion 207 at said grid 202 earlier with fluorine ion 208, in said grid 202, injects fluorine ion 208 then; Or in said grid 202, inject fluorine ion 208 and phosphonium ion 207 simultaneously.
In said grid 202, inject phosphonium ion 207 in the ban, when in said grid 202, injecting fluorine ion 208 then: the injection energy range of said fluorine ion 208 is 2KeV to 20KeV, and the implantation dosage scope is 1E14/cm
2To 3E15/cm
2The injection energy range of said phosphonium ion 207 is 3KeV to 10KeV, and the implantation dosage scope is 1E15/cm
2To 5E15/cm
2, to reduce the loss of said grid 202.
When in said grid 202, injecting fluorine ion 208 simultaneously, can be in said grid 202, directly to inject PF with phosphonium ion 207
3And PF
5In a kind of or its combination, this moment, to inject energy range be 3KeV to 10KeV, the implantation dosage scope is 1E15/cm
2To 6E15/cm
2
Execution in step S104 carries out heavy doping ion and injects in the Semiconductor substrate 200 of said grid 202 both sides then, forms heavy-doped source/drain region 206.
Further; The said heavy doping ion of carrying out is injected and to be comprised: the relative both sides at said gate dielectric 201 and said grid 202 form isolated side wall 205, form structure as shown in Figure 7 (isolated side wall 205 can be in silica, silicon nitride, the silicon oxynitride a kind of or they make up arbitrarily); Is mask with said grid 202 with said isolated side wall 205, in Semiconductor substrate 200, injects phosphonium ion or arsenic ion to form heavy-doped source/drain region 206, forms structure as shown in Figure 8.
When in Semiconductor substrate 200, injecting phosphonium ion when forming heavy-doped source/drain region 206, the energy range that ion injects is 8KeV to 30KeV, and the ion implantation dosage scope is 1.5E14/cm
2To 6E15/cm
2
When in Semiconductor substrate 200, injecting arsenic ion when forming heavy-doped source/drain region 206, the energy range that ion injects is 8KeV to 50KeV, and the ion implantation dosage scope is 1.5E14/cm
2To 6E15/cm
2
Last execution in step S105 carries out fast peak annealing and laser pulse annealing successively.
The temperature peak scope of said fast peak annealing is 900 ℃ to 1070 ℃, and annealing time is 5 seconds to 60 seconds, and the fast peak annealing of this moment can make the center divide fluorine ion 208 to diffuse into gate dielectric 201, with reference to shown in Figure 9.
The temperature peak scope of said laser pulse annealing is 1200 ℃ to 1300 ℃; The laser pulse annealing of this moment can make the fluorine ion 208 that gets into gate dielectric 201 be activated; And the partial oxygen ion that the fluorine ion 208 that is activated replaces in the gate dielectric 201; Thereby form the fluorine silicon group, bring into play the function that fluorine ion is repaired chemical bond simultaneously, and then make the interface of gate dielectric 201 and Semiconductor substrate 200 become fine and close more.
Present embodiment is through after adding the technology of injecting fluorine ion in grid 202, the nmos pass transistor of preparing can be through the system performance testing of HCI; And the nmos pass transistor that adopts prior art for preparing to go out can not be through the system performance testing of HCI.
Embodiment 2
Shown in figure 10, the manufacturing approach of nmos pass transistor may further comprise the steps in the present embodiment:
S300 provides Semiconductor substrate;
S301 forms gate dielectric and is positioned at the grid on the gate dielectric on said Semiconductor substrate;
S302 carries out the light dope ion and injects in the Semiconductor substrate of grid both sides, form lightly-doped source/drain region;
S303 carries out heavy doping ion and injects in the Semiconductor substrate of grid both sides, form heavy-doped source/drain region;
S304 injects fluorine ion and phosphonium ion in said grid;
S305 carries out fast peak annealing and laser pulse annealing successively.
The difference of present embodiment and embodiment 1 only is that " in the Semiconductor substrate of grid both sides, carrying out heavy doping ion injects; form heavy-doped source/drain region " step is different with the execution sequence of " in said grid, injecting fluorine ion and phosphonium ion " step, and carrying into execution a plan that each step is concrete is identical with embodiment 1.
Present embodiment through technology that in grid, add to inject fluorine ion after, the nmos pass transistor of preparing can be through the system performance testing of HCI, and effect is with embodiment 1; And the nmos pass transistor that adopts prior art for preparing to go out can not be through the system performance testing of HCI.
Embodiment 3
Shown in figure 11, the manufacturing approach of nmos pass transistor may further comprise the steps in the present embodiment:
S400 provides Semiconductor substrate;
S401 forms gate dielectric and is positioned at the grid on the gate dielectric on said Semiconductor substrate;
S402 injects fluorine ion and phosphonium ion in said grid;
S403 carries out the light dope ion and injects in the Semiconductor substrate of grid both sides, form lightly-doped source/drain region;
S404 carries out heavy doping ion and injects in the Semiconductor substrate of grid both sides, form heavy-doped source/drain region;
S405 carries out fast peak annealing and laser pulse annealing successively.
The difference of present embodiment and embodiment 1 only is that " in the Semiconductor substrate of grid both sides, carrying out the light dope ion injects; form lightly-doped source/drain region " step is different with the execution sequence of " in said grid, injecting fluorine ion and phosphonium ion " step, and carrying into execution a plan that each step is concrete is identical with embodiment 1.
Present embodiment through technology that in grid, add to inject fluorine ion after, the nmos pass transistor of preparing can be through the system performance testing of HCI, and effect is with embodiment 1; And the nmos pass transistor that adopts prior art for preparing to go out can not be through the system performance testing of HCI.
Only in grid, inject phosphonium ion in the prior art to reduce the loss of grid; And the compatibility of the present invention and prior art is very strong; Just in grid, inject after the phosphonium ion or also injected fluorine ion at grid when injecting phosphonium ion, and make the part fluorine ion diffuse into gate dielectric, activated the fluorine ion in the gate dielectric through laser pulse annealing again through the fast peak annealing process; Make fluorine ion replace the partial oxygen ion in the gate dielectric; Thereby form the fluorine silicon group,, and then make the interface of gate dielectric and Semiconductor substrate become fine and close more simultaneously because fluorine ion is repaired the function of chemical bond; Improved the interface quality between gate dielectric and Semiconductor substrate; Stop to form charge trap, prevent lightly-doped source under making alive/drain region gathering electric charge, thereby improved the HCI effect of nmos pass transistor greatly.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
1. the manufacturing approach of a nmos pass transistor comprises: Semiconductor substrate is provided; On said Semiconductor substrate, form gate dielectric and be positioned at the grid on the gate dielectric; Formation source/drain region in the Semiconductor substrate of grid both sides; It is characterized in that,
During formation source/drain region, in said grid, inject fluorine ion and phosphonium ion;
Also comprise: behind formation source/drain region, carry out fast peak annealing and laser pulse annealing successively.
2. the manufacturing approach of nmos pass transistor according to claim 1 is characterized in that, said formation source/drain region comprises successively: the light dope ion injects; In said grid, inject fluorine ion and phosphonium ion; Heavy doping ion is injected.
3. the manufacturing approach of nmos pass transistor according to claim 1 is characterized in that, said formation source/drain region comprises successively: the light dope ion injects; Heavy doping ion is injected; In said grid, inject fluorine ion and phosphonium ion.
4. the manufacturing approach of nmos pass transistor according to claim 1 is characterized in that, said formation source/drain region comprises successively: in said grid, inject fluorine ion and phosphonium ion; The light dope ion injects; Heavy doping ion is injected.
5. according to the manufacturing approach of claim 2 or 3 or 4 described nmos pass transistors, it is characterized in that said light dope ion injects and comprises: be mask with the grid, in Semiconductor substrate, inject phosphonium ion or arsenic ion to form lightly-doped source/drain region; When the ion of light dope ion injection was phosphonium ion, the energy range that ion injects was 1KeV to 20KeV, and the dosage range that ion injects is 1E14/cm
2To 1E15/cm
2When the ion of light dope ion injection was arsenic ion, the energy range that ion injects was 2KeV to 35KeV, and the dosage range that ion injects is 1E14/cm
2To 1E15/cm
2
6. according to the manufacturing approach of claim 2 or 3 or 4 described nmos pass transistors, it is characterized in that said heavy doping ion is injected and comprised: the relative both sides at said gate dielectric and said grid form isolated side wall; With said grid and said isolated side wall is mask, in Semiconductor substrate, injects phosphonium ion or arsenic ion to form heavy-doped source/drain region; When in Semiconductor substrate, injecting phosphonium ion when forming heavy-doped source/drain region, the energy range that ion injects is 8KeV to 30KeV, and the ion implantation dosage scope is 1.5E14/cm
2To 6E15/cm
2When injecting arsenic ion in Semiconductor substrate when forming heavy-doped source/drain region, the energy range that ion injects is 8KeV to 50KeV, and the ion implantation dosage scope is 1.5E14/cm
2To 6E15/cm
2
7. the manufacturing approach of nmos pass transistor according to claim 1 is characterized in that, injection fluorine ion and phosphonium ion comprise in said grid: inject phosphonium ion at said grid earlier, in said grid, inject fluorine ion then.
8. the manufacturing approach of nmos pass transistor according to claim 7 is characterized in that, the injection energy range of said fluorine ion is 2KeV to 20KeV, and the implantation dosage scope is 1E14/cm
2To 3E15/cm
2The injection energy range of said phosphonium ion is 3KeV to 10KeV, and the implantation dosage scope is 1E15/cm
2To 5E15/cm
2
9. the manufacturing approach of nmos pass transistor according to claim 1 is characterized in that, injection fluorine ion and phosphonium ion comprise in said grid: inject fluorine ion and phosphonium ion simultaneously at said grid.
10. the manufacturing approach of nmos pass transistor according to claim 9 is characterized in that, in said grid, injects fluorine ion simultaneously and phosphonium ion comprises: directly inject PF at said grid
3And PF
5In a kind of or its combination, the injection energy range is 3KeV to 10KeV, the implantation dosage scope is 1E15/cm
2To 6E15/cm
2
11. the manufacturing approach of nmos pass transistor according to claim 1 is characterized in that, the temperature peak scope of said fast peak annealing is 900 ℃ to 1070 ℃, and annealing time is 5 seconds to 60 seconds.
12. the manufacturing approach of nmos pass transistor according to claim 1 is characterized in that, the temperature peak scope of said laser pulse annealing is 1200 ℃ to 1300 ℃.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103681276A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal gate, forming method of MOS transistor and forming method of CMOS structure |
| CN104078359A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and manufacturing method thereof |
| CN113224097A (en) * | 2021-04-25 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for improving negative signal of CIS product |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103681276A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal gate, forming method of MOS transistor and forming method of CMOS structure |
| CN104078359A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and manufacturing method thereof |
| CN113224097A (en) * | 2021-04-25 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for improving negative signal of CIS product |
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