CN109148589A - High-voltage LDMOS device process for making and high-voltage LDMOS device - Google Patents
High-voltage LDMOS device process for making and high-voltage LDMOS device Download PDFInfo
- Publication number
- CN109148589A CN109148589A CN201810984597.6A CN201810984597A CN109148589A CN 109148589 A CN109148589 A CN 109148589A CN 201810984597 A CN201810984597 A CN 201810984597A CN 109148589 A CN109148589 A CN 109148589A
- Authority
- CN
- China
- Prior art keywords
- dnw
- drift region
- type
- injection
- deep
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000002347 injection Methods 0.000 claims abstract description 23
- 239000007924 injection Substances 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000002513 implantation Methods 0.000 claims abstract description 6
- 230000019552 anatomical structure morphogenesis Effects 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims abstract description 3
- 238000000576 coating method Methods 0.000 claims abstract description 3
- 239000002019 doping agent Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of high-voltage LDMOS device process for making, include the following steps: step 1, form NBL layers in the upper end Selective implantation of P type substrate, grow to form p-type epitaxial layer in P type substrate upper end；Step 2, coating photoresist, are connected in NBL isolation structure forming DNW, are fully opened the injection region DNW by photoetching；The photoresist pattern that partially opens of intermittent is used injecting the injection region to form drift region using DNW；The drift region for the photoresist morphogenesis high-voltage LDMOS device for carrying out DNW injection, being connected in NBL isolation structure in DNW and forming deep N-well, while being partially opened using DNW injection and intermittent, the doping concentration of the drift region are less than the doping concentration of deep n-type trap.The invention also discloses a kind of high-voltage LDMOS devices.The present invention can effectively improve the breakdown voltage of LDMOS and reduce manufacturing cost.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, and more particularly to a kind of high-voltage LDMOS, (horizontal proliferation metal is aoxidized
Object semiconductor transistor) device making technics method.The invention further relates to a kind of high-voltage LDMOS devices.
Background technique
It is well known that breakdown voltage BV is higher, the concentration of the drift region of LDMOS device must be smaller, therefore with DNW
(Deep N-type Well deep n-type trap) is in the LDMOS device of drift region, for the breakdown voltage for improving device, it is necessary to reduce
The dosage of DNW injection.In entire technique platform and in the LDMOS device, DNW is NBL (N-type in connection isolation structure
Buried Layer n type buried layer) a part；That is DNW must be connect with NBL by injection and thermal process.DNW dosage is got over
Small, DNW is more difficult to connect with NBL.Therefore the opening for needing to increase DNW injection in the case that dosage is small just can guarantee DNW and NBL
Connection is abundant.The area that will increase device in this way is unfavorable for reducing manufacturing cost.It can be manufactured in the case where not reducing DNW dosage
The LDMOS device of higher BV is conducive to improve technique competitiveness, reduces manufacturing cost.
In Fig. 1,101 be P type substrate, and 102 be n type buried layer, and 103 be p-type epitaxial layer, and 104 be p-well, and 107 be gate oxide
And polysilicon layer, 108 be p-type heavily doped region, and 109 be N-type heavily doped region, and 110 be N trap, 111-deep n-type traps, 112-DTI
(deep trench isolation) oxide layer, 113 be STI (shallow trench isolation) field oxygen.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of high-voltage LDMOS device process for making, can effectively improve
The breakdown voltage of LDMOS simultaneously reduces manufacturing cost；For this purpose, the present invention also provides a kind of high-voltage LDMOS device.
In order to solve the above technical problems, high-voltage LDMOS device process for making of the invention, includes the following steps:
Step 1, NBL layers of the upper end Selective implantation formation in P type substrate, grow to be formed outside p-type in P type substrate upper end
Prolong layer；
Step 2, coating photoresist, are connected in NBL isolation structure forming DNW, by photoetching that the injection region DNW is complete
It opens；In the photoresist pattern that the injection region for forming drift region uses intermittent to partially open；DNW injection is carried out, depth N is formed
Trap, while the drift region of the photoresist morphogenesis high-voltage LDMOS device partially opened using DNW injection and intermittent,；DNW
After the completion of injection, keep the drift region dopant profiles uniform by thermal process, and the doping concentration of the drift region is made to be less than deep n-type
The doping concentration of trap.
High-voltage LDMOS device of the invention, has a deep N-well and a drift region, and the DNW injection doping of the drift region is dense
The DNW that degree is less than deep n-type trap injects doping concentration.
Using method of the invention, due to the drift region DNW of the high-voltage LDMOS device whole doping concentration injected be less than every
Doping concentration from DNW in connection structure, and the breakdown voltage of device, therefore this can be improved in the doping concentration for reducing drift region
Invention can effectively improve the breakdown voltage of LDMOS device.
Method of the invention is conducive to improve technique competitiveness, reduces manufacturing cost without increasing additional processing step.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is LDMOS device structural schematic diagram；
Fig. 2 forms NBL and p-type epitaxial layer schematic diagram；
Fig. 3 is the drift region schematic diagram to form deep n-type trap and LDMOS；
Fig. 4 is the device architecture schematic diagram using high-voltage LDMOS device process for making production.
Specific embodiment
In the following embodiments, fabrication processing is as follows for the high-voltage LDMOS device process for making:
Step 1, referring to fig. 2 forms NBL202 in the upper end Selective implantation of P type substrate 201, in P type substrate 201
Growth forms p-type epitaxial layer 203.
Step 2, referring to Fig. 3, apply photoresist 215, be connected in NBL isolation structure forming DNW, passing through photoetching will
The injection region DNW fully opens；The photoresist pattern that partially opens of intermittent is used in the injection region for forming the drift region of LDMOS,
The photoresist pattern can reduce the doping that DNW is injected into drift region, and dopant profiles heterogeneous are formed after the completion of injection
Drift region.DNW injection is carried out, deep n-type trap 211 and the drift region of high-voltage LDMOS device of high-dopant concentration, i.e. low-mix are formed
The deep n-type trap 214 of miscellaneous concentration.After the completion of injection, make the drift region of LDMOS by heat-flash process, dopant profiles more evenly, and
And can make LDMOS drift region doping concentration be less than high-dopant concentration deep n-type trap 211.Therefore LDMOS can be improved
Breakdown voltage.Not needing to increase additional processing step in implementation process can be realized the LDMOS device with higher BV,
Therefore the present invention advantageously reduces process costs.
Step 3, referring to fig. 4 forms STI oxygen 213 on the top of p-type epitaxial layer 203, and the lower end of STI oxygen 213 is formed
DTI (deep trench isolation) structure 212, Selective implantation forms N trap 210, p-well 204 on the top of p-type epitaxial layer 203, in p-type
The upper end of epitaxial layer 203 forms gate oxide and polysilicon layer 207, and ion implanting forms N-type heavily doped region 209, p-type heavy doping
Area 208.Last part technology is consistent with traditional cmos process.
Heretofore described high pressure > 100V.
By emulation, the high-voltage LDMOS device made of method of the invention can effectively reduce drift region doping
Concentration, and improve breakdown voltage.
The drift region of existing process for making, LDMOS device is injected using DNW, the concentration and isolation junction of drift region
DNW concentration is the same in structure.Process of the invention passes through the concentration of DNW in special photoresist morphogenesis isolation structure
Greater than the concentration for the DNW for being used as drift region, it is minimized drift region concentration, improves BV.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of high-voltage LDMOS device process for making, which comprises the steps of:
Step 1, NBL layers of the upper end Selective implantation formation in P type substrate, grow to form p-type extension in P type substrate upper end
Layer；
Step 2, coating photoresist, are connected in NBL isolation structure forming DNW, are beaten the injection region DNW completely by photoetching
It opens；In the photoresist pattern that the injection region for forming drift region uses intermittent to partially open；DNW injection is carried out, deep N-well is formed,
The drift region of the photoresist morphogenesis high-voltage LDMOS device partially opened simultaneously using DNW injection and intermittent；DNW injection
After the completion, make the drift region dopant profiles uniform by thermal process, and the doping concentration of the drift region is made to be less than deep n-type
The doping concentration of trap.
2. the method as described in claim 1, it is characterised in that: further include step 3, form STI on the top of p-type epitaxial layer
Oxygen, the lower end of STI oxygen form DTI structure, and Selective implantation forms N trap, p-well on the top of p-type epitaxial layer, in p-type extension
The upper end of layer forms gate oxide and polysilicon layer, and ion implanting forms N-type heavy doping, p-type heavily doped region.
3. the method as described in claim 1, it is characterised in that: the deep N-well and drift region, by with along with DNW inject and formed.
4. the method as described in claim 1, it is characterised in that: the high pressure > 100V.
5. a kind of high-voltage LDMOS device, it is characterised in that: there is a deep N-well and a drift region, the DNW of the drift region injects
The DNW that doping concentration is less than deep n-type trap injects doping concentration.
6. device as claimed in claim 5, it is characterised in that: the deep N-well and drift region, by with along with DNW inject and formed.
7. device as claimed in claim 5, it is characterised in that: the high pressure > 100V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810984597.6A CN109148589A (en) | 2018-08-28 | 2018-08-28 | High-voltage LDMOS device process for making and high-voltage LDMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810984597.6A CN109148589A (en) | 2018-08-28 | 2018-08-28 | High-voltage LDMOS device process for making and high-voltage LDMOS device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109148589A true CN109148589A (en) | 2019-01-04 |
Family
ID=64828588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810984597.6A Pending CN109148589A (en) | 2018-08-28 | 2018-08-28 | High-voltage LDMOS device process for making and high-voltage LDMOS device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109148589A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785634A (en) * | 2020-06-30 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
| CN117457747A (en) * | 2023-12-22 | 2024-01-26 | 粤芯半导体技术股份有限公司 | DEMOS structure of embedded flash memory technology and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931004A (en) * | 2009-06-22 | 2010-12-29 | 宏海微电子股份有限公司 | Structure of transverse diffusion metal oxide semiconductor field effect transistor |
| US20120112277A1 (en) * | 2010-10-28 | 2012-05-10 | Texas Instruments Incorporated | Integrated lateral high voltage mosfet |
| CN104716185A (en) * | 2013-12-17 | 2015-06-17 | 德州仪器公司 | High voltage lateral dmos transistor with optimized source-side blocking capability |
| CN106887452A (en) * | 2015-10-29 | 2017-06-23 | 飞思卡尔半导体公司 | Self-adjustable isolation biasing in semiconductor devices |
-
2018
- 2018-08-28 CN CN201810984597.6A patent/CN109148589A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101931004A (en) * | 2009-06-22 | 2010-12-29 | 宏海微电子股份有限公司 | Structure of transverse diffusion metal oxide semiconductor field effect transistor |
| US20120112277A1 (en) * | 2010-10-28 | 2012-05-10 | Texas Instruments Incorporated | Integrated lateral high voltage mosfet |
| CN104716185A (en) * | 2013-12-17 | 2015-06-17 | 德州仪器公司 | High voltage lateral dmos transistor with optimized source-side blocking capability |
| CN106887452A (en) * | 2015-10-29 | 2017-06-23 | 飞思卡尔半导体公司 | Self-adjustable isolation biasing in semiconductor devices |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111785634A (en) * | 2020-06-30 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
| CN111785634B (en) * | 2020-06-30 | 2024-03-15 | 上海华虹宏力半导体制造有限公司 | LDMOS device and process method |
| CN117457747A (en) * | 2023-12-22 | 2024-01-26 | 粤芯半导体技术股份有限公司 | DEMOS structure of embedded flash memory technology and preparation method thereof |
| CN117457747B (en) * | 2023-12-22 | 2024-06-04 | 粤芯半导体技术股份有限公司 | DEMOS structure of embedded flash memory technology and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104992977B (en) | NLDMOS device and its manufacturing method | |
| CN102412126B (en) | Technological method for manufacturing supervoltage laterally diffused metal oxide semiconductor (LDMOS) | |
| CN105931983A (en) | Low-cost Mask Reduction Method And Device For High Voltage Devices | |
| CN105789311A (en) | Transverse diffusion field effect transistor and manufacturing method therefor | |
| CN101924131B (en) | Transverse-diffusion MOS (Metal Oxide Semiconductor) device and manufacturing method thereof | |
| CN102723353B (en) | High voltage power LDMOS device and manufacture method thereof | |
| CN102412162B (en) | Method for improving breakdown voltage of N-groove laterally diffused metal oxide semiconductor (LDMOS) | |
| CN103178087A (en) | Ultra-high voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure and production method thereof | |
| CN103579005B (en) | Power transistor using the anti-injection of high voltage | |
| CN109148589A (en) | High-voltage LDMOS device process for making and high-voltage LDMOS device | |
| CN104282762B (en) | Radio frequency horizontal dual pervasion field effect transistor and preparation method thereof | |
| CN110323138A (en) | A kind of manufacturing method of LDMOS device | |
| CN103107191B (en) | High-voltage P-type LDMOS structure and manufacture method thereof | |
| CN109119458B (en) | Isolation structure and process method | |
| CN106409675A (en) | Production method for depletion mode power transistor | |
| CN104638003B (en) | Radio frequency LDMOS device and process | |
| CN103811402B (en) | A kind of isolation structure process for making of ultrahigh voltage BCD technology | |
| CN104465774A (en) | Isolated LDMOS device and manufacturing method thereof | |
| CN107785324A (en) | High-pressure process integrated circuit method | |
| CN105957880A (en) | High voltage LDMOS device and the processing method for the same | |
| CN106206259A (en) | A kind of method reducing variodenser minimum capacity | |
| CN106206677A (en) | The laterally junction termination structures of high voltage power device | |
| CN103178109A (en) | High voltage isolation n-type Lateral Double-Diffused Metal Oxide Semiconductor (NLDMOS) structure and manufacture method thereof | |
| CN106169506B (en) | DDD MOS device structure and its manufacturing method | |
| CN103035637B (en) | ESD device in RFLDMOS technique and manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190104 |