CN107785324A - High-pressure process integrated circuit method - Google Patents
High-pressure process integrated circuit method Download PDFInfo
- Publication number
- CN107785324A CN107785324A CN201710851519.4A CN201710851519A CN107785324A CN 107785324 A CN107785324 A CN 107785324A CN 201710851519 A CN201710851519 A CN 201710851519A CN 107785324 A CN107785324 A CN 107785324A
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- China
- Prior art keywords
- injection
- resistance
- integrated circuit
- pressure process
- circuit method
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
Abstract
The invention discloses a kind of high-pressure process integrated circuit method, comprising：Step 1, injection forms N-type deep trap in P type substrate, and injection forms p-well；Thermal oxide layer is formed in high resistance region；Step 2, the overall of impurity is carried out to device surface to inject, the concentration of adjustment N-type deep-well region silicon face doping, and then adjust PMOS threshold voltages and reach design requirement；Step 3, grid thermal oxide layer and polysilicon are deposited, carries out low-doped injection, regulation polycrystalline Load Resistance reaches the resistance requirement of high value resistor, completes the etching shaping of polysilicon gate and high value resistor, completes the source-drain electrode injection of PMOS and NMOS in CMOS；Step 4, inter-level dielectric is deposited, contact hole is etched and makes electrode, draws.The present invention is injected to adjust the resistance value of high value resistor using the low-doped p-type of CMOS gate polysilicon, is adjusted the square resistance of polysilicon gate simultaneously using CMOS source region and drain region injection, is saved a lithography step of high value resistor, save process costs.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relates to a kind of high-pressure process integrated circuit method.
Background technology
In current high pressure BCD integrated circuit technologies, low pressure well region is typically formed using N traps, p-well, it is deep to spread trap DNW shapes
Into the drift region of high tension apparatus.High value resistor then generally deposits one layer of polysilicon and additionally increases a second layer polysilicon light shield
And formed by the way that injection is lightly doped.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of high-pressure process integrated circuit method, can reduce technique
Cost.
To solve the above problems, a kind of high-pressure process integrated circuit method of the present invention, includes the steps：
Step 1, according to High voltage BCD process, injection forms N-type deep trap in P type substrate, and injection forms p-well；In height
Hinder region and form thermal oxide layer；
Step 2, the overall of impurity is carried out to device surface to inject, the concentration of adjustment N-type deep-well region silicon face doping, and then
Adjustment PMOS threshold voltages reach design requirement；
Step 3, grid thermal oxide layer and polysilicon are deposited, carries out low-doped injection, regulation polycrystalline Load Resistance reaches high
It is worth the resistance requirement of resistance；Complete the etching shaping of polysilicon gate and high value resistor；Complete the source of PMOS and NMOS in CMOS
Drain electrode injection；
Step 4, inter-level dielectric is deposited, contact hole is etched and makes electrode, draws.
Further, in the step 1, the injection of N traps is substituted using the injection of N-type deep trap, it is overall by device surface
Injection regulation PMOS threshold voltage.
Further, the impurity that described device surface integrally injects is arsenic, and Implantation Energy is 80~120keV, injectant
Measure as 9E11~5E12cm-2。
Further, in the step 2, the impurity integrally injected is arsenic or phosphorus, and Implantation Energy is 80~140keV, injection
Dosage is 1E11~6E11cm-2。
Further, in the step 3, while polysilicon gate is completed using the injection of PMOS and NMOS source-drain electrode
Doping, adjust the resistance of polysilicon gate.
High-pressure process integrated circuit method of the present invention,, can for cmos device on the basis of conventional flowsheet
To save N traps and be substituted using N-type deep trap.Thus PMOS device will be changed into surface channel device from buried channel devices, can be by
General note N-type injection is adjusted PMOS threshold voltages.The polysilicon of high value resistor and the lithography step of secondary polysilicon are saved, can
To use CMOS gate polysilicon and inject low-doped p-type regulation high value resistor square resistance.And the gate polycrystalline of device portions
Silicon can be injected to adjust grid polycrystalline silicon square resistance by the source electrode of subsequent technique.Save process costs.
Brief description of the drawings
Fig. 1 is the structural representation of device in BCD techniques, the high value resistor in CMOS regions and right side comprising left side
Area.
Fig. 2~5 are present invention process step schematic diagrams.
Fig. 6 is present invention process flow chart of steps.
Embodiment
High-pressure process integrated circuit method of the present invention, includes the steps：
Step 1, according to High voltage BCD process, CMOS areas and higher-pressure region (or high value resistor area, high resistance area are divided on substrate
Domain), injection forms N-type deep trap DNW in P type substrate, and injection forms p-well.As shown in Figure 2.Compared to traditional handicraft, this hair
The bright injection using N-type deep trap substitutes the injection of N traps in traditional handicraft, and regulation PMOS threshold value is integrally injected by device surface
Voltage.
The impurity that described device surface integrally injects is arsenic, and Implantation Energy is 80~120keV, implantation dosage 9E11
~5E12cm-2。
Meanwhile it is consistent with traditional handicraft, thermal oxide layer LOCOS is formed in the high resistance region of device, is subsequently formed high level
Resistance.
Step 2, being injected as shown in figure 3, carrying out the overall of impurity to device surface, the impurity integrally injected is arsenic or phosphorus,
Implantation Energy is 80~140keV, and implantation dosage is 1E11~6E11cm-2.Adjust the dense of the silicon face doping in N-type deep trap region
Degree, and then adjust PMOS threshold voltages and reach design requirement.
Step 3, as shown in figure 4, deposit grid thermal oxide layer and polysilicon, carry out low-doped p type impurity injection, regulation
High value resistor polycrystalline Load Resistance reaches resistance requirement；Complete the etching shaping of polysilicon gate and high value resistor；Complete CMOS
Middle PMOS and NMOS source-drain electrode injection.Simultaneously polysilicon gate is completed using the injection of PMOS and NMOS source-drain electrode again
Doping, adjust the resistance of polysilicon gate.
Step 4, it is as shown in figure 5, identical with common process, inter-level dielectric is deposited, contact hole is etched and makes electrode, draws
Go out.
The present invention is injected to adjust high value resistor compared to traditional handicraft using the low-doped p-type of CMOS gate polysilicon
Resistance value, the square resistance for carrying out while adjusting polysilicon gate is injected using CMOS source region and drain region, saves high value resistor
A lithography step, save process costs.
The preferred embodiments of the present invention are these are only, are not intended to limit the present invention.Come for those skilled in the art
Say, the present invention there can be various modifications and variations.Within the spirit and principles of the invention, it is any modification for being made, equivalent
Replace, improve etc., it should be included in the scope of the protection.
Claims (5)
- A kind of 1. high-pressure process integrated circuit method, it is characterised in that：Include the steps：Step 1, according to High voltage BCD process, injection forms N-type deep trap in P type substrate, and injection forms p-well；In high resistance area Domain forms thermal oxide layer；Step 2, the overall of impurity is carried out to device surface to inject, the concentration of adjustment N-type deep-well region silicon face doping, and then adjust PMOS threshold voltages reach design requirement；Step 3, grid thermal oxide layer and polysilicon are deposited, carries out low-doped injection, regulation polycrystalline Load Resistance reaches high level electricity The resistance requirement of resistance；Complete the etching shaping of polysilicon gate and high value resistor；Complete the source-drain electrode of PMOS and NMOS in CMOS Injection；Step 4, inter-level dielectric is deposited, contact hole is etched and makes electrode, draws.
- 2. high-pressure process integrated circuit method as claimed in claim 1, it is characterised in that：It is deep using N-type in the step 1 The injection of trap substitutes the injection of N traps, and regulation PMOS threshold voltage is integrally injected by device surface.
- 3. high-pressure process integrated circuit method as claimed in claim 2, it is characterised in that：Described device surface integrally injects Impurity be arsenic, Implantation Energy is 80~120keV, and implantation dosage is 9E11~5E12cm-2。
- 4. high-pressure process integrated circuit method as claimed in claim 1, it is characterised in that：In the step 2, integrally inject Impurity is arsenic or phosphorus, and Implantation Energy is 80~140keV, and implantation dosage is 1E11~6E11cm-2。
- 5. high-pressure process integrated circuit method as claimed in claim 1, it is characterised in that：In the step 3, utilize simultaneously Injecting to complete the doping of polysilicon gate for PMOS and NMOS source-drain electrode, adjusts the resistance of polysilicon gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710851519.4A CN107785324A (en) | 2017-09-19 | 2017-09-19 | High-pressure process integrated circuit method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710851519.4A CN107785324A (en) | 2017-09-19 | 2017-09-19 | High-pressure process integrated circuit method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107785324A true CN107785324A (en) | 2018-03-09 |
Family
ID=61438159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201710851519.4A Pending CN107785324A (en) | 2017-09-19 | 2017-09-19 | High-pressure process integrated circuit method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786328A (en) * | 2017-11-10 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and its manufacturing method |
| CN114023702A (en) * | 2022-01-06 | 2022-02-08 | 南京华瑞微集成电路有限公司 | Manufacturing method of intelligent power MOS (Metal oxide semiconductor) transistor for solving resistance nonlinearity |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4517731A (en) * | 1983-09-29 | 1985-05-21 | Fairchild Camera & Instrument Corporation | Double polysilicon process for fabricating CMOS integrated circuits |
| CN1471724A (en) * | 2000-11-03 | 2004-01-28 | Lm��������绰��˾ | Integration of high voltage self-aligned MOS components |
| CN1901164A (en) * | 2005-07-22 | 2007-01-24 | 三洋电机株式会社 | Manufacturing method of semiconductor device |
| CN102087998A (en) * | 2009-12-04 | 2011-06-08 | 无锡华润上华半导体有限公司 | Dual polycrystalline structure device and manufacturing method thereof |
-
2017
- 2017-09-19 CN CN201710851519.4A patent/CN107785324A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4517731A (en) * | 1983-09-29 | 1985-05-21 | Fairchild Camera & Instrument Corporation | Double polysilicon process for fabricating CMOS integrated circuits |
| CN1471724A (en) * | 2000-11-03 | 2004-01-28 | Lm��������绰��˾ | Integration of high voltage self-aligned MOS components |
| CN1901164A (en) * | 2005-07-22 | 2007-01-24 | 三洋电机株式会社 | Manufacturing method of semiconductor device |
| CN102087998A (en) * | 2009-12-04 | 2011-06-08 | 无锡华润上华半导体有限公司 | Dual polycrystalline structure device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786328A (en) * | 2017-11-10 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and its manufacturing method |
| CN114023702A (en) * | 2022-01-06 | 2022-02-08 | 南京华瑞微集成电路有限公司 | Manufacturing method of intelligent power MOS (Metal oxide semiconductor) transistor for solving resistance nonlinearity |
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Application publication date: 20180309 |
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