CN102087998A - Dual polycrystalline structure device and manufacturing method thereof - Google Patents
Dual polycrystalline structure device and manufacturing method thereof Download PDFInfo
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- CN102087998A CN102087998A CN2009101886199A CN200910188619A CN102087998A CN 102087998 A CN102087998 A CN 102087998A CN 2009101886199 A CN2009101886199 A CN 2009101886199A CN 200910188619 A CN200910188619 A CN 200910188619A CN 102087998 A CN102087998 A CN 102087998A
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Abstract
The invention relates to a method for manufacturing a dual polycrystalline structure device, which comprises the following steps of: forming a pit and an active area on a substrate, and thermally growing a field oxide layer; performing thermal oxide growth of a first grid oxide layer; depositing a first polycrystalline silicon layer; forming a polycrystalline silicon resistor by plasma injection; forming a bottom plate and a first grid of a polycrystalline silicon capacitor by plasma injection, and removing the redundant first polycrystalline layer by etching; performing thermal treatment on the dual polycrystalline structure device; performing thermal oxide growth of a second grid oxide layer and growing an insulation medium; performing threshold adjustment and injection; depositing a second polycrystalline silicon layer; and forming a top plate and a second grid of the polycrystalline silicon capacitor by plasma injection, and etching to remove the redundant second polycrystalline silicon layer. In the dual polycrystalline structure device manufactured by the method provided by the invention, the grids of high and low-voltage devices are manufactured by two layers of different polycrystalline silicon, the processes such as thermal treatment and grid oxide layer growth are separated, so the parameter characteristics of high and low-voltage devices can be adjusted independently without influencing one another.
Description
[technical field]
The present invention relates to integrated circuit fabrication process, relate in particular to a kind of pair of polycrystalline structure device, also relate to the manufacture method of a kind of pair of polycrystalline structure device.
[background technology]
Two polycrystalline (Double Poly) technology is widely used in the integrated circuit manufacturing; but extensiveization along with integrated circuit; make that the integrated level of manufacture of semiconductor is more and more higher; complicated one of them result who brings of technology is that the compatibility between device requires to improve; expedited the emergence of and made bipolar tube (Bipolar) on the same chip, the technology of devices such as CMOS and DMOS (BCD technology).Because part category is various, the compatibility that must accomplish high tension apparatus and low-voltage device; The compatibility of bipolar process and CMOS technology, the DMOS compatibility of high-voltage CMOS and various puncture voltages.
The gate electrode of all devices all is to adopt with one deck polysilicon in traditional two polycrystalline technologies.For example with the grid of first polysilicon layer as metal-oxide-semiconductor, and the bottom crown of electric capacity; Second polysilicon layer is used for doing resistance, and the top crown of electric capacity.Its technological process is: the first step, at first inject with mode deposit one deck polysilicon of low-pressure chemical vapor phase deposition (LPCVD) and to it, follow depositing metal (titanium on polysilicon layer, cobalt, Deng) or metallide (tungsten silicon) to obtain lower resistance, remove by photoetching and corrosion then and remove unnecessary polysilicon; Second step, the dielectric layer of deposit electric capacity; The 3rd step: deposit second polysilicon layer, form polysilicon resistance by injecting than low dosage, then inject the top crown of electric capacity and the exit of polysilicon resistance, then by photoetching and the unnecessary polysilicon of erosion removal by selectivity.Thereby form grid, polysilicon resistance and the polysilicon capacitance of polysilicon in disk surfaces.
Adopt this traditional structure can cause following problem: because the gate electrode of all devices all is to adopt with one deck polysilicon, in device manufacturing processes, will certainly influence each other, what especially the different heat treatment process of high-low voltage device was brought influences each other, and can cause the change of device electrical performance.Must adopt other means that device is adjusted in order to eliminate this influence, make process complications, the device construction cycle is elongated.
[summary of the invention]
In order to solve the interactional problem of high-low pressure grid that traditional double polycrystalline technology causes, be necessary to provide the manufacture method of a kind of pair of polycrystalline structure device.
The manufacture method of a kind of pair of polycrystalline structure device may further comprise the steps: form trap and active area on substrate, and heat is given birth to the long field oxide layer; Thermal oxide growth first grid oxide layer; Deposit first polysilicon layer; Adopt plasma to inject and form polysilicon resistance; Inject formation polysilicon capacitance bottom crown and first grid by plasma, and etch away the first unnecessary polysilicon layer; Described pair of polycrystalline structure device heat-treated; Thermal oxide growth second grid oxide layer, and growth dielectric; The threshold value adjustment is injected; Deposit second polysilicon layer; Inject formation polysilicon capacitance top crown and second grid by plasma, and etch away the second unnecessary polysilicon layer.
Preferably, the thickness of described first grid oxide layer is 6nm～200nm.
Preferably, described growth dielectric is to carry out the heat growth in thermal oxide growth second grid oxide layer on the polysilicon capacitance bottom crown.
Preferably, described dielectric is a silicon dioxide.
Preferably, it is not need photoetching that described threshold value adjustment is injected, and directly carries out.
In order to solve the interactional problem of high-low pressure grid of traditional double polycrystalline structure device, also be necessary to provide a kind of pair of polycrystalline structure device.
A kind of pair of polycrystalline structure device, comprise substrate, first grid oxide layer of substrate surface, second grid oxide layer, an oxygen layer, first grid on first grid oxide layer, second grid on second grid oxide layer, polysilicon resistance, polysilicon capacitance bottom crown on the oxygen layer of field, the dielectric on polysilicon capacitance bottom crown surface, the polysilicon capacitance top crown on the dielectric; Described polysilicon capacitance bottom crown, polysilicon resistance and first grid adopt same polysilicon layer to form, and described polysilicon capacitance top crown and second grid adopt same polysilicon layer to form.
Preferably, described first grid oxide layer is to grow in different steps with second grid oxide layer.
Preferably, the thickness of described first grid oxide layer is 6nm～200nm.
The above-mentioned pair of polycrystalline structure device and manufacture method thereof, utilize two-layer different polysilicon respectively as the grid of high and low pressure device, technologies such as the heat treatment of high-low voltage device, growth of gate oxide layer are separated, make the parameter characteristic of high-low voltage device independently to adjust, be independent of each other.
[description of drawings]
Fig. 1 is the schematic diagram of the two polycrystalline structure devices of the present invention.
[embodiment]
Fig. 1 is the schematic diagram of the two polycrystalline structure devices of the present invention.The manufacture method of two polycrystalline structure devices may further comprise the steps:
(1) adopt the known standard technology of those skilled in the art on substrate 100, to form trap and active area (figure does not show), and heat is given birth to long field oxide layer 109.
(2) thermal oxide growth first grid oxide layer 101.This layer is the oxide layer of high tension apparatus grid, and thickness is 6nm～200nm, can adjust according to the parameter request of high tension apparatus, and can the oxide layer of low-voltage device grid do not impacted, and also just can the performance of low-voltage device do not impacted.Described high tension apparatus refers to the known DMOS of those skilled in the art, the higher devices of puncture voltage such as IGBT, JFET, and low-voltage device refers to low voltage CMOS, the device that puncture voltages such as BJT are lower.
(3) deposit first polysilicon layer.In preferred embodiment, adopt the technology of low-pressure chemical vapor phase deposition (LPCVD) that this polysilicon is carried out deposit; In other embodiments, also can adopt atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition technologies such as (PECVD) to realize.
(4) first polysilicon layer is carried out plasma and inject formation polysilicon resistance 102, in preferred embodiment, adopt phosphorus or potassium to inject, implantation dosage is adjusted according to the actual resistance demand.
(5) first polysilicon layer is carried out plasma and inject formation polysilicon capacitance bottom crown 103 and first grid 104, and etch away resistance 102, bottom crown 103, the first grid 104 first unnecessary polysilicon layer in addition.
(6) according to the high tension apparatus parameters needed two polycrystalline structure devices are heat-treated.Because this moment, low-voltage device did not also form, and therefore can the characteristic of low-voltage device not impacted.
(7) thermal oxide growth low pressure grid oxide layer 105, the oxide layer of growing on bottom crown 103 simultaneously forms dielectric 106.Second grid oxide layer 105 is oxide layers of low-voltage device grid, and thickness can be adjusted according to the parameter request of low-voltage device.When utilizing thermal oxide growth second grid oxide layer on the polysilicon capacitance bottom crown growth dielectric 106, saved the step of deposit in the traditional handicraft or growth dielectric 106, accelerated speed of production, reduced production cost.
(8) the threshold value adjustment of area of low pressure is injected.By the plasma injection technology voltage threshold of low-voltage device is adjusted.Because this moment, the channel surface of high-pressure area was covered by first grid 104, therefore can directly inject, and had saved the step of a photoetching with respect to traditional handicraft, had accelerated speed of production, had reduced production cost.
(9) deposit second polysilicon layer.In preferred embodiment, adopt the technology of low-pressure chemical vapor phase deposition (LPCVD) that this polysilicon is carried out deposit; In other embodiments, also can adopt atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition technologies such as (PECVD) to realize.
(10) inject second polysilicon layer by plasma and form polysilicon capacitance top crown 108 and second grid 107, and etch away top crown 108, the second grid 107 second unnecessary polysilicon layer in addition.
Deposit separator afterwards, metal line, passivation step can be undertaken by the known standard technology of those skilled in the art, do not repeat them here.
As shown in Figure 1, adopt two polycrystalline structure devices of said method manufacturing to comprise substrate 100, first grid oxide layer 101 of substrate surface, second grid oxide layer 105, an oxygen layer 109, first grid 104 on first grid oxide layer 101, second grid 107 on second grid oxide layer 105, polysilicon resistance 102, polysilicon capacitance bottom crown 103 on the field oxygen layer 109, the dielectric 106 on polysilicon capacitance bottom crown 103 surfaces, the polysilicon capacitance top crown 108 on the dielectric 106.
The two polycrystalline structure devices that adopt the inventive method to make, utilize two-layer different polysilicon respectively as the grid of high and low pressure device, technologies such as the heat treatment of high-low voltage device, growth of gate oxide layer are separated, make the parameter characteristic of high-low voltage device independently to adjust, be independent of each other.The dielectric of growing on the polysilicon capacitance bottom crown when utilizing thermal oxide growth low pressure grid oxide layer has saved the step of deposit in the traditional handicraft or growth dielectric; Because the channel surface of higher-pressure region is covered by the high pressure grid, therefore can directly inject when carrying out the threshold value adjustment injection of area of low pressure, save the step of a photoetching with respect to traditional handicraft, thereby accelerated speed of production, reduce production cost.
The above embodiment has only expressed embodiments of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (8)
1. the manufacture method of two polycrystalline structure devices may further comprise the steps:
On substrate, form trap and active area, and heat is given birth to the long field oxide layer;
Thermal oxide growth first grid oxide layer;
Deposit first polysilicon layer;
Adopt plasma to inject and form polysilicon resistance;
Inject formation polysilicon capacitance bottom crown and first grid by plasma, and etch away the first unnecessary polysilicon layer;
Described pair of polycrystalline structure device heat-treated;
Thermal oxide growth second grid oxide layer, and growth dielectric;
The threshold value adjustment is injected;
Deposit second polysilicon layer;
Inject formation polysilicon capacitance top crown and second grid by plasma, and etch away the second unnecessary polysilicon layer.
2. the manufacture method of according to claim 1 pair of polycrystalline structure device is characterized in that: the thickness of described first grid oxide layer is 6nm～200nm.
3. the manufacture method of according to claim 1 pair of polycrystalline structure device is characterized in that: described growth dielectric is to carry out the heat growth in thermal oxide growth second grid oxide layer on the polysilicon capacitance bottom crown.
4. the manufacture method of according to claim 3 pair of polycrystalline structure device is characterized in that: described dielectric is a silicon dioxide.
5. the manufacture method of according to claim 1 pair of polycrystalline structure device is characterized in that: it is not need photoetching that described threshold value adjustment is injected, and directly carries out.
6. two polycrystalline structure device, comprise substrate, first grid oxide layer of substrate surface, second grid oxide layer, an oxygen layer, first grid on first grid oxide layer, second grid on second grid oxide layer, polysilicon resistance, polysilicon capacitance bottom crown on the oxygen layer of field, the dielectric on polysilicon capacitance bottom crown surface, the polysilicon capacitance top crown on the dielectric; It is characterized in that described polysilicon capacitance bottom crown, polysilicon resistance and first grid adopt same polysilicon layer to form, described polysilicon capacitance top crown and second grid adopt same polysilicon layer to form.
7. according to claim 6 pair of polycrystalline structure device is characterized in that: described first grid oxide layer is to grow in different steps with second grid oxide layer.
8. according to claim 7 pair of polycrystalline structure device is characterized in that: the thickness of described first grid oxide layer is 6nm～200nm.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489830A (en) * | 2012-06-08 | 2014-01-01 | 北大方正集团有限公司 | Method for manufacturing integrated circuit |
| CN103578949A (en) * | 2012-07-30 | 2014-02-12 | 上海华虹Nec电子有限公司 | Integrated production method of grid polysilicon and polysilicon resistors |
| CN104347504A (en) * | 2013-08-08 | 2015-02-11 | 北大方正集团有限公司 | Manufacturing method of mixed signal integrated circuit |
| CN107785324A (en) * | 2017-09-19 | 2018-03-09 | 上海华虹宏力半导体制造有限公司 | High-pressure process integrated circuit method |
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| CN1691353A (en) * | 2004-04-26 | 2005-11-02 | 统宝光电股份有限公司 | Thin-film transistor and method for making same |
| CN101013664A (en) * | 2006-01-30 | 2007-08-08 | 三洋电机株式会社 | Method of manufacturing semiconductor device |
| CN101483153A (en) * | 2008-01-07 | 2009-07-15 | 中芯国际集成电路制造(上海)有限公司 | Semi-conductor device manufacturing process capable of being optimized |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1691353A (en) * | 2004-04-26 | 2005-11-02 | 统宝光电股份有限公司 | Thin-film transistor and method for making same |
| CN101013664A (en) * | 2006-01-30 | 2007-08-08 | 三洋电机株式会社 | Method of manufacturing semiconductor device |
| CN101483153A (en) * | 2008-01-07 | 2009-07-15 | 中芯国际集成电路制造(上海)有限公司 | Semi-conductor device manufacturing process capable of being optimized |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489830A (en) * | 2012-06-08 | 2014-01-01 | 北大方正集团有限公司 | Method for manufacturing integrated circuit |
| CN103489830B (en) * | 2012-06-08 | 2016-10-05 | 北大方正集团有限公司 | A kind of preparation method of integrated circuit |
| CN103578949A (en) * | 2012-07-30 | 2014-02-12 | 上海华虹Nec电子有限公司 | Integrated production method of grid polysilicon and polysilicon resistors |
| CN103578949B (en) * | 2012-07-30 | 2016-11-02 | 上海华虹宏力半导体制造有限公司 | Grid polycrystalline silicon and polysilicon resistance integrated manufacturing method |
| CN104347504A (en) * | 2013-08-08 | 2015-02-11 | 北大方正集团有限公司 | Manufacturing method of mixed signal integrated circuit |
| CN107785324A (en) * | 2017-09-19 | 2018-03-09 | 上海华虹宏力半导体制造有限公司 | High-pressure process integrated circuit method |
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Effective date of registration: 20170926 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214000 No. 5 Hanjiang Road, national hi tech Industrial Development Zone, Wuxi, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |
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