CN102867749B - Method for forming MOS (metal oxide semiconductor) transistor - Google Patents
Method for forming MOS (metal oxide semiconductor) transistor Download PDFInfo
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- CN102867749B CN102867749B CN201110188555.XA CN201110188555A CN102867749B CN 102867749 B CN102867749 B CN 102867749B CN 201110188555 A CN201110188555 A CN 201110188555A CN 102867749 B CN102867749 B CN 102867749B
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Abstract
The invention discloses a method for forming an MOS (metal oxide semiconductor) transistor. The method comprises the following steps of: providing a semiconductor substrate; forming gate structures on the semiconductor substrate; etching the semiconductor substrate; forming a first trench between the gate structures, wherein the width of the bottom of the first trench is larger than the space between the gate structures; etching the first trench so as to form a second trench; and forming a source region and a drain region inside the second trench. According to the technical scheme provided by the invention, by changing process parameters of dry etching, trenches are formed inside the semiconductor substrate, and the bottoms of the trenches are relatively wider, so that the phenomenon that a closed angle occurs at the bottoms of the trenches during later wet etching is prevented.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of MOS transistor.
Background technology
Metal-oxide-semicondutor (metal oxide semiconductor, MOS) field-effect transistor is as the most basic device in semiconductor manufacture, be widely used in various integrated circuits, MOS transistor is divided into P channel type MOS transistor and N channel type MOS transistor.
Along with constantly reducing of dimensions of semiconductor devices, in the following manufacturing process of 32nm, be difficult to promote by further reducing characteristic size the performance of semiconductor device.And for MOS transistor, normally adopt strained silicon technology, the in the situation that of reduction of device characteristic size not, improve the device performance of MOS transistor.At present, strained silicon technology is mainly divided into overall strain and local train.Wherein, overall strain gauge technique refers to that stress is produced by substrate, and can cover all transistor area that are produced on substrate.The material that for example, can produce overall strain comprises germanium silicon on insulating barrier (SiGe On Insulator, SGOI), SiGe virtual substrate etc.Local train technology normally only in the part of semiconductor device to semiconductor channel region stress application.For example, at source-drain area, inject germanium silicon (SiGe) or carborundum (SiC), dual stressed layers technology etc.
But existing local train technology is Shortcomings also, take at source-drain area injection germanium silicon (SiGe) is example.Referring to figs. 1 to form the generalized section of source-drain area in the prior art shown in Fig. 4 between grid.
As shown in Figure 1, provide Semiconductor substrate 10; As shown in Figure 2, in described Semiconductor substrate 10, form grid structure, described grid structure comprises the gate dielectric layer 11 that is formed in Semiconductor substrate 10, is formed at the grid 12 on gate dielectric layer 11 and is formed at grid 12 side wall 13 around; As shown in Figure 3, adopt dry etching to carry out etching to Semiconductor substrate 10, between described grid structure, form groove 14; As shown in Figure 4, adopt wet etching to continue etching to groove 14, formation groove 14 '.In subsequent technique, will, at described groove 14 ' interior deposit Germanium silicon, form source region, drain region (not shown in Fig. 4).
But, along with reducing of dimensions of semiconductor devices, distance between described grid structure hour, is utilized the groove 14 that said method forms ' be unfavorable for that subsequent deposition germanium silicon forms source region, drain region, thereby it is poor to cause finally forming the device performance of MOS transistor.The patent application document that more technical schemes about MOS transistor and forming method thereof can be 200810202960.0 with reference to Chinese Patent Application No..
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of MOS transistor, avoids occurring wedge angle phenomenon at the channel bottom that forms source region or drain region.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of MOS transistor, comprises the steps: to provide Semiconductor substrate; In described Semiconductor substrate, form grid structure; Semiconductor substrate described in etching forms the first groove between described grid structure; Described in etching, the first groove forms the second groove; In described the second groove, form source region, drain region.
Alternatively, Semiconductor substrate described in described etching, the method that forms the first groove between described grid structure is dry etching.
Alternatively, the parameter of described dry etching is as follows: reacting gas comprises CF
4, Cl
2, O
2and Ar, wherein said CF
4gas flow be 10-200sccm, described Cl
2gas flow be 10-200sccm, described O
2gas flow be that the gas flow of 10-50sccm, described Ar is 50-200sccm; Reaction time is 10s-60s; Reaction pressure is 10-100mTorr; Bias voltage is 10-200W; Transformer coupled plasma power is 100-1000W.
Alternatively, the method that described in etching, the first groove forms the second groove is wet etching.
Alternatively, the reaction solution of described wet etching comprises Tetramethylammonium hydroxide (TMAH), and its concentration is 10%-40%; Reaction temperature is 60-90 degree Celsius.
Alternatively, described grid structure comprises the gate dielectric layer that is formed in described Semiconductor substrate, is formed at the grid on described gate dielectric layer and is formed at described grid side wall around.
Alternatively, described source region, drain region form by deposit Germanium silicon.
Alternatively, after the first groove forms the second groove described in etching, form source region, drain region in described the second groove before, also comprise step: by reflux technique, described Semiconductor substrate is processed.
Alternatively, the reative cell of described reflux technique is reflow ovens, and the temperature range in described reflow ovens is at 800-850 degree Celsius.
Compared with prior art, the technical program has the following advantages: in forming the process of MOS transistor, first, form grid structure in Semiconductor substrate; Then, in Semiconductor substrate between grid structure, form groove, the technique of described formation groove is divided into two processes: first by being dry-etched in, form the first groove in Semiconductor substrate, the width of described the first channel bottom is greater than the spacing between described grid structure, by wet etching, described the first groove is continued to etching more afterwards, form the second groove.Finally, in described the second groove, form source region, drain region.Owing to can form bottom width in Semiconductor substrate, be greater than the first groove of grid structure spacing, thereby avoided follow-up, the first groove carried out to wet etching while forming the second groove, at described the second channel bottom, occur wedge angle phenomenon.
In the specific embodiment of the invention, one group of technological parameter for above-mentioned dry etching is provided, as follows: reacting gas comprises CF
4, Cl
2, O
2and Ar, wherein said CF
4gas flow be 10-200sccm, described Cl
2gas flow be 10-200sccm, described O
2gas flow be that the gas flow of 10-50sccm, described Ar is 50-200sccm; Reaction time is 10s-60s; Reaction pressure is 10-100mTorr; Bias voltage is 10-200W; Transformer coupled plasma power is 100-1000W.
By the dry etching of above-mentioned technological parameter, in Semiconductor substrate, can form the first groove that bottom width is greater than grid structure spacing, thereby avoided follow-up, the first groove is carried out to wet etching while forming the second groove, at described the second channel bottom, occur wedge angle phenomenon.
Accompanying drawing explanation
Fig. 1 to Fig. 5 forms the generalized section of source-drain area between grid in prior art;
Fig. 6 is the schematic flow sheet of embodiment of the formation method of a kind of MOS transistor of the present invention;
Fig. 7 to Figure 11 is the cross-sectional view that the present invention forms a kind of specific embodiment of MOS transistor.
Embodiment
With reference to figure 1-Fig. 4, inventor finds in forming the process of MOS transistor, along with the spacing between grid structure reduces, when adopting dry etching to carry out etching to Semiconductor substrate 10, the bottom width of the groove 14 forming is also less, conventionally with grid structure between spacing identical, when further adopting wet etching to continue described groove 14 etching, due to very fast to the etch rate of groove 14 bottoms, therefore be easy to produce as shown in Figure 5, groove 14 ' bottom there is the situation of wedge angle 15, this forms source region to subsequent deposition germanium silicon, drain region can produce adverse influence, cause deposition germanium silicon cannot fill up completely groove 14 ', thereby affect the device performance of MOS transistor.
For those skilled in the art be can better understand the present invention, below in conjunction with accompanying drawing and specific embodiment, describe MOS transistor of the present invention and forming method thereof in detail.
Fig. 6 is the schematic flow sheet of embodiment of the formation method of MOS transistor of the present invention, and with reference to figure 6, the method for the formation MOS transistor of the specific embodiment of the invention comprises:
Step S1: Semiconductor substrate is provided;
Step S2: form grid structure in described Semiconductor substrate;
Step S3: Semiconductor substrate described in etching, between described grid structure, form the first groove, the width of described the first channel bottom is greater than the spacing between described grid structure;
Step S4: described in etching, the first groove forms the second groove;
Step S5: form source region, drain region in described the second groove.
Further, if Fig. 7 to Figure 11 is the cross-sectional view of the specific embodiment of a kind of MOS transistor of formation of the present invention, in conjunction with describe the method for the formation MOS transistor of the specific embodiment of the invention in detail with reference to figure 6 and Fig. 7 to Figure 11.
In conjunction with reference to figure 6 and Fig. 7, perform step S1, Semiconductor substrate 20 is provided.In embodiments of the present invention, described Semiconductor substrate 20 can be the III-V compounds of group such as monocrystalline silicon or GaAs.
In conjunction with reference to figure 6 and Fig. 8, perform step S2, in described Semiconductor substrate 20, form grid structure.In embodiments of the present invention, described grid structure comprises the gate dielectric layer 21 that is positioned in Semiconductor substrate 20, is positioned at the grid 22 on gate dielectric layer 21 and is positioned at described grid 22 side wall 23 around.In embodiments of the present invention, the material of described gate dielectric layer 21 can be silica, but in practical application, is not limited to silica, and its thickness can need to be determined according to actual process.The material of described grid 22 can be polysilicon or metal material (for example, metallic aluminium), but in practical application, is not limited to above-mentioned material.Described side wall 23 can be single layer structure, and for example monox lateral wall, can be also laminated construction, for example laminated construction of silica and silicon nitride.
The method that forms described grid structure is: in described Semiconductor substrate 20, form successively dielectric layer, form conductive layer on dielectric layer, and adopt photoetching, the graphical described dielectric layer of etching technics and conductive layer to form gate dielectric layer 21 and grid 22; Then, form dielectric layer, cover described grid 22, gate dielectric layer 21 and Semiconductor substrate 20, this dielectric layer can be also laminated construction for single layer structure, returns afterwards and carves this dielectric layer formation side wall 23.But in actual applications, be not limited to above-mentioned formation method.
In conjunction with reference to figure 6 and Fig. 9, execution step S3, Semiconductor substrate 20 described in etching forms the first groove 24 between described grid structure, and the width of described the first groove 24 bottoms is greater than the spacing between described grid structure.In embodiments of the present invention, adopt dry etching method to carry out etching to described Semiconductor substrate 20.Alternatively, the parameter of described dry etching is as follows: reacting gas comprises carbon tetrafluoride (Carbontetrafluoride, CF
4), chlorine (Cl
2), oxygen (O
2) and argon gas (Argon, Ar), wherein said CF
4gas flow be 10-200sccm (mark condition milliliter per minute standard-state cubiccentimeter per minute), described Cl
2gas flow be 10-200sccm, described O
2gas flow be that the gas flow of 10-50sccm, described Ar is 50-200sccm; Reaction time is 10 seconds-60 seconds; Reaction pressure is 10-100mTorr (millitorr); Bias voltage (Bias power) be 10-200W (watt); Transformer coupled plasma (transformer coupled plasma, TCP) power is 100-1000W.
It should be noted that, above-mentioned technological parameter is only to form the wider groove of bottom width for example, and in actual applications, the width of the first channel bottom can determine as required, corresponding, and dry etching forms the parameter of described the first groove also can be different.
Inventor finds through experiment, adopt the dry etching method of above-mentioned technological parameter to carry out after etching described Semiconductor substrate 20, the first groove 24 forming between described grid structure, owing to being provided with bias value in technological parameter, make reacting gas depart from the direction perpendicular to described Semiconductor substrate 20, the bottom width of described the first groove 24 forming is like this greater than the spacing (being similar to the top of described the first groove 24) of described grid structure; Further, equally due to bias value, reaction gas is known from experience described Semiconductor substrate 20 is produced to lateral etching, the sidewall of described the first groove 24 therefore forming is circular arc.It should be noted that, shown in Fig. 9 is only the schematic diagram of embodiment, and due to the variation of technological parameter, the first groove 24 of formation may be not limited to the shape shown in Fig. 9.
Compared with prior art, by changing the technological parameter of dry etching, especially be provided with bias value, make the bottom width of described the first groove 24 of forming be greater than the spacing of described grid structure, because the bottom of described the first groove 24 is wider, follow-up, described the first groove 24 is carried out to wet etching while forming the second groove like this, can avoid the bottom of the second groove because the etch rate of described the first groove 24 bottoms comparatively fast being made form to occur wedge angle phenomenon.
In conjunction with reference to figure 6 and Figure 10, execution step S4, described in etching the first groove 24 form the second grooves 24 '.In embodiments of the present invention, adopt wet etching method to continue etching to described the first groove 24, formation the second groove 24 '.Alternatively, the reaction solution of described wet etching comprises Tetramethylammonium hydroxide (Tetramethylammonium hydroxide, TMAH), and its concentration is 10%-40%; Reaction temperature is 60-90 degree Celsius.
Due in above-mentioned steps S3, the bottom of the first groove 24 forming by dry etching is wider.In this step, adopt wet etching method to continue etchings to described the first groove 24 and formed for second 24 ' time of groove, can avoid described the second groove 24 ' bottom produce wedge angle phenomenon.As well known to those skilled in the art, wet etching is the corrosion of isotropism chemistry, in all directions, with same speed, carry out etching, like this when the bottom of described the first groove 24 is wider, described the second groove 24 forming after etching ' there will not be wedge angle phenomenon.It should be noted that, shown in Figure 10 is only the schematic diagram of embodiment, the second groove 24 ' edge be similar to ∑ type, in actual process, form the second described groove 24 ' be not limited to shape shown in Figure 10.
In conjunction with Fig. 6 and Figure 11, execution step S5, in described the second groove 24 ' interior formation source region, drain region.In embodiments of the present invention, described source region, drain region form by deposit Germanium silicon.For example, by chemical vapour deposition technique (Chemical Vapor Deposition, CVD), at described the second groove 24 ' interior deposit Germanium silicon, form source region 25 (or drain region).The the second groove 24 ' interior bottom forming due to above-mentioned steps S4 does not have wedge angle phenomenon, therefore, the germanium silicon depositing in this step can fill up whole the second groove 24 ', form source region 25 (or drain region).
Further, this step can also well known to a person skilled in the art that technology realizes by other.For example, can pass through the method for molecular beam epitaxy (Molecular Beam Epitaxy, MBE) at described the second groove 24 ' interior growth germanium silicon, form source region 25 (or drain region).The method of described molecular beam epitaxy refers to Semiconductor substrate 20 is placed in ultra high vacuum cavity, needs the monocrystalline material (the present embodiment middle finger germanium and silicon) of growth to spray in stove by being difference placed on respectively of element.The molecular flow being ejected by each element that is heated to respectively relevant temperature grows the superlattice structure (the present embodiment middle finger germanium silicon) of several metabolies in described Semiconductor substrate 20.
It should be noted that, due in Figure 11, in described Semiconductor substrate 20, only show adjacent two grid structures and the source region 25 (or drain region) between two grid structures in Semiconductor substrate.But, in practical application, in Semiconductor substrate, conventionally can form a plurality of grid structures, in the Semiconductor substrate between adjacent grid structure, form source region, drain region.
One in the embodiment of the present invention changes in example, at described step S4: after described in etching, the first groove forms the second groove, also comprise step S5: form source region, drain region in described the second groove before, also comprise step: by reflux technique, described Semiconductor substrate is processed.
In the present embodiment, the reative cell of described reflux technique is reflow ovens, and the temperature range in described reflow ovens is at 800-850 degree Celsius.In conjunction with Figure 10, after reflux technique, raised the position of the described second groove 24 ' edge wedge angle in described Semiconductor substrate 20, make the follow-up better effects if at described the second groove 24 ' interior deposit Germanium silicon (SiGe).
The formation method of the MOS transistor providing according to the embodiment of the present invention, by changing the technological parameter of dry etching, especially by bias value is set, in Semiconductor substrate, can form the first groove that bottom width is greater than grid structure spacing, thereby avoided follow-up the first groove has been carried out to wet etching while forming the second groove, at described the second channel bottom, there is wedge angle phenomenon, make the follow-up germanium silicon depositing in the second groove can fill up whole the second groove, form source region, drain region, improved the device performance of MOS transistor.
The foregoing is only specific embodiments of the invention; in order to make those skilled in the art better understand spirit of the present invention; it is limited range that yet protection scope of the present invention not take the specific descriptions of this specific embodiment; any those skilled in the art is not within departing from the scope of spirit of the present invention; can make an amendment to specific embodiments of the invention, and not depart from protection scope of the present invention.
Claims (7)
1. a formation method for MOS transistor, is characterized in that, comprises the steps:
Semiconductor substrate is provided;
In described Semiconductor substrate, form grid structure;
Semiconductor substrate described in dry etching forms the first groove between described grid structure, and the width of described the first channel bottom is greater than the spacing between described grid structure, and the parameter of described dry etching is as follows: reacting gas comprises CF
4, Cl
2, O
2and Ar, wherein said CF
4gas flow be 10-200sccm, described Cl
2gas flow be 10-200sccm, described O
2gas flow be that the gas flow of 10-50sccm, described Ar is 50-200sccm; Reaction time is 10s-60s; Reaction pressure is 10-100mTorr; Bias voltage is 10-200W; Transformer coupled plasma power is 100-1000W;
Described in etching, the first groove forms the second groove;
In described the second groove, form source region, drain region.
2. the formation method of MOS transistor according to claim 1, is characterized in that, to form the method for the second groove be wet etching to the first groove described in etching.
3. the formation method of MOS transistor according to claim 2, is characterized in that, the reaction solution of described wet etching comprises Tetramethylammonium hydroxide, and its concentration is 10%-40%; Reaction temperature is 60-90 degree Celsius.
4. the formation method of MOS transistor according to claim 1, is characterized in that, described grid structure comprises the gate dielectric layer that is formed in described Semiconductor substrate, is formed at the grid on described gate dielectric layer and is formed at described grid side wall around.
5. the formation method of MOS transistor according to claim 1, is characterized in that, described source region, drain region form by deposit Germanium silicon.
6. the formation method of MOS transistor according to claim 1, is characterized in that, after the first groove forms the second groove described in etching, before forming source region, drain region, also comprises step in described the second groove:
By reflux technique, described Semiconductor substrate is processed.
7. the formation method of MOS transistor according to claim 6, is characterized in that, the reative cell of described reflux technique is reflow ovens, and the temperature range in described reflow ovens is at 800-850 degree Celsius.
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| CN104681441A (en) * | 2013-11-29 | 2015-06-03 | 中芯国际集成电路制造(上海)有限公司 | Method for preventing embedded germanium silicon top cap layer from etching pollution |
| CN109786335B (en) * | 2018-12-25 | 2021-07-06 | 惠科股份有限公司 | Preparation method of array substrate structure, array substrate and display panel |
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| US7951657B2 (en) * | 2009-05-21 | 2011-05-31 | International Business Machines Corporation | Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor |
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