CN103489830A - Method for manufacturing integrated circuit - Google Patents
Method for manufacturing integrated circuit Download PDFInfo
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- CN103489830A CN103489830A CN201210189838.0A CN201210189838A CN103489830A CN 103489830 A CN103489830 A CN 103489830A CN 201210189838 A CN201210189838 A CN 201210189838A CN 103489830 A CN103489830 A CN 103489830A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 86
- 239000004065 semiconductor Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 239000000203 mixture Substances 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 239000002019 doping agent Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000280 densification Methods 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 abstract 2
- 238000011165 process development Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 206010020843 Hyperthermia Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000036031 hyperthermia Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a method for manufacturing an integrated circuit and relates to the field of integrated circuit manufacture. The method can reduce the process difficulty and improve the flexibility of integrated circuit process development and integrated circuit design. The method for manufacturing an integrated circuit comprises the following steps: forming an N well and a P well on a substrate; sequentially forming a field oxide layer, a first polycrystalline silicon layer pattern and an insulating medium layer pattern respectively on field regions of the N well and the P well, wherein the first polycrystalline silicon layer pattern includes a lower electrode plate of a double polycrystalline silicon capacitor located on the field oxide layer, and a first polycrystalline silicon layer resistor; forming a gate oxide layer on active regions of the N well and the P well; forming a second polycrystalline silicon layer pattern on the gate oxide layer, the field oxide layer and the insulating medium layer pattern, wherein the second polycrystalline silicon layer pattern includes a polycrystalline silicon gate located on the gate oxide layer, a second polycrystalline silicon layer low-value resistor located on the field oxide layer, and an upper electrode plate of the double polycrystalline silicon capacitor located on the insulating medium layer; and forming a source and drain regions in the active regions.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, relate in particular to a kind of manufacture method of integrated circuit.
Background technology
Two polycrystalline integrated circuits are a kind of integrated circuits that include the element (as two polycrystalline electric capacity) be comprised of two-layer polysilicon.In traditional two polycrystalline integrated circuit preparation process, adopt the ground floor polysilicon to make metal-oxide semiconductor (MOS) (Metal-Oxide-Semiconductor in integrated circuit, MOS) bottom crown of pipe and two polycrystalline electric capacity, then make the insulating medium layer of two polycrystalline electric capacity, adopt again afterwards second layer polysilicon to make the top crown of two polycrystalline electric capacity.
But, when adopting said method to make two polycrystalline integrated circuit, the process of making the top crown of the insulating medium layer of two polycrystalline electric capacity and two polycrystalline electric capacity can exert an influence to parameter and the characteristic of the metal-oxide-semiconductor that completes before, therefore in practice is produced, precision control to metal-oxide-semiconductor requires high, technology difficulty is large, and the parameter of the metal-oxide-semiconductor in the metal-oxide-semiconductor of producing and the integrated circuit that does not comprise two polycrystalline elements and characteristic be difference to some extent, makes the difficulty increase of integrated circuit technology exploitation and integrated circuit (IC) design.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of integrated circuit, reduces technology difficulty, improves the flexibility of integrated circuit technology exploitation and integrated circuit (IC) design.
For solving the problems of the technologies described above, embodiments of the invention adopt following technical scheme:
A kind of manufacture method of integrated circuit comprises:
Form N trap and P trap on substrate; Form successively field oxide, the first polysilicon layer figure and dielectric layer pattern on the place of described N trap and described P trap; Form gate oxide on the active area of described N trap and described P trap;
On described gate oxide, described field oxide and described dielectric layer pattern, form the second polysilicon layer figure, described the second polysilicon layer figure comprises: be positioned at the polysilicon gate on described gate oxide, be positioned at the second polysilicon layer low resistance on described field oxide, be positioned at the top crown of the two polycrystalline electric capacity on described insulating medium layer;
Form source-drain area at described active area.
Described formation the first polysilicon layer figure comprises: form the bottom crown be positioned at the two polycrystalline electric capacity on described field oxide, be positioned at high value resistor and low resistance on described field oxide.
Form successively field oxide, the first polysilicon layer figure and dielectric layer pattern on the place of described N trap and described P trap; Forming gate oxide on the active area of described N trap and described P trap comprises:
Form field oxide and cover the sacrificial oxide layer on described N trap and P trap active area on described N trap and P trap;
Form polysilicon layer on described field oxide and sacrificial oxide layer;
Described polysilicon layer is adulterated, form low concentration doping zone and high-concentration dopant zone, described low concentration doping zone is used to form described high value resistor, and described high-concentration dopant zone is used to form bottom crown and the low resistance of described pair of polycrystalline electric capacity;
Form insulating medium layer on described polysilicon layer;
Form bottom crown, high value resistor, the low resistance of described pair of polycrystalline electric capacity by composition technique and be positioned at the described dielectric layer pattern on the bottom crown, high value resistor, low resistance of described pair of polycrystalline electric capacity on described field oxide;
Remove described sacrificial oxide layer, in described surfaces of active regions, generate gate oxide and described dielectric layer pattern carried out to the high temperature densification simultaneously.
The described insulating medium layer that forms on described polysilicon layer comprises:
Deposit silica coating on described polysilicon layer;
Deposit silicon nitride rete on described silica coating.
Described on described gate oxide, described field oxide and described dielectric layer pattern, form the second polysilicon layer figure and also comprise:
Form the top crown of two polycrystalline electric capacity on described dielectric layer pattern;
Form low resistance on described field oxide.
Described on described gate oxide and described dielectric layer pattern, form the second polysilicon layer figure and comprise:
Form polysilicon layer on described gate oxide and described dielectric layer pattern;
Described polysilicon layer is carried out to high-concentration dopant;
Form polysilicon gate by composition technique on described gate oxide, the while forms low resistance, forms the top crown of two polycrystalline electric capacity on described dielectric layer pattern on described field oxide.
The thickness of described silica coating is 100 to 400 dusts, and the thickness of described silicon nitride film layer is 100 to 400 dusts.
The described source-drain area at described active area formation metal-oxide-semiconductor comprises:
Utilize composition technique to form the described source-drain area of metal-oxide-semiconductor at described active area, and described high value resistor is adulterated simultaneously, form medium resistance.
The integrated circuit manufacture method that the embodiment of the present invention provides, just completed the making of two-layer polysilicon figure and insulating medium layer before the polysilicon gate of making metal-oxide-semiconductor and source-drain area, avoided making the processing step of polysilicon graphics and making insulating medium layer to the parameter of metal-oxide-semiconductor and the impact of performance generation, and parameter and the characteristic of the metal-oxide-semiconductor in the metal-oxide-semiconductor of producing and the integrated circuit that does not comprise two polycrystalline elements do not have difference, therefore, with respect to prior art, method provided by the invention has reduced technology difficulty, improve the flexibility of integrated circuit technology exploitation and integrated circuit (IC) design.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The method flow diagram that Fig. 1 provides for the embodiment of the present invention;
The method flow diagram that Fig. 2 is step 101 in the embodiment of the present invention;
Fig. 3 forms the schematic diagram of field oxide and sacrificial oxide layer in the embodiment of the present invention;
Fig. 4 forms the schematic diagram of the first polysilicon layer in the embodiment of the present invention;
Fig. 5 forms the schematic diagram of insulating medium layer in the embodiment of the present invention;
Fig. 6 forms the schematic diagram of the first polysilicon layer figure and dielectric layer pattern in the embodiment of the present invention;
Fig. 7 be in the embodiment of the present invention, form gate oxide and high temperature densification schematic diagram;
Fig. 8 forms the schematic diagram of the second polysilicon layer in the embodiment of the present invention;
Fig. 9 forms the schematic diagram of the second polysilicon layer figure in the embodiment of the present invention;
Figure 10 forms the schematic diagram of the source-drain area of metal-oxide-semiconductor in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of manufacture method of integrated circuit, and as shown in Figure 1, the method comprises:
101, form N trap and P trap on substrate; Form successively field oxide, the first polysilicon layer figure and dielectric layer pattern on the place of described N trap and described P trap, described the first polysilicon layer figure comprises: be positioned at bottom crown and the first polysilicon layer resistance of the two polycrystalline electric capacity on described field oxide, described the first polysilicon layer resistance comprises the first polysilicon layer low resistance and the first polysilicon layer high value resistor; Form gate oxide on the active area of described N trap and described P trap;
Concrete, the place of N trap and P trap and the position of active area and quantity can be selected according to the design of concrete integrated circuit.
The ground floor polysilicon graphics can comprise: the bottom crown of two polycrystalline electric capacity, and resistance or other polysilicon components, the concrete composition of ground floor polysilicon graphics is not done restriction here, in practice process, can specifically according to the design of integrated circuit, be selected.
102, on gate oxide, field oxide and dielectric layer pattern, form the second polysilicon layer figure, forming the second polysilicon layer figure comprises: be positioned at the polysilicon gate on described gate oxide, be positioned at the second polysilicon layer low resistance on described field oxide, be positioned at the top crown of the two polycrystalline electric capacity on described insulating medium layer;
Concrete, the second polysilicon layer figure can comprise: the top crown of two polycrystalline electric capacity, and resistance or other elements, the concrete composition of second layer polysilicon graphics is not done restriction here, in practice process, can specifically according to the design of integrated circuit, be selected.
103, form source-drain area at described active area.
The integrated circuit manufacture method that the embodiment of the present invention provides, just completed the making of two-layer polysilicon figure and insulating medium layer before the polysilicon gate of making metal-oxide-semiconductor and source-drain area, avoided making the processing step of polysilicon graphics and making insulating medium layer to the parameter of metal-oxide-semiconductor and the impact of performance generation, and parameter and the characteristic of the metal-oxide-semiconductor in the metal-oxide-semiconductor of producing and the integrated circuit that does not comprise two polycrystalline elements do not have difference, therefore, with respect to prior art, method provided by the invention has reduced technology difficulty, improve the flexibility of integrated circuit technology exploitation and integrated circuit (IC) design.
Optionally, in embodiment of the present invention step 101, form the first polysilicon layer figure and comprise: form the bottom crown be positioned at the two polycrystalline electric capacity on field oxide, be positioned at high value resistor and low resistance on field oxide.
Further, in embodiment of the present invention step 101, as shown in Figure 2, form successively field oxide, the first polysilicon layer figure and dielectric layer pattern on the place of described N trap and described P trap; Forming gate oxide on the active area of described N trap and described P trap comprises:
1011, as shown in Figure 3, form N trap 1 and P trap 2 on substrate 3, form field oxide 4 and cover the sacrificial oxide layer 5 on N trap 1 and P trap 2 active areas on N trap 1 and P trap 2; The position of the position of N trap and P trap and quantity and place and active area and quantity can be selected according to the design of concrete integrated circuit;
1012, as shown in Figure 4, form polysilicon layer 6 on field oxide 4 and sacrificial oxide layer 5, deposit one deck polysilicon on field oxide 4 and sacrificial oxide layer 5, form polysilicon layer 6;
1013, polysilicon layer 6 is adulterated, form low concentration doping zone and high-concentration dopant zone, in embodiments of the present invention, first polysilicon layer is carried out to light dope, and then by composition technique, high-concentration dopant is carried out in subregion to polysilicon layer, and the low concentration doping zone is used to form high value resistor, and the high-concentration dopant zone is used to form bottom crown and the low resistance of two polycrystalline electric capacity.
1014, as shown in Figure 5, form insulating medium layer on polysilicon layer 6; Further, forming insulating medium layer on polysilicon layer comprises:
Deposit silicon nitride rete 8 on silica coating 7; the thickness of silicon nitride film layer is preferably 100 to 400 dusts; deposit silicon nitride rete 8 as dielectric can after during the step of sacrificial oxide layer of rinsing surfaces of active regions; can protect silica coating not rinsed; can generate silicon oxynitride again simultaneously in the process close in hyperthermia induced, play the effect of dielectric.
1015, as shown in Figure 6, form bottom crown 9, high value resistor 11, the low resistance 10 of two polycrystalline electric capacity by composition technique on field oxide 4 and be positioned at the dielectric layer pattern 12 on the bottom crown, high value resistor, low resistance of two polycrystalline electric capacity;
1016, as shown in Figure 7, remove sacrificial oxide layer, generate gate oxide 13 and the dielectric layer pattern carried out to the high temperature densification simultaneously in surfaces of active regions, in embodiments of the present invention, first rinse the sacrificial oxide layer of surfaces of active regions, then surface-mounted integrated circuit is carried out to the high temperature densification, in high temperature, the sidewall of the first polysilicon layer figure (as high value resistor 11) forms silica coating 7 through high-temperature oxydation, the silicon nitride film layer 8 be positioned on former upper surface dioxide layer rete 7 forms one deck silicon oxynitride 14 through high-temperature oxydation on surface and sidewall, surfaces of active regions forms gate oxide 13 simultaneously.The present invention is a step by the fine and close Process fusion of the high temperature of the formation of gate oxide and insulating medium layer, realize the high temperature densification of insulating medium layer and the formation of gate oxide by once heating high temperature simultaneously, shorten production stage with respect to prior art, improved production efficiency.
Optionally, in embodiments of the present invention, described on gate oxide and dielectric layer pattern, form the second polysilicon layer figure and also comprise:
Form the top crown of two polycrystalline electric capacity on the dielectric layer pattern;
Form low resistance on field oxide.
Further, in embodiments of the present invention, on gate oxide and dielectric layer pattern, form the second polysilicon layer figure and comprise:
As shown in Figure 8, deposit one deck polysilicon on gate oxide 13 and dielectric layer pattern 12, form polysilicon layer 15;
Polysilicon layer 15 is carried out to high-concentration dopant;
As shown in Figure 9, form polysilicon gate 16 by composition technique on gate oxide, the while forms low resistance 18, forms the top crown 17 of two polycrystalline electric capacity on dielectric layer pattern 12 on field oxide.
Further, in embodiments of the present invention, as shown in figure 10, the source-drain area that forms metal-oxide-semiconductor at active area comprises:
Utilize composition technique to form the source-drain area of metal-oxide-semiconductor at active area, and high value resistor is adulterated simultaneously, form medium resistance.By composition technique, active area is carried out to Implantation, form the source-drain area 19 of metal-oxide-semiconductor; Optionally, utilize this composition technique again the high value resistor formed to be carried out to the primary ions injection simultaneously, form medium resistance, medium resistance and source-drain area are used same mask plate to form, do not add any cost and just can complete the preparation of medium resistance, reduced processing step, reduced cost.
The integrated circuit manufacture method that the embodiment of the present invention provides, just completed the making of two-layer polysilicon figure and insulating medium layer before the polysilicon gate of making metal-oxide-semiconductor and source-drain area, avoided making the processing step of polysilicon graphics and making insulating medium layer to the parameter of metal-oxide-semiconductor and the impact of performance generation, and parameter and the characteristic of the metal-oxide-semiconductor in the metal-oxide-semiconductor of producing and the integrated circuit that does not comprise two polycrystalline elements do not have difference, therefore, with respect to prior art, method provided by the invention has reduced technology difficulty, improve the flexibility of integrated circuit technology exploitation and integrated circuit (IC) design.And, the present invention is a step by the fine and close Process fusion of the high temperature of the formation of gate oxide and insulating medium layer, realize the high temperature densification of insulating medium layer and the formation of gate oxide by once heating high temperature simultaneously, shortened production stage with respect to prior art, improved production efficiency, method provided by the invention can utilize homogeneous composition technique again the high value resistor formed to be carried out to the primary ions injection when forming source-drain area, form medium resistance, do not add any cost and just can complete the preparation of medium resistance, further improved production efficiency, reduced cost.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (6)
1. the manufacture method of an integrated circuit, is characterized in that, comprising:
Form N trap and P trap on substrate;
Form successively field oxide, the first polysilicon layer figure and dielectric layer pattern on the place of described N trap and described P trap, described the first polysilicon layer figure comprises: be positioned at bottom crown and the first polysilicon layer resistance of the two polycrystalline electric capacity on described field oxide, described the first polysilicon layer resistance comprises the first polysilicon layer low resistance and the first polysilicon layer high value resistor;
Form gate oxide on the active area of described N trap and described P trap;
On described gate oxide, described field oxide and described dielectric layer pattern, form the second polysilicon layer figure, described the second polysilicon layer figure comprises: be positioned at the polysilicon gate on described gate oxide, be positioned at the second polysilicon layer low resistance on described field oxide, be positioned at the top crown of the two polycrystalline electric capacity on described insulating medium layer;
Form source-drain area at described active area.
2. method according to claim 1, is characterized in that, forms successively field oxide, the first polysilicon layer figure and dielectric layer pattern on the place of described N trap and described P trap; Forming gate oxide on the active area of described N trap and described P trap comprises:
Form field oxide and cover the sacrificial oxide layer on described N trap and P trap active area on described N trap and P trap;
Form polysilicon layer on described field oxide and sacrificial oxide layer;
Described polysilicon layer is adulterated, form low concentration doping zone and high-concentration dopant zone, described low concentration doping zone is used to form described high value resistor, and described high-concentration dopant zone is used to form bottom crown and the low resistance of described pair of polycrystalline electric capacity;
Form insulating medium layer on described polysilicon layer;
Form bottom crown, high value resistor, the low resistance of described pair of polycrystalline electric capacity by composition technique and be positioned at the described dielectric layer pattern on the bottom crown, high value resistor, low resistance of described pair of polycrystalline electric capacity on described field oxide;
Remove described sacrificial oxide layer, in described surfaces of active regions, generate gate oxide and described dielectric layer pattern carried out to the high temperature densification simultaneously.
3. method according to claim 2, is characterized in that, the described insulating medium layer that forms on described polysilicon layer comprises:
Deposit silica coating on described polysilicon layer;
Deposit silicon nitride rete on described silica coating.
4. method according to claim 1, is characterized in that, described on described gate oxide, described field oxide and described dielectric layer pattern, forms the second polysilicon layer figure and comprise:
Form polysilicon layer on described gate oxide, described field oxide and described dielectric layer pattern;
Described polysilicon layer is carried out to high-concentration dopant;
Form polysilicon gate by composition technique on described gate oxide, the while forms low resistance, forms the top crown of two polycrystalline electric capacity on described dielectric layer pattern on described field oxide.
5. method according to claim 3, is characterized in that, the thickness of described silica coating is 100 to 400 dusts, and the thickness of described silicon nitride film layer is 100 to 400 dusts.
6. method according to claim 1, is characterized in that, the described source-drain area at described active area formation metal-oxide-semiconductor comprises:
Utilize composition technique to form the described source-drain area of metal-oxide-semiconductor at described active area, and described high value resistor is adulterated simultaneously, form medium resistance.
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| CN106298981A (en) * | 2016-08-16 | 2017-01-04 | 中国电子科技集团公司第二十四研究所 | The double polycrystalline capacitance structures integrated with metal-oxide-semiconductor and manufacture method |
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| CN114093866A (en) * | 2021-11-19 | 2022-02-25 | 陕西亚成微电子股份有限公司 | MOSFET structure of integrated starting device and manufacturing method |
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| CN105575899A (en) * | 2014-10-30 | 2016-05-11 | 台湾积体电路制造股份有限公司 | Equal gate height control method for semiconductor device with different pattern densities |
| CN105575899B (en) * | 2014-10-30 | 2018-10-23 | 台湾积体电路制造股份有限公司 | Equal gate heights control method for the semiconductor devices with different pattern density |
| CN107464852A (en) * | 2016-06-02 | 2017-12-12 | 北大方正集团有限公司 | IC-components of integrated super-pressure resistance and preparation method thereof |
| CN106298981A (en) * | 2016-08-16 | 2017-01-04 | 中国电子科技集团公司第二十四研究所 | The double polycrystalline capacitance structures integrated with metal-oxide-semiconductor and manufacture method |
| CN114093866A (en) * | 2021-11-19 | 2022-02-25 | 陕西亚成微电子股份有限公司 | MOSFET structure of integrated starting device and manufacturing method |
| CN114093866B (en) * | 2021-11-19 | 2023-03-14 | 陕西亚成微电子股份有限公司 | MOSFET structure of integrated starting device and manufacturing method |
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