CN100349284C - Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit - Google Patents

Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit Download PDF

Info

Publication number
CN100349284C
CN100349284C CNB2004100537234A CN200410053723A CN100349284C CN 100349284 C CN100349284 C CN 100349284C CN B2004100537234 A CNB2004100537234 A CN B2004100537234A CN 200410053723 A CN200410053723 A CN 200410053723A CN 100349284 C CN100349284 C CN 100349284C
Authority
CN
China
Prior art keywords
trap
well
ion
nmos
dark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2004100537234A
Other languages
Chinese (zh)
Other versions
CN1734748A (en
Inventor
乔琼华
邵凯
龚大卫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHANGHAI XIANJIN SEMICONDUCTOR MANUFACTURING Co Ltd
Original Assignee
SHANGHAI XIANJIN SEMICONDUCTOR MANUFACTURING Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHANGHAI XIANJIN SEMICONDUCTOR MANUFACTURING Co Ltd filed Critical SHANGHAI XIANJIN SEMICONDUCTOR MANUFACTURING Co Ltd
Priority to CNB2004100537234A priority Critical patent/CN100349284C/en
Publication of CN1734748A publication Critical patent/CN1734748A/en
Application granted granted Critical
Publication of CN100349284C publication Critical patent/CN100349284C/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The present invention discloses an improved process for manufacturing a BICMOS integrated circuit of 0.8 micrometer. A DP well is formed in an N well, and the process specifically comprises the following steps that the N well and a P well are formed on a P-type substrate by ion implantation and a thermal propulsion process; the DP well is formed in the N well, a DP well region is firstly defined by photoresist, and the DP well is formed by ion implantation; a plurality of isolation regions are formed by an LOCOS process, an active region is formed, and the position of insolation regions is in conformity with the position of the formed wells; a gate oxide layer and a capacitor element are manufactured, wherein the gate oxide layer of a high-voltage device and that of a low-voltage device are completed in the same oxidation step; a CMOS device and a bipolar device are manufactured, wherein an isolation NMOS device and a bipolar NPN device are formed on the N well provided with the DP well; a connecting line between metal layers and a passivation layer are manufactured. The present invention has the advantages of simple flow and low cost. When a BICMOS device with good performance is manufactured, the process flow is more reasonable.

Description

0.8 micron silicon bipolar complementary metal oxide semiconductor integrated circuit fabrication process
Technical field
The present invention relates to the manufacturing process of silicon bipolar complementary metal oxide semiconductor (BICMOS) integrated circuit, more particularly, relate to a kind of 0.8 micron manufacturing process of BICMOS integrated circuit.
Background technology
What mainly use in the integrated circuit at present is cmos device and bipolar device, these two kinds of devices have advantage and limitation separately, cmos device has the advantage that device power consumption is low, integrated level is high and antijamming capability is strong, and the device operating rate is low, the shortcoming of driving force difference but also have.The advantage that the bipolar device device speed is fast, driving force is strong, simulation precision is high, but the device power consumption height is also arranged, the shortcoming that integrated level is low.From the above mentioned, the pluses and minuses that can see CMOS and bipolar device are just in time complementary, so, a kind of CMOS and ambipolar two kinds of semiconductor device be produced on simultaneously on the same chip technology---BiCMOS is development therefore, to satisfy the demand for development of industry toward high speed, high integration, high performance LSI and VLSI.
The basic demand of BiCMOS technology is with needing " at a high speed " and " current drives " part in the entire circuit, to handle with ambipolar with two kinds of combination of devices to same chip, as the I/O part (I/O) of circuit; And with " high integrated " " low-power consumption " zone in the circuit, as array, make with CMOS, the chip that obtains thus has good comprehensive performances, but making Bi-CMOS needs to add bipolar device in the circuit that original CMOS is a design agents, existing Bi-CMOS technology will be than simple CMOS complex process, and cost also can improve.Especially when the device of making 0.8 micron, it is especially obvious that this defective seems.
Therefore, just need a kind of improved technological process, the technological process of the manufacturing BiCMOS device that makes obtains simplifying, and cost reduces.When having the BiCMOS device of superperformance, manufacturing make technological process also more reasonable.
Summary of the invention
At technological process complexity in the prior art, defect of high cost the purpose of this invention is to provide a kind of manufacturing process of improved 0.8 micron BICMOS integrated circuit, simplifies technological process, reduces the cost of technology.
According to the present invention, a kind of improved 0.8 micron BICMOS integrated circuit fabrication process is provided, in the N trap, form dark P type trap, specifically comprise following step: on P type substrate, use the ion injection and pick into technology formation N trap and P trap; In the N trap, form dark P type trap, at first make to define dark P type well area with photoresist, re-use ion and inject the dark P type trap of formation; Adopt LOCOS technology to form a plurality of area of isolation and be formed with the source region, described area of isolation conforms to the position of the trap of formation; Manufacturing gate oxide layers and capacitor element; Wherein, the gate oxide of described high tension apparatus and low-voltage device is finished with in an oxidation step; Make cmos device and bipolar device; Wherein, on described N trap with dark P type trap, form and isolate nmos device and ambipolar NPN device; Make metal interlevel line and passivation layer.
According to one embodiment of the present of invention, in above-mentioned step, can adopt following concrete technological process, wherein:
The step of described formation N trap and P trap specifically comprises: first oxygen; Make and carry out N well area and P trap location with photoresist; N trap ion injects; P trap ion injects; Two traps advance.
The step that described employing LOCOS technology forms a plurality of area of isolation and is formed with the source region specifically comprises: basic oxygen; Lay lpcvd silicon nitride; Carry out the active area photoetching; The place ion injects; The field oxidation; Remove silicon nitride and oxide skin(coating).
The step of described manufacturing gate oxide layers and capacitor element specifically comprises: pre-grid oxygen; Ion is regulated and is injected; Gate oxidation; First polysilicon layer deposition; First polysilicon layer mixes; The first polysilicon layer etching; Capping oxidation layer deposition; Second polysilicon layer deposition; Second polysilicon layer mixes; The second polysilicon layer etching.
The step of described making cmos device and bipolar device specifically comprises: the photoetching of NMOS LDD structure; NMOS LDD structure ion injects; The annealing of NMOS LDD structure; The photoetching of PMOS LDD structure; PMOS LDD structure ion injects, the annealing of PMOS LDD structure; The TEOS deposition; The gasket construction etching; The photoetching of nmos area territory; Nmos area territory ion injects; PMOS zone photoetching; PMOS zone ion injects; The BPSG deposition is also fine and close; Contact hole photoetching and etching.
According to one embodiment of present invention, in the step of the dark P type of described formation trap, the ion of injection is B 11+Ion.
Adopt technical scheme of the present invention, the technology of making BICMOS becomes only to increase by two steps than typical logical integrated circuit cmos process flow, just can obtain double level polysilicon electric capacity (PIPCAPACITOR), and high value, highly reliable polysilicon resistance (HIGH VALUERESISTOR).These two all is passive device commonly used in the Analog Circuit Design.In addition, add a P type knot and form DP shape trap in the N trap, can obtain three extraordinary devices simultaneously: 1) HVMOS, P type layer can be used as the high pressure extension layer in the drain region of LDMOS, makes it can be operated in the above zone of 20V.2) vertical-type NPN (VERTICAL NPN): P type layer can be used as the base of VNPN, and the bipolar device of this high pressure has high-gain simultaneously.3) Jue Yuan NMOS:P type layer can be used as the NMOS substrate of insulation, and the N trap is thoroughly isolated itself and silicon substrate.The NMOS of insulation has good low noise function.Five above devices are compatible mutually with the CMOS logical circuit fully, can keep the SPICE MODEL of CMOS not change, and do not increase complicated especially technology again.
Description of drawings
Essence of the present invention and advantage will become more obvious after the description to embodiment below in conjunction with the accompanying drawings, wherein:
Fig. 1 is the process chart according to one embodiment of the present of invention;
Fig. 2 is the concrete process chart of making according to two traps of one embodiment of the present of invention;
Fig. 3 is the dark P type well structure schematic diagram according to one embodiment of the present of invention;
Fig. 4 is that the employing LOCOS technology according to one embodiment of the present of invention forms a plurality of area of isolation and is formed with the flow chart in source region;
Fig. 5 is the structural representation after the described step of Fig. 4 is finished;
Fig. 6 is according to the manufacturing gate oxide layers of one embodiment of the present of invention and the flow chart of capacitor element;
Fig. 7 is the structural representation after the described step of Fig. 6 is finished;
Fig. 8 implements the sharp making cmos device and the flow chart of bipolar device according to one of the present invention;
Fig. 9 is the structural representation after technological process of the present invention is finished.
Embodiment
Further specify technical scheme of the present invention below in conjunction with embodiment.
The flow process of manufacturing process of the present invention is as follows, and with reference to figure 1, wherein main characteristics is also to form dark P type trap in the N trap; The gate oxide of high tension apparatus and low-voltage device is finished with in an oxidation step; And nmos device and ambipolar NPN device are isolated in formation on the N trap with dark P type trap.
As shown in Figure 1, this flow process comprises following step:
S11. on P type substrate, use the ion injection and pick into technology formation N trap and P trap.In this embodiment, the step of the two traps of this making specifically comprises: first oxygen; Make and carry out N well area and P trap location with photoresist; N trap ion injects; P trap ion injects; Two traps advance.Above-mentioned steps is with reference to figure 2, and these steps are identical with general COMS twin well process.
S12. in the N trap, form dark P type trap, at first make to define dark P type well area with photoresist, re-use ion and inject the dark P type trap of formation.Finish dark P type trap and inject device architecture figure afterwards as shown in Figure 3.Wherein, have in two N traps the ion of injection form dark P type trap, in this embodiment, then two N traps with dark P type trap will be used to make and isolate nmos device and ambipolar NPN device.And the ion that injects when forming dark P type trap is B 11+Ion.
S13. adopt LOCOS technology to form a plurality of area of isolation and be formed with the source region, area of isolation conforms to the position of the trap of formation.In this was implemented, this step specifically comprised: basic oxygen; Lay lpcvd silicon nitride; Carry out the active area photoetching; The place ion injects; The field oxidation; Remove silicon nitride and oxide skin(coating), with reference to figure 4.And the structural representation of Fig. 5 described step that is Fig. 4 after finishing.As shown in Figure 5, after this step is finished, isolation by field oxide 120 has formed a plurality of isolated areas 100,102,104,106,108 and 110, in this embodiment, they are used to make different devices, and wherein 100 is ambipolar NPN devices, the 102nd, low pressure nmos device, the 104th, and high pressure NMOS part, the 106th is isolated nmos device, the 108th, PMOS device, the 110th, electric capacity.After this step is finished, also formed a first oxygen layer 112 in each region surface that is used to make device.
S14. manufacturing gate oxide layers and capacitor element; Wherein, the gate oxide of high tension apparatus and low-voltage device is finished with in an oxidation step.In this embodiment, specifically comprise the steps,, comprising: pre-grid oxygen with reference to figure 6; Vt regulates injection; Gate oxidation; First polysilicon layer (Poly1) deposition; First polysilicon layer mixes; The first polysilicon layer etching; Capping oxidation layer deposition; Second polysilicon layer (Poly2) deposition; Second polysilicon layer mixes; The second polysilicon layer etching.After this step was finished, its structure as shown in Figure 7.First polysilicon layer 114 is being used as low pressure NMOS102, high pressure NMOS 104, the grid of isolating NMOS106, PMOS108 and the bottom electrode of electric capacity 110 after etching.It should be noted that in high pressure NMOS 106 some has covered field oxide first polysilicon layer 114.For electric capacity 110, also need second polysilicon layer 118 to come, and between upper/lower electrode, also need capping oxidation layer (TEOS oxide layer) 116 to isolate as its top electrode.That is to say that in aforesaid step, except the position of electric capacity 110, other zones all will be etched away after laying for the capping oxidation layer 116 and second polysilicon layer 118.
S15. make cmos device and bipolar device; Wherein, on N trap, form isolation nmos device and ambipolar NPN device with dark P type trap.In this embodiment, specifically comprise, as shown in Figure 8: the photoetching of NMOS LDD structure; NMOS LDD structure ion injects; The annealing of NMOSLDD structure; The photoetching of PMOS LDD structure; PMOS LDD structure ion injects, the annealing of PMOSLDD structure; The TEOS deposition; Gasket construction (spacer) etching; The photoetching of nmos area territory; Nmos area territory ion injects; PMOS zone photoetching; PMOS zone ion injects; The BPSG deposition is also fine and close; Contact hole photoetching and etching.Most technology is identical with conventional art in this step, and distinguishing to be exactly making when isolating NMOS and ambipolar NPN device be to have on the N trap of dark P type trap to carry out.
S16. make metal interlevel line and passivation layer, this step is identical with tradition, has just no longer described here.
After adopting technical scheme of the present invention, only increase by two steps and just can obtain double level polysilicon electric capacity (PIP CAPACITOR) than typical logical integrated circuit cmos process flow, and high value, highly reliable polysilicon resistance (HIGH VALUE RESISTOR).These two all is passive device commonly used in the Analog Circuit Design.In addition, add a P type knot and form DP shape trap in the N trap, can obtain three extraordinary devices: 1) HVMOS, its P type layer can be used as the high pressure extension layer in the drain region of LDMOS, makes it can be operated in the above zone of 20V.2) vertical-type NPN (VERTICAL NPN): P type layer can be used as the base of VNPN, and the bipolar device of this high pressure has high-gain simultaneously.3) Jue Yuan NMOS:P type layer can be used as the NMOS substrate of insulation, and the N trap is thoroughly isolated itself and silicon substrate.The NMOS of insulation has good low noise function.Five above devices are compatible mutually with the CMOS logical circuit fully, can keep the SPICE MODEL of CMOS not change, and do not increase complicated especially technology again.
The foregoing description provides to being familiar with the person in the art and realizes or use of the present invention; those skilled in the art can be under the situation that does not break away from invention thought of the present invention; the foregoing description is made various modifications or variation; thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.

Claims (6)

1. improved 0.8 micron BICMOS integrated circuit fabrication process is characterized in that, forms dark P type trap in the N trap, specifically comprises following step:
On P type substrate, use the ion injection and pick into technology formation N trap and P trap;
In the N trap, form dark P type trap, at first make to define dark P type well area with photoresist, re-use ion and inject the dark P type trap of formation;
Adopt LOCOS technology to form a plurality of area of isolation and be formed with the source region, described area of isolation conforms to the position of the trap of formation;
Manufacturing gate oxide layers and capacitor element; Wherein, the gate oxide of high tension apparatus and low-voltage device is finished with in an oxidation step;
Make cmos device and bipolar device; Wherein, on described N trap with dark P type trap, form and isolate nmos device and ambipolar NPN device;
Make metal interlevel line and passivation layer.
2. manufacturing process as claimed in claim 1 is characterized in that, the step of described formation N trap and P trap specifically comprises:
First oxygen; Make and carry out N well area and P trap location with photoresist; N trap ion injects; P trap ion injects; Two traps advance.
3. will go 1 described manufacturing process as right, it is characterized in that, the step that described employing LOCOS technology forms a plurality of area of isolation and is formed with the source region specifically comprises:
Base oxygen; Lay lpcvd silicon nitride; Carry out the active area photoetching; The place ion injects; The field oxidation; Remove silicon nitride and oxide skin(coating).
4. manufacturing process as claimed in claim 1 is characterized in that, the step of described manufacturing gate oxide layers and capacitor element specifically comprises:
Pre-grid oxygen; Ion is regulated and is injected; Gate oxidation; First polysilicon layer deposition; First polysilicon layer mixes; The first polysilicon layer etching; Capping oxidation layer deposition; Second polysilicon layer deposition; Second polysilicon layer mixes; The second polysilicon layer etching.
5. manufacturing process as claimed in claim 1 is characterized in that, the step of described making cmos device and bipolar device specifically comprises:
The photoetching of NMOS LDD structure; NMOS LDD structure ion injects; The annealing of NMOS LDD structure; The photoetching of PMOS LDD structure; PMOS LDD structure ion injects, the annealing of PMOS LDD structure; The TEOS deposition; The gasket construction etching; The photoetching of nmos area territory; Nmos area territory ion injects; PMOS zone photoetching; PMOS zone ion injects; The BPSG deposition is also fine and close; Contact hole photoetching and etching.
6. manufacturing process as claimed in claim 1 is characterized in that, in the step of the dark P type of described formation trap, the ion of injection is B 11+Ion.
CNB2004100537234A 2004-08-13 2004-08-13 Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit Active CN100349284C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2004100537234A CN100349284C (en) 2004-08-13 2004-08-13 Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2004100537234A CN100349284C (en) 2004-08-13 2004-08-13 Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit

Publications (2)

Publication Number Publication Date
CN1734748A CN1734748A (en) 2006-02-15
CN100349284C true CN100349284C (en) 2007-11-14

Family

ID=36077051

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100537234A Active CN100349284C (en) 2004-08-13 2004-08-13 Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit

Country Status (1)

Country Link
CN (1) CN100349284C (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101373770B (en) * 2007-08-20 2011-10-05 天津南大强芯半导体芯片设计有限公司 Chip substrate electric potential isolating circuit and use thereof, and method for using the same
CN102122659B (en) * 2011-01-17 2016-02-03 上海华虹宏力半导体制造有限公司 Bipolar complementary metal oxide semiconductor device and preparation method thereof
CN102184897B (en) * 2011-03-28 2013-11-06 上海贝岭股份有限公司 Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855244A (en) * 1987-07-02 1989-08-08 Texas Instruments Incorporated Method of making vertical PNP transistor in merged bipolar/CMOS technology
US5374569A (en) * 1992-09-21 1994-12-20 Siliconix Incorporated Method for forming a BiCDMOS
CN1217575A (en) * 1997-11-06 1999-05-26 日本电气株式会社 Method for producing BiCMOS semiconductor device
US6171894B1 (en) * 1998-11-30 2001-01-09 Stmicroelectronics S.A. Method of manufacturing BICMOS integrated circuits on a conventional CMOS substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855244A (en) * 1987-07-02 1989-08-08 Texas Instruments Incorporated Method of making vertical PNP transistor in merged bipolar/CMOS technology
US5374569A (en) * 1992-09-21 1994-12-20 Siliconix Incorporated Method for forming a BiCDMOS
CN1217575A (en) * 1997-11-06 1999-05-26 日本电气株式会社 Method for producing BiCMOS semiconductor device
US6171894B1 (en) * 1998-11-30 2001-01-09 Stmicroelectronics S.A. Method of manufacturing BICMOS integrated circuits on a conventional CMOS substrate

Also Published As

Publication number Publication date
CN1734748A (en) 2006-02-15

Similar Documents

Publication Publication Date Title
US6207484B1 (en) Method for fabricating BiCDMOS device and BiCDMOS device fabricated by the same
JP3974205B2 (en) Manufacturing method of semiconductor device
US7456069B2 (en) Method in the fabrication of an integrated injection logic circuit
US20080217653A1 (en) Method of Manufacturing a Semiconductor Device with an Isolation Region and a Device Manufactured by the Method
US8575691B2 (en) Lateral-diffusion metal-oxide semiconductor device
JPH07202051A (en) Gate control type lateral bipolar junction transistor and manufacture thereof
CN101211849B (en) Semiconductor device capacitor fabrication method
US7772652B2 (en) Semiconductor component arrangement having a first and second region
CN1332424C (en) Method of fabricating a polysilicon capacitor utilizing FET and bipolar base polysilicon layers
CN103022006A (en) Epitaxy technology based three-dimensional integrated power semiconductor and manufacturing method thereof
CN104377244A (en) Device structure lowering LDMOS on resistance
US20090039460A1 (en) Deep trench isolation structures in integrated semiconductor devices
CN108010903B (en) MOS capacitor structure for reducing capacitance change
JP3783156B2 (en) Semiconductor device
CN205845961U (en) Integrated circuit
JPH10214907A (en) Semiconductor device and its manufacture
CN102867827A (en) Integrated circuit device
CN100349284C (en) Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit
CN101393890A (en) Fabrication method for high-voltage BCD device
KR100954919B1 (en) Inductor for semiconductor device and method for fabricating the same
CN101521213A (en) High breakdown voltage semiconductor integrated circuit device and dielectric separation type semiconductor device
CN103489830A (en) Method for manufacturing integrated circuit
KR101206628B1 (en) Thick oxide region in a semiconductor device and method of forming same
CN105449007A (en) Overlapping capacitor and manufacturing method thereof
CN103094329A (en) Germanium-silicon heterojunction bipolar transistor (HBT) component provided with deep burying layers and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant