CN102184897B - Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit - Google Patents

Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit Download PDF

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CN102184897B
CN102184897B CN 201110076175 CN201110076175A CN102184897B CN 102184897 B CN102184897 B CN 102184897B CN 201110076175 CN201110076175 CN 201110076175 CN 201110076175 A CN201110076175 A CN 201110076175A CN 102184897 B CN102184897 B CN 102184897B
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oxide
process
circuit
dbicmos
diffused
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CN 201110076175
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CN102184897A (en )
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聂纪平
谢玉森
张勇
刘亿
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上海贝岭股份有限公司
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Abstract

本发明涉及一种DBICMOS集成电路制造工艺,该制造工艺包括N阱制作步骤、有源区制作步骤、P型场区制作步骤、多晶制作步骤、N型区制作步骤、P型区制作步骤、接触孔制作步骤、铝线制作步骤和钝化层制作步骤,所述制造工艺还包括在所述P型场区制作步骤之后的基区制作步骤和电容制作步骤以及在所述多晶制作步骤之后的N型Ldd制作步骤。 The present invention relates to a DBICMOS integrated circuit manufacturing process, the manufacturing process comprises a N-well forming step, the step of making the active region, P-type field region production step, a polycrystalline manufacturing steps, the step of making N-type region, P-type region production step, a contact hole making step, the step of making aluminum production step and the passivation layer, the manufacturing process further comprises the step of making the base region and a capacitor fabrication steps following the step of making the field region and the P-type after the step of making the polycrystalline N-type Ldd production steps. 本发明通过增加电容制作步骤将多晶电容优化为MOS电容,提高了产品的设计精度;同时,通过增加基区制作步骤和N型Ldd制作步骤,实现了双极和DMOS结构的制作;另外,还通过调节N型区的浓度进一步优化了电路性能。 The present invention is polycrystalline capacitor capacitance by increasing manufacturing steps will optimize for the MOS capacitors, designed to improve the accuracy of the product; the same time, increasing the manufacturing steps and the N-type base region Ldd production steps, to achieve the production of bipolar and DMOS structure; Further, further optimize circuit performance by adjusting the concentration of the N-type region.

Description

—种DBICMOS集成电路制造工艺 - kind of integrated circuit manufacturing process DBICMOS

技术领域 FIELD

[0001] 本发明涉及一种DBICMOS(扩散型互补金属氧化物、双极和互补金属氧化物半导体)集成电路制造工艺。 [0001] The present invention relates to a DBICMOS (complementary metal oxide diffusion, bipolar and complementary metal oxide semiconductor) integrated circuit manufacturing process.

背景技术 Background technique

[0002] 当前的DBICMOS电路的制造一般是采用通用的集成电路制造工艺,然而这种常规的工艺应用在DBICMOS电路时,造成了以下的不便: [0002] Production DBICMOS current circuit is generally used a common integrated circuit manufacturing process, however, such a conventional process applied when DBICMOS circuit causes the following inconvenience:

[0003] 首先,为了考虑各种工艺特点,电路要求光刻层次太多; [0003] First, to consider the characteristics of the process, a photolithography circuit requires too many levels;

[0004] 其次,电路特性由于工艺的限制较为固定,对设计造成了很大困难; [0004] Next, circuit characteristics due to the limitation of the process relatively fixed, the design has caused great difficulties;

[0005] 第三,当前的DBICMOS很难实现器件设计高压的要求。 [0005] Third, the current DBICMOS device design is difficult to achieve high-pressure requirements.

[0006] 因此,针对上述情况,现在迫切需要开发一种适用于DBICMOS集成电路的制造工艺。 [0006] Accordingly, for the above, there is an urgent need to develop a process for the manufacture of integrated circuits DBICMOS.

发明内容 SUMMARY

[0007] 为了解决上述现有技术存在的问题,本发明旨在提供一种基于CMOS平台的DBICMOS集成电路制造工艺,以通过优化的工艺设计满足DBICMOS集成电路制造过程中特定的工艺和设计要求。 [0007] In order to solve the prior art problems, the present invention aims to provide DBICMOS CMOS integrated circuit manufacturing process based on the platform to meet DBICMOS integrated circuit manufacturing process and design requirements of a particular process by optimizing the process design.

[0008] 本发明所述的一种DBICMOS集成电路制造工艺,该制造工艺包括N阱制作步骤、有源区制作步骤、P型场区制作步骤、多晶制作步骤、N型区制作步骤、P型区制作步骤、接触孔制作步骤、铝线制作步骤和钝化层制作步骤,所述制造工艺还包括在所述P型场区制作步骤之后的基区制作步骤和电容制作步骤以及在所述多晶制作步骤之后的N型Ldd制作步骤。 [0008] A DBICMOS integrated circuit fabrication process of the present invention, the manufacturing process comprises N-well forming step, the step of making the active region, the step of making a P-type field region polycrystalline production step, the step of making the N-type region, P production step type region, the contact hole making step, the step of making aluminum production step and the passivation layer, the manufacturing process further comprises the step of making the base region and a capacitor fabrication steps following the step of making the P-type field in the region and N-type polycrystalline Ldd production step after manufacturing steps.

[0009] 在上述的DBICMOS集成电路制造工艺中,所述基区制作步骤是先光刻形成基区的光刻区域,然后在该光刻区域内进行硼注入,且硼注入时的能量为32.5keV,注入的剂量范围为4.5E13-5.5E13,随后在1100°C的温度下,对该光刻区域进行高温推进,以形成基区,且推进的时间范围为20-30min。 [0009] In the DBICMOS integrated circuit fabrication process, the first step is to create the base region is formed by photolithography lithographic base region, followed by boron implantation region in the photolithography, and the boron implantation energy of 32.5 keV, implantation dose ranging 4.5E13-5.5E13, and then at a temperature of 1100 ° C, the high temperature region to promote the photolithography, to form a base region and the advancing time is 20-30min.

[0010] 在上述的DBICMOS集成电路制造工艺中,所述电容制作步骤是先光刻形成电容区,然后在该电容区生长栅氧化层,以形成MOS电容,再对所述电容区调节注入硼,且硼注入时的能量为40keV,注入的剂量范围为5.5E11-5.7E11,以形成DBICMOS开启电压。 [0010] In the DBICMOS integrated circuit fabrication process, the first step is to produce a lithographic capacitance capacitor region is formed, and then growing a gate oxide layer on the capacitor region, to form a MOS capacitor, then the capacitance of the tuning implant region boron , and the boron implantation energy of 40 keV is, injection dosage ranges 5.5E11-5.7E11, DBICMOS to form a turn-on voltage.

[0011] 在上述的DBICMOS集成电路制造工艺中,所述N型Ldd制作步骤是设置低掺杂的漏区,并在950°C的温度下,对该漏区进行退火推进,且推进的时间范围为30-60min。 [0011] In the DBICMOS integrated circuit fabrication process, the N-type Ldd provided the step of forming lightly doped drain regions, and at a temperature of 950 ° C, and the drain region to promote annealing, and advancing time range 30-60min.

[0012] 在上述的DBICMOS集成电路制造工艺中,所述N型区制作步骤包括对N型区进行砷注入,且砷注入时的能量为IlOkeV,注入的剂量范围为6E15-6E17。 [0012] In the DBICMOS integrated circuit fabrication process, the N-type region creating step comprises implantation of arsenic for N-type regions, and the energy of the arsenic implant is IlOkeV, implantation dose ranging 6E15-6E17.

[0013] 由于采用了上述的技术解决方案,本发明通过增加电容制作步骤将原有的双层多晶的硅栅CMOS工艺改进为单层多晶加电容制作工艺,从而将多晶电容优化为MOS电容,提高了产品的设计精度;同时,通过增加基区制作步骤和N型Ldd(Lightly Doped Drain,轻掺杂漏区)制作步骤,即在通用的CMOS工艺基础上集成了NDMOS (N型耗尽型M0S)和NPN管(三极管)的工艺,实现了双极和DMOS结构的制作;另外,还通过调节N型区的浓度进一步优化了电路性能。 [0013] By adopting the technical solution of the present invention, the original double polycrystalline silicon gate CMOS process manufacturing steps is improved by increasing the capacitance of capacitor production plus a single poly process, so as to optimize the capacitance of the polycrystalline MOS capacitors, improved design accuracy of the product; the same time, increasing the manufacturing steps and the N-type base region Ldd (lightly doped drain, lightly doped drain region) production step, i.e. integrated with the NDMOS (N-type in a CMOS process based on general process M0S depletion type) and NPN transistor (transistor) to achieve a production of bipolar and DMOS structure; in addition, further optimize circuit performance by adjusting the concentration of the N-type region. 本发明可以很好的满足一般用户对于DBICMOS电路的设计和工艺要求以及可以满足一般客户在CMOS电路基础上的设计要求。 The present invention can satisfy the general user to the design and process requirements DBICMOS circuit and meet the general requirements of the customer design circuit based on the CMOS.

具体实施方式 detailed description

[0014] 下面结合附图,对本发明的具体实施例进行详细说明。 [0014] below with the accompanying drawings, specific embodiments of the present invention will be described in detail.

[0015] 本发明,即一种DBICMOS集成电路制造工艺,包括下列步骤:N阱制作步骤、有源区制作步骤、P型场区制作步骤、基区制作步骤、电容制作步骤、多晶制作步骤、N型Ldd制作步骤、N型区制作步骤、P型区制作步骤、接触孔制作步骤、铝线制作步骤和钝化层制作步骤,其中, [0015] In the present invention, i.e., a DBICMOS integrated circuit fabrication process, comprising the following steps: N-well forming step, the step of making the active region, a P-type field region creating step, the step of making the base region, the capacitor manufacturing step, the step of making a polycrystalline , N-type Ldd production step, the step of making the N-type region, P-type region production step, the contact hole making step, the step of making aluminum production step and the passivation layer, wherein

[0016] 基区制作步骤是先光刻形成基区的光刻区域,然后在该光刻区域内进行硼注入,且硼注入时的能量为32.5keV,注入的剂量范围为4.5E13-5.5E13,随后在1100°C的温度下,对该光刻区域进行高温推进,以形成基区,且推进的时间范围为20-30min ; [0016] the step of forming the base region to region of the base region is formed by photolithography photolithography, followed by boron implantation region in the photolithography, and the boron implantation energy is 32.5keV, implantation dose ranging 4.5E13-5.5E13 , then at a temperature of 1100 ° C, the high temperature region for advancing the photolithography, to form a base region and the advancing time is 20-30min;

[0017] 电容制作步骤是先光刻形成电容区,然后在该电容区的特定区域生长具有一定厚度的栅氧化层,以形成MOS电容,再对所述电容区调节注入硼,且硼注入时的能量为40keV,注入的剂量范围为5.5E11-5.7E11,以形成DBICMOS (即NDMOS和M0S)开启电压; When [0017] the step of forming the first capacitor forming a capacitor region photolithography, and then growing a gate oxide layer having a thickness in a specific area of ​​the capacitor area, to form a MOS capacitor, then the capacitance adjustment zone implantation of boron and boron implantation the energy of 40keV, a dose in the range of implantation 5.5E11-5.7E11, to form DBICMOS (i.e. NDMOS and M0S) threshold voltage;

[0018] N型Ldd制作步骤是在沟道中靠近漏极的附近设置一个低掺杂的漏区,并在950°C的温度下,对该漏区进行退火推进,且推进的时间范围为30-60min ;由于该低掺杂的漏区也承受部分电压,可防止热电子退化效应,因此,Ldd结构即是MOS为了减弱漏区电场、以改进热电子退化效应所采取的一种结构,通过该结构可以改善NDMOS的击穿电压,从而达到设计要求; Time [0018] N-type Ldd production step is provided in the channel near the drain in the vicinity of a low-doped drain region, and at a temperature of 950 ° C, and the drain region to promote annealing, and 30 is propelled -60min; Since the lightly doped drain voltage receiving portion also prevents degradation of hot electron effect, therefore, it is a structure Ldd MOS structure is to reduce the drain field region, to improve the hot electron degradation effects taken by this structure can improve the breakdown voltage of the NDMOS to meet the design requirements;

[0019] N型区制作步骤包括对N型区进行砷As注入,且砷注入时的能量为IlOkeV,注入的剂量范围为6E15-6E17。 [0019] N-type region creating step comprises an N-type arsenic As implantation region, and the energy of the arsenic implant is IlOkeV, implantation dose ranging 6E15-6E17.

[0020] 采用本发明制造工艺生产的NDMOS和NPN管,它们的击穿电压一般大于12V,从而可以满足高压的多元化设计要求。 [0020] The manufacturing process of the present invention is produced and the NPN NDMOS, their breakdown voltage is typically greater than 12V, so as to meet the diversified high pressure design requirements.

[0021] 以上结合附图实施例对本发明进行了详细说明,本领域中普通技术人员可根据上述说明对本发明做出种种变化例。 [0021] While the invention has been described in detail in conjunction with the accompanying drawings embodiments of ordinary skill in the art that various changes may be made to the above embodiment of the present invention is described. 因而,实施例中的某些细节不应构成对本发明的限定,本发明将以所附权利要求书界定的范围作为本发明的保护范围。 Thus, certain details of the embodiments should not be construed as limiting the present invention, the present invention will define the scope of the claims appended as the scope of the present invention.

Claims (4)

  1. 1.一种DBICMOS集成电路制造工艺,该制造工艺包括N阱制作步骤、有源区制作步骤、P型场区制作步骤、多晶制作步骤、N型区制作步骤、P型区制作步骤、接触孔制作步骤、铝线制作步骤和钝化层制作步骤,其特征在于,所述制造工艺还包括在所述P型场区制作步骤之后的基区制作步骤和电容制作步骤以及在所述多晶制作步骤之后的N型Ldd制作步骤, 所述电容制作步骤是先光刻形成电容区,然后在该电容区生长栅氧化层,以形成MOS电容,再对所述电容区调节注入硼,且硼注入时的能量为40keV,注入的剂量范围为5.5E11-5.7E11,以形成DBICMOS 开启电压。 A DBICMOS integrated circuit manufacturing process, the manufacturing process comprises a N-well forming step, the step of making the active region, P-type field region production step, a polycrystalline manufacturing steps, the step of making N-type region, P-type region manufacturing steps, in contact with hole making step, the step of making aluminum production step and the passivation layer, characterized in that the process further comprises the step of making a base region and a capacitor fabrication steps following the step of making the P-type field region and in the manufacture of the polycrystalline N-type Ldd production step after manufacturing step, the step of forming said first capacitor forming a capacitor region photolithography, and then growing a gate oxide layer on the capacitor region, to form a MOS capacitor, then the capacitance of the tuning implant region boron, and boron when the injection energy of 40 keV, implantation dose ranging 5.5E11-5.7E11, DBICMOS to form a turn-on voltage.
  2. 2.根据权利要求1所述的DBICMOS集成电路制造工艺,其特征在于,所述基区制作步骤是先光刻形成基区的光刻区域,然后在该光刻区域内进行硼注入,且硼注入时的能量为32.5keV,注入的剂量范围为4.5E13-5.5E13,随后在1100°C的温度下,对该光刻区域进行高温推进,以形成基区,且推进的时间范围为20-30min。 2. DBICMOS integrated circuit fabrication process according to claim 1, characterized in that the base region is formed by photolithography before the step of forming a lithographic base region, followed by boron implantation in the lithography region, and boron when the injection energy of 32.5keV, injection dosage ranges 4.5E13-5.5E13, and then at a temperature of 1100 ° C, the high temperature region to promote the photolithography, to form a base region, and the time range of 20 to promote 30min.
  3. 3.根据权利要求1所述的DBICMOS集成电路制造工艺,其特征在于,所述N型Ldd制作步骤是设置低掺杂的漏区,并在950°C的温度下,对该漏区进行退火推进,且推进的时间范围为30-60min。 3. DBICMOS integrated circuit fabrication process according to claim 1, wherein said N-type Ldd provided the step of forming lightly doped drain regions, and at a temperature of 950 ° C, and annealing the drain region to promote and advance time is 30-60min.
  4. 4.根据权利要求1所述的DBICMOS集成电路制造工艺,其特征在于,所述N型区制作步骤包括对N型区进行砷注入,且砷注入时的能量为IlOkeV,注入的剂量范围为6E15-6E17。 4. The DBICMOS integrated circuit fabrication process of claim 1, wherein said N-type region creating step comprises implantation of arsenic for N-type regions, and the energy of the arsenic implant is IlOkeV, implantation dose range of 6E15 -6E17.
CN 201110076175 2011-03-28 2011-03-28 Manufacturing process of DBICMOS (Diffused/Bipolar Complementary Metal Oxide Semiconductors) integrated circuit CN102184897B (en)

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US5171699A (en) 1990-10-03 1992-12-15 Texas Instruments Incorporated Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication
US5618743A (en) 1992-09-21 1997-04-08 Siliconix Incorporated MOS transistor having adjusted threshold voltage formed along with other transistors
CN1514481A (en) 2002-12-31 2004-07-21 上海贝岭股份有限公司 Technology of manufacturing high voltage semiconductor device
CN1734748A (en) 2004-08-13 2006-02-15 上海先进半导体制造有限公司 Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit

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US20030141566A1 (en) * 2002-01-25 2003-07-31 Agere Systems Guardian Corp. Method of simultaneously manufacturing a metal oxide semiconductor device and a bipolar device

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US5171699A (en) 1990-10-03 1992-12-15 Texas Instruments Incorporated Vertical DMOS transistor structure built in an N-well CMOS-based BiCMOS process and method of fabrication
US5618743A (en) 1992-09-21 1997-04-08 Siliconix Incorporated MOS transistor having adjusted threshold voltage formed along with other transistors
CN1514481A (en) 2002-12-31 2004-07-21 上海贝岭股份有限公司 Technology of manufacturing high voltage semiconductor device
CN1734748A (en) 2004-08-13 2006-02-15 上海先进半导体制造有限公司 Process for manufacturing 0.8 micron silicon bipolar CMOS integrated circuit

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