CN103022006A - Epitaxy technology based three-dimensional integrated power semiconductor and manufacturing method thereof - Google Patents
Epitaxy technology based three-dimensional integrated power semiconductor and manufacturing method thereof Download PDFInfo
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- CN103022006A CN103022006A CN2013100208170A CN201310020817A CN103022006A CN 103022006 A CN103022006 A CN 103022006A CN 2013100208170 A CN2013100208170 A CN 2013100208170A CN 201310020817 A CN201310020817 A CN 201310020817A CN 103022006 A CN103022006 A CN 103022006A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000005516 engineering process Methods 0.000 title claims abstract description 17
- 238000000407 epitaxy Methods 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000012010 growth Effects 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 17
- 239000007924 injection Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 17
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 238000012545 processing Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 4
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- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 6
- 230000000149 penetrating effect Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
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- 238000000151 deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
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- 229910052905 tridymite Inorganic materials 0.000 description 1
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Abstract
The invention discloses an epitaxy technology based three-dimensional integrated power semiconductor and a manufacturing method thereof. Integrated high-power equipment is a VDMOS (vertical diffused metal-oxide semiconductor), and a step of manufacturing substrate materials is added before normal silicon substrate thick epitaxy high-press BCD (bipolar, complementary metal oxide semiconductor, diffused metal-oxide semiconductor) technology. The step of manufacturing the substrate materials includes that heavily doped N-type silicon slices with impurity concentration larger than 19th power of magnitude order are taken as the substrate materials and three times of epitaxial growth are included. The integrated power semiconductor obtained by the manufacturing method can meet transverse dielectric isolation and longitudinal dielectric isolation, is high in integration density and low in leak current among isolated islands.
Description
Technical field
The present invention relates to a kind ofly based on the silicon epitaxy technology, can be used in three-dimensional integrated power semiconductor of making the low-loss power integrated circuit and preparation method thereof.
Background technology
The integrated power semiconductor technology is realize the semiconductor power integrated circuit basic and crucial, the continuous progress of this technology is promoting electronic information and power electronic system constantly toward the development of the aspects such as integrated, intelligent, low power consumption, high stability and reliability.In the integrated power semiconductor technologies of single-chip, precondition is to possess good isolation structure, guarantees the electric insulation between each device; Its key is the compatibility that is the high and low pressure device making technics, only has device compatible on the technique to be integrated together, and each performance of devices of guarantee satisfies application requirements, also reduces production costs as far as possible simultaneously; Can integrated high power device be core, dissimilar high power devices have determined the application that power integrated circuit is different.
The semi-conductive major technique of current integrated power is BCD (Bioplar, CMOS, DMOS) technique, silica-based thick extension High voltage BCD process is in occupation of main share, in this technique, mainly be to isolate by anti-partially PN junction between the device, after the necessary long-time pyroprocess of process, isolation diffusion can be very large, and there is leakage current in anti-partially PN junction, can affect the power consumption of whole circuit, the electrode of various devices all is to draw from chip surface, and integrated high power device mainly is LDMOS(Laterally Diffused MOS, transverse-diffusion MOS (Metal Oxide Semiconductor) device), or LIGBT(Laterally Insulated Gate Bipolar Translator, landscape insulation bar double-pole-type transistor), or the VDMOS(Vertical Diffused MOS that drains and draw from silicon chip surface, longitudinal diffusion MOS device), these devices not only can take more chip area, also can bring difficulty to high pressure interconnection and chip thermal design etc.
Summary of the invention
The technical problem to be solved in the present invention is: a kind of three-dimensional integrated power semiconductor based on epitaxy technology and preparation method thereof is provided, expand conventional BCD process, satisfy horizontal medium isolation, vertically knot isolation, can be used for producing high integration, the power integrated circuit of leakage current between low isolated island.
Technical scheme of the present invention is: a kind of three-dimensional integrated power semiconductor based on epitaxy technology, the integrated power semiconductor comprises heavy doping N-type silicon chip, ground floor light dope N-type epitaxial loayer, second layer light dope N-type epitaxial loayer and the 3rd layer of light dope N-type epitaxial loayer from bottom to up successively, comprise the P_bulk layer between second layer light dope N-type epitaxial loayer and the 3rd layer of light dope N-type epitaxial loayer, comprise PBL, P_sink district and N_sink district in the 3rd floor light dope N-type epitaxial loayer of P_bulk floor top, in second and third layer light dope N-type epitaxial loayer filling slot is arranged.Filled media comprises SiO
2Perhaps SiO
2Composition with polysilicon.
A kind of above-mentioned semi-conductive manufacture method of three-dimensional integrated power based on epitaxy technology comprises base material making step and conventional BCD processing step.
Choose heavily doped N-type silicon chip as backing material (impurity concentration is more than the 19 power orders of magnitude), at the certain thickness light dope N-type epitaxial loayer of silicon substrate growth, the thickness of epitaxial loayer and concentration are by the withstand voltage decision of isolation structure and VDMOS first.Next carry out photoetching, etching, boron impurity injection and annealing in P_bulk layer corresponding region.Carry out the light dope N-type outer layer growth second time after removing surface oxide layer, the thickness of this epitaxial loayer and concentration are by the withstand voltage decision of P_bulk layer.And then carry out alignment, etching in P_bulk layer corresponding region, boron impurity injects and annealing, carries out PBL(P-type Buried Layer, p type buried layer need to doing the position that body draws to the P_bulk layer) alignment, etching, boron impurity injects and annealing.Carry out for the third time light dope N-type outer layer growth after removing surface oxide layer, the thickness of the 3rd epitaxial loayer and concentration are mainly by the withstand voltage decision of low-voltage device.Then carrying out heavy doping N_sink(N type at the collector electrode place of drawing, the transistorized base stage of the PNP place of drawing of NPN transistor penetrates) alignment, etching, phosphorus impurities in district inject, carry out the P_sink(P type and penetrate need to doing position that body draws to P_bulk) alignment, etching, the boron impurity in district inject.Through oxidizing annealing at the silicon chip surface certain thickness SiO that grows
2(silicon dioxide) etches away the SiO in groove district
2After carry out the grooving backfilling process, the medium of backfill can be single SiO
2, also can be " SiO
2+ un-doped polysilicon ", the latter is without concrete mixed proportion.Polysilicon only is used for filling SiO
2Do not fill full space.If that fill in the groove is " SiO
2+ polysilicon ", then need the polysilicon on surface is removed, and make the silicon chip surface planarization.So far finished the preparation of semi-insulating base material.
Polysilicon and SiO with silicon chip surface
2(silicon dioxide) is got rid of, and after making the silicon chip surface planarization, ensuing technique is all carried out (except last attenuate and back side metallization technology) in light dope epitaxial loayer one side, and the processing step of these techniques and conventional BCD is basically identical.At first be alignment, injection and the annealing of P trap (perhaps N trap); Next carry out an oxidation and active area photoetching and etching; After etching the active area window, for the thick grating oxide layer that obtains VDMOS and the thin gate oxide of low pressure MOS, the first thicker gate oxide of growth is removed the gate oxide that regrowth one deck is thin with the thick grating oxide layer of the grid corresponding region of low pressure MOS; The certain thickness polysilicon of deposit carries out etching polysilicon and oxidation, and polysilicon doping is by follow-up N+(or P+) when injecting, autoregistration finishes together; Next carry out alignment, etching, injection and the annealing in body district (tagma of VDMOS); Then carry out the heavy doping p type island region of ZP(Zener diode) alignment, etching, injection and annealing; Then be N+ district alignment, etching, injection and annealing, P+ district alignment, etching, injection and annealing; Then use the LPCVD(low-pressure chemical vapor deposition) the thicker SiO of deposit
2(silicon dioxide) is to SiO
2(silicon dioxide) carries out density, plays simultaneously the annealing effect to N+ district and P+ district; Then the window as pressure welding point or test point of carry out that contact hole photoetching and etching, deposited metal, metal level anti-carve, growing surface passivation layer, photoetching and etching TOPSIDE(leaving at passivation layer) window.At last, the heavy doping substrate thinning to certain thickness (concrete thickness is required to determine by working condition and device parameters), is carried out back face metalization again.
Principle Analysis of the present invention is as follows: the homotype light dope epitaxial loayer that the one deck of growing first on heavily doped substrate slice is thicker, inject the impurity of opposite types in other zones except the VDMOS corresponding region, the epitaxial loayer that regrowth one deck is identical with the substrate doping type, then also inject the impurity of opposite types in other zones except the VDMOS corresponding region, carry out buried regions photoetching and injection at the body extraction location, the epitaxial loayer that regrowth one deck is identical with the substrate doping type, then carry out respectively photoetching and the injection of N-type and P type penetrating region, the masking layer of using when behind oxidizing annealing, obtaining grooving.Grooving, backfill medium and surface media all removed after, obtained making the required semi-insulating base material of three-dimensional integrated power chip.According to different application, can choose the semi-insulating base material that n extension adds that n-1 Impurity injection realized satisfying the demands.
After above-mentioned steps is produced semi-insulating base material, adopt and the duplicate processing step of conventional BCD, contained high power device is VDMOS in the power integrated circuit of producing, and the drain electrode of VDMOS is to draw from chip back, device and device laterally between be the medium isolation, be that PN junction is isolated between low-voltage device and the substrate.The drain electrode of high-power V DMOS device is drawn from the back side of power integrated chip, be conducive to improve the complexity of the power density of power integrated chip, the utilance that improves silicon materials, the difficulty that reduces the high pressure interconnection, reduction thermal design problem.
The present invention compared with prior art has the following advantages:
Integrated high power device is VDMOS, and the drain electrode of VDMOS is drawn from chip back, realizes the three-dimensional integrated of single-chip, has improved the power density of power integrated circuit, has reduced the interconnected complexity of high pressure.Couple together by the opposite window of dopant type of leaving at the P_bulk layer between the drift region of high-power V DMOS and the substrate, namely realized the vertical conduction path of VDMOS, guaranteed again the electric insulation between each low-voltage device and the substrate.Each device adopts the medium isolation between laterally, has saved chip area, has reduced the power loss that the leakage current that exists because of isolated part causes.
Description of drawings
Fig. 1 is semi-insulating underlying structure profile of the present invention, Si represents silicon among the figure, SiO2 represents silicon dioxide, Poly represents polysilicon, N+ substrate represents heavily doped N-type substrate, and the P_bulk layer represents P type interlayer, and N-represents lightly doped N-type layer, PBL represents p type buried layer, and the P_sink district represents P type penetrating region.
Fig. 2 is section of structure of the present invention, NSD represents the N-type heavily doped region among the figure, and PSD represents P type heavily doped region, and the N_sink district represents the N-type penetrating region, S represents metal-oxide-semiconductor " source electrode ", G represents metal-oxide-semiconductor " grid ", and D represents " drain electrode " of metal-oxide-semiconductor, and C represents " collector electrode " of bipolar transistor, B represents bipolar transistor " base stage ", E represents bipolar transistor " emitter ", and Vdd represents "+" current potential, the GND representative " " current potential.
Embodiment
Such as Fig. 2, a kind of three-dimensional integrated power semiconductor based on epitaxy technology, integrated high power device is VDMOS, the integrated power semiconductor comprises heavy doping N-type silicon chip, ground floor light dope N-type epitaxial loayer, second layer light dope N-type epitaxial loayer and the 3rd layer of light dope N-type epitaxial loayer from bottom to up successively, comprise the P_bulk layer between second layer light dope N-type epitaxial loayer and the 3rd layer of light dope N-type epitaxial loayer, comprise PBL, P_sink district and N_sink district in the 3rd floor light dope N-type epitaxial loayer of P_bulk floor top, in second and third layer light dope N-type epitaxial loayer filling slot is arranged.Filled media is SiO
2Composition with polysilicon.
Such as Fig. 1, the first step is the preparation of semi-insulating base material.It is the N＜100〉arsenic doped silicon wafer of 0.002 ~ 0.004 Ω cm that preparing substrate material at first, heavy doping silicon substrate are selected resistivity, and perhaps resistivity is the N＜100 of 0.008 ~ 0.02 Ω cm〉mix stibium silicon chip.First at the burnishing surface growth thickness of substrate slice about 20 m, impurity concentration is the N-epitaxial loayer of 2.5e15.Then in the oxide layer of epitaxial loayer by thermal oxidation (1050 ℃ of wet-oxygen oxidations) growth about 6000.When carrying out the P_bulk layer photoetching first time/corrosion, leave the alignment mark window, inject (implantation dosage: 8.0e12 through pre-oxidation (the impurity gear of 950 ℃ of wet-oxygen oxidation growths about 1000 is kept away oxide layer), low boron, Implantation Energy: 80KeV), after the annealing (under 850 ℃ of nitrogen environments annealing 30 minutes), the oxide layer of wet-oxygen oxidation growth about 4000 under 1050 ℃ of conditions again, after the surface oxide layer removal, the zone that alignment mark is corresponding is shorter by about 1500 than the peripheral region, thereby has obtained the alignment mark that the subsequent technique alignment is used.Next carry out for the second time growth of N-epitaxial loayer, the thickness of this epitaxial loayer is 5 m, and impurity concentration is 2.5e15.Extension is carried out later P_bulk layer photoetching second time, burn into injects and annealing, reticle and other process conditions with the first time P_bulk layer the same.Need to be by PBL(P type buried regions as the P type divider wall of anti-partially PN junction isolation) and P_sink district (P type penetrating region) form leading to spread, so must be PBL in position corresponding to P type divider wall before the extension for the third time.The alignment, burn into of finishing PBL inject and annealing after carry out for the third time N-outer layer growth, the thickness of the 3rd layer of extension is 11 m, impurity concentration is 2.5e15.Then be that alignment, the burn into that carries out N_sink district (N-type penetrating region) and P_sink district injects and annealing, the N_sink district is for the collector series resistance that reduces NPN transistor and the transistorized base series resistor of PNP.When carrying out the annealing of N_sink district and P_sink district, in the thicker oxide layer of silicon chip surface growth one deck, etch away the SiO in groove district
2After carry out the grooving backfilling process, the width of groove is 1.6 m, groove needs the N-epitaxial loayer of break-through top layer to arrive the P_bulk layer in the vertical, some is embedded in the P_bulk layer at bottom land.The medium of backfill is " SiO
2+ un-doped polysilicon ", first by thermal oxidation at the certain thickness SiO of cell wall growth
2Concrete thickness is by the withstand voltage decision of groove), then depositing polysilicon fills up groove.After the medium backfill is finished by CMP(Chemical Mechanical Polishing, cmp) thrown polysilicon and the SiO of silicon chip surface
2So far finished the preparation of base material.
Second step is the realization of various devices and circuit.Polysilicon and the SiO on surface have been thrown
2, and behind the flattening surface, ensuing technique is all carried out (except last attenuate and back side metallization technology) at the light dope epitaxial loayer, and the processing step of these techniques and conventional BCD is basically identical.At first be to carry out the P_well(P trap) alignment, injection and annealing; Next carry out an oxidation and active area photoetching and etching; After etching the active area window, for the thick grating oxide layer that obtains VDMOS and the thin gate oxide of low pressure MOS, the first thicker gate oxide (thickness is about 850) of growth, the thick grating oxide layer of the grid corresponding region of low pressure MOS is removed the gate oxide that regrowth one deck is thin (thickness is about 360); Deposition thickness is the polysilicon of 0.5 m, carries out etching polysilicon and oxidation, and polysilicon doping is by follow-up NSD(N+ source/leakage) when injecting, autoregistration finishes together; Next carry out alignment, etching, injection and the annealing in body district (tagma of VDMOS); Then carry out the heavy doping p type island region of ZP(Zener diode) alignment, etching, injection and annealing; Then be NSD alignment, etching, injection and annealing, PSD(P+ source/leakage) district's alignment, etching, injection and annealing; Then use the LPCVD(low-pressure chemical vapor deposition) silicon dioxide of deposit 4500, under 960 ℃ of nitrogen environments silicon dioxide was carried out density 30 minutes, play simultaneously the annealing effect to NSD and PSD; Then the window as pressure welding point or test point of carry out that contact hole photoetching and etching, deposited metal, metal level anti-carve, growing surface passivation layer, photoetching and etching TOPSIDE(leaving at passivation layer) window.At last, with heavy doping substrate thinning to 300 ~ 350um, carry out again back face metalization.
The present invention is applicable to various single chip integrated power integrated circuits.
Claims (3)
1. three-dimensional integrated power semiconductor based on epitaxy technology, it is characterized in that: described integrated power semiconductor comprises heavy doping N-type silicon chip from bottom to up successively, ground floor light dope N-type epitaxial loayer, second layer light dope N-type epitaxial loayer and the 3rd layer of light dope N-type epitaxial loayer, comprise the P_bulk layer between second layer light dope N-type epitaxial loayer and the 3rd layer of light dope N-type epitaxial loayer, comprise PBL in the 3rd layer of light dope N-type epitaxial loayer of P_bulk layer top, P_sink district and N_sink district, second, in three layers of light dope N-type epitaxial loayer filling slot being arranged, is filled media in the groove.
2. a kind of three-dimensional integrated power semiconductor based on epitaxy technology according to claim 1 is characterized in that: the filled media in the filling slot comprises SiO
2Or SiO
2Composition with polysilicon.
3. make integrated power method for semiconductor in the claim 1 and 2 for one kind, comprise the BCD processing step, it is characterized in that: before the BCD processing step, also comprise the step of making base material:
At first select impurity concentration to make backing material greater than the heavy doping N-type silicon chip of the 19 power orders of magnitude, at silicon substrate growth one deck light dope N-type epitaxial loayer, next carry out photoetching, etching, boron impurity injection and annealing in P_bulk layer corresponding region first;
Carry out second layer light dope N-type outer layer growth after removing surface oxide layer, and then carry out alignment, etching in P_bulk layer corresponding region, boron impurity injects and annealing, PBL alignment, etching are carried out in the position that body draws, boron impurity injects and annealing in that the P_bulk layer is done;
Carry out the 3rd layer of light dope N-type outer layer growth after removing surface oxide layer, then carry out alignment, etching, the phosphorus impurities injection in heavy doping N_sink district at the collector electrode place of drawing of NPN transistor and the transistorized base stage of the PNP place of drawing, carry out alignment, etching, the boron impurity injection in P_sink district the P_bulk floor being done the position that body draws;
Through oxidizing annealing at silicon chip surface growth one deck SiO
2, etch away the SiO in groove district
2After carry out the grooving backfill, the medium of backfill comprises single SiO
2Perhaps SiO
2Composition with polysilicon.
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| CN113690318B (en) * | 2021-10-25 | 2022-05-03 | 陕西亚成微电子股份有限公司 | Longitudinal BCD device and preparation method thereof |
| CN113690319B (en) * | 2021-10-25 | 2022-05-03 | 陕西亚成微电子股份有限公司 | Longitudinal BCD device capable of inhibiting parasitism and preparation method thereof |
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