CN103022006B - Epitaxy technology based three-dimensional integrated power semiconductor and manufacturing method thereof - Google Patents
Epitaxy technology based three-dimensional integrated power semiconductor and manufacturing method thereof Download PDFInfo
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- CN103022006B CN103022006B CN201310020817.0A CN201310020817A CN103022006B CN 103022006 B CN103022006 B CN 103022006B CN 201310020817 A CN201310020817 A CN 201310020817A CN 103022006 B CN103022006 B CN 103022006B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000005516 engineering process Methods 0.000 title claims abstract description 17
- 238000000407 epitaxy Methods 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 14
- 230000012010 growth Effects 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 54
- 238000005530 etching Methods 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 26
- 239000011229 interlayer Substances 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 17
- 239000007924 injection Substances 0.000 claims description 17
- 230000000149 penetrating effect Effects 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 16
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 4
- 150000004706 metal oxides Chemical class 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 3
- 230000000295 complement effect Effects 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
The invention discloses an epitaxy technology based three-dimensional integrated power semiconductor and a manufacturing method thereof. Integrated high-power equipment is a VDMOS (vertical diffused metal-oxide semiconductor), and a step of manufacturing substrate materials is added before normal silicon substrate thick epitaxy high-press BCD (bipolar, complementary metal oxide semiconductor, diffused metal-oxide semiconductor) technology. The step of manufacturing the substrate materials includes that heavily doped N-type silicon slices with impurity concentration larger than 19th power of magnitude order are taken as the substrate materials and three times of epitaxial growth are included. The integrated power semiconductor obtained by the manufacturing method can meet transverse dielectric isolation and longitudinal dielectric isolation, is high in integration density and low in leak current among isolated islands.
Description
Technical field
The present invention relates to a kind of based on silicon epitaxy technology, can be used in three-dimensional integrated power semiconductor manufacturing low-loss power integrated circuit and preparation method thereof.
Background technology
Integrated power semiconductor technology is the basis and the key that realize semiconductor power integrated circuit, the continuous progress of this technology, promotes electronic information and power electronic system constantly develops toward aspects such as integrated, intelligent, low power consumption, high stability and reliabilities.In the power semiconductor technologies of Single-Chip Integration, precondition to possess good isolation structure, guarantees the electric insulation between each device; Its key is the compatibility being high and low pressure device making technics, only has device compatible in technique to be integrated together, and the performance of each device of guarantee meets application requirement, also reduces production cost as far as possible simultaneously; The high power device of accessible site is core, and dissimilar high power device determines the different application of power integrated circuit.
The major technique of current integrated power semiconductor is BCD (Bioplar, CMOS, DMOS) technique, silica-based thick extension High voltage BCD process is in occupation of dominant contribution, in such a process, mainly isolated by reverse biased pn junction between device, after necessary long-time pyroprocess, isolation diffusion can be very large, and there is leakage current in reverse biased pn junction, the power consumption of whole circuit can be affected, the electrode of various device is all draw from chip surface, integrated high power device is LDMOS(Laterally Diffused MOS mainly, transverse-diffusion MOS (Metal Oxide Semiconductor) device), or LIGBT(Laterally Insulated Gate Bipolar Translator, landscape insulation bar double-pole-type transistor), or the VDMOS(Vertical Diffused MOS that drain electrode is drawn from silicon chip surface, longitudinal diffusion MOS device), these devices not only can take more chip area, also can bring difficulty to high pressure interconnection and chip thermal design etc.
Summary of the invention
The technical problem to be solved in the present invention is: provide a kind of three-dimensional integrated power semiconductor based on epitaxy technology and preparation method thereof, expand conventional BCD process, meet the isolation of horizontal medium, longitudinally tie isolation, can be used for producing high integration, the power integrated circuit of leakage current between low isolated island.
Technical scheme of the present invention is: a kind of three-dimensional integrated power semiconductor based on epitaxy technology, integrated power semiconductor comprises heavily doped N-type silicon chip from bottom to up successively, ground floor lightly doped n-type epitaxial loayer, second layer lightly doped n-type epitaxial loayer and third layer lightly doped n-type epitaxial loayer, P type interlayer is comprised between ground floor lightly doped n-type epitaxial loayer and third layer lightly doped n-type epitaxial loayer, P type interlayer is embedded in second layer lightly doped n-type epitaxial loayer, p type buried layer is comprised in third layer lightly doped n-type epitaxial loayer above P type interlayer, P type penetrating region and N-type penetrating region, second, filling slot is had in three layers of lightly doped n-type epitaxial loayer.Filled media comprises SiO
2or SiO
2with the composition of un-doped polysilicon.
A manufacture method for the above-mentioned three-dimensional integrated power semiconductor based on epitaxy technology, comprises base material making step and conventional BCD processing step.
Choose heavily doped N-type silicon chip as backing material (impurity concentration is more than the 19 power orders of magnitude), first on silicon substrate, grow certain thickness lightly doped n-type epitaxial loayer, the thickness of epitaxial loayer and concentration are by the withstand voltage decision of isolation structure and VDMOS.Next photoetching, etching, boron impurity injection and annealing is carried out in P type interlayer corresponding region.Carry out second time lightly doped n-type outer layer growth after removing surface oxide layer, the thickness of this epitaxial loayer and concentration are by the withstand voltage decision of P type interlayer.And then to carry out alignment in P type interlayer corresponding region, etching, boron impurity inject and annealing, carries out PBL(P-type Buried Layer, p type buried layer needing to do to P type interlayer the position that body draws) alignment, etching, boron impurity inject and annealing.Carry out third time lightly doped n-type outer layer growth after removing surface oxide layer, the thickness of the 3rd epitaxial loayer and concentration are primarily of the withstand voltage decision of low-voltage device.Then carrying out heavy doping N_sink(N type penetrate in collector electrode extraction place of NPN transistor, base stage extraction place of PNP transistor) alignment in district, etching, phosphorus impurities inject, carry out P_sink(P type and penetrate needing to do to P type interlayer position that body draws) alignment in district, etching, boron impurity inject.Certain thickness SiO is grown at silicon chip surface through oxidizing annealing
2(silicon dioxide), etches away the SiO in groove district
2after carry out grooving backfilling process, the medium of backfill can be single SiO
2, also can be " SiO
2+ un-doped polysilicon ", the latter is without concrete mixed proportion.Polysilicon is only for filling SiO
2do not fill full space.If that fill in groove is " SiO
2+ un-doped polysilicon ", then need the polysilicon on surface to remove, and make silicon chip surface planarization.So far the preparation of semi-insulating base material is completed.
By the polysilicon of silicon chip surface and SiO
2(silicon dioxide) is got rid of, and after making silicon chip surface planarization, ensuing technique is all carried out (the thinning and back side metallization technology except last) in light dope epitaxial loayer side, and the processing step of these techniques and conventional BCD is basically identical.First be the alignment of P trap (or N trap), injection and annealing; Next field oxidation and active area photoetching and etching is carried out; After etching active area window, in order to the thin gate oxide of the thick grating oxide layer and low pressure MOS that obtain VDMOS, first grow thicker gate oxide, the thick grating oxide layer of the grid corresponding region of low pressure MOS is removed, the gate oxide that regrowth one deck is thin; The certain thickness polysilicon of deposit, carries out etching polysilicon and oxidation, and polysilicon doping is by follow-up N+(or P+) autoregistration inject time complete together; Next the alignment in body district (tagma of VDMOS), etching, injection and annealing is carried out; Then carry out the heavily doped P-type district of ZP(Zener diode) alignment, etching, injection and annealing; Then be N+ district alignment, etching, injection and annealing, P+ district alignment, etching, injection and annealing; Then LPCVD(low-pressure chemical vapor deposition is used) the thicker SiO of deposit
2(silicon dioxide), to SiO
2(silicon dioxide) carries out density, plays the annealing effect to N+ district and P+ district simultaneously; Then carry out contact hole photoetching and etching, deposited metal, metal level anti-carve, growing surface passivation layer, photoetching and etching TOPSIDE(output over the passivation layer as the window of pressure welding point or test point) window.Finally, by heavy doping substrate thinning to certain thickness (concrete thickness is determined by working condition and device parameter requirements), then back face metalization is carried out.
Principle Analysis of the present invention is as follows: on heavily doped substrate slice, first grow the homotype light dope epitaxial loayer that one deck is thicker, the impurity of opposite types is injected in other regions except VDMOS corresponding region, the epitaxial loayer that regrowth one deck is identical with substrate doping type, then the impurity of opposite types is also injected in other regions except VDMOS corresponding region, buried regions photoetching and injection is carried out at body extraction location, the epitaxial loayer that regrowth one deck is identical with substrate doping type, then photoetching and the injection of N-type and P type penetrating region is carried out respectively, masking layer during grooving is obtained after oxidizing annealing.Grooving, backfill dielectric after all being removed by surface media, obtain the semi-insulating base material made needed for three-dimensional integrated power chip.According to different application, n extension can be chosen and add that n-1 impurity injects the semi-insulating base material realizing satisfying the demands.
Produce after semi-insulating base material through above-mentioned steps, adopt and the duplicate processing step of conventional BCD, high power device contained in the power integrated circuit produced is VDMOS, and the drain electrode of VDMOS is drawn from chip back, being medium isolation between device and the transverse direction of device, is PN junction isolation between low-voltage device and substrate.The back side of the drain electrode of high-power V DMOS device from power integrated chip is drawn, is conducive to the complexity improving the power density of power integrated chip, the utilance improving silicon materials, the difficulty reducing high pressure interconnection, reduction thermal design problem.
The present invention compared with prior art, has the following advantages:
Integrated high power device is VDMOS, and the drain electrode of VDMOS is drawn from chip back, and the three-dimensional realizing single-chip is integrated, improves the power density of power integrated circuit, reduces the complexity that high pressure is interconnected.Coupled together by the window that the dopant type outputed on P type interlayer is contrary between the drift region of high-power V DMOS and substrate, namely achieve the vertical conductive vias of VDMOS, in turn ensure that the electric insulation between each low-voltage device and substrate.Adopt medium to isolate between each device is horizontal, save chip area, reduce the power loss caused because of the leakage current of isolated part existence.
Accompanying drawing explanation
Fig. 1 is semi-insulating underlying structure profile of the present invention, in figure, Si represents silicon, SiO2 represents silicon dioxide, Poly represents polysilicon, N+ substrate represents heavily doped N-type substrate, and P_bulk layer represents P type interlayer, and N-represents lightly doped N-type layer, PBL represents p type buried layer, and P_sink district represents P type penetrating region.
Fig. 2 is section of structure of the present invention, in figure, NSD represents N-type heavily doped region, and PSD represents P type heavily doped region, and N_sink district represents N-type penetrating region, S represents " source electrode " of metal-oxide-semiconductor, G represents " grid " of metal-oxide-semiconductor, and D represents " drain electrode " of metal-oxide-semiconductor, and C represents " collector electrode " of bipolar transistor, B represents " base stage " of bipolar transistor, E represents " emitter " of bipolar transistor, and Vdd represents "+" current potential, GND representative " " current potential.
Embodiment
As Fig. 2, a kind of three-dimensional integrated power semiconductor based on epitaxy technology, integrated high power device is VDMOS, integrated power semiconductor comprises heavily doped N-type silicon chip from bottom to up successively, ground floor lightly doped n-type epitaxial loayer, second layer lightly doped n-type epitaxial loayer and third layer lightly doped n-type epitaxial loayer, P type interlayer is comprised between ground floor lightly doped n-type epitaxial loayer and third layer lightly doped n-type epitaxial loayer, P type interlayer is embedded in second layer lightly doped n-type epitaxial loayer, p type buried layer is comprised in third layer lightly doped n-type epitaxial loayer above P type interlayer, P type penetrating region and N-type penetrating region, second, filling slot is had in three layers of lightly doped n-type epitaxial loayer.Filled media is SiO
2with the composition of un-doped polysilicon.
As Fig. 1, the first step is the preparation of semi-insulating base material.First preparing substrate material, heavy doping silicon substrate selects resistivity to be the N<100> arsenic doped silicon wafer of 0.002 ~ 0.004 Ω cm, or resistivity is that the N<100> of 0.008 ~ 0.02 Ω cm mixes stibium silicon chip.The first burnishing surface growth thickness at substrate slice is 20
left and right, impurity concentration is the N-epitaxial loayer of 2.5e15.Then on epitaxial loayer, 6000 are grown by thermal oxidation (1050 DEG C of wet-oxygen oxidations)
the oxide layer of left and right.Alignment mark window is outputed, through pre-oxidation (950 DEG C of wet-oxygen oxidation growths 1000 while carrying out first time P type interlayer photoetching/corrosion
the impurity gear of left and right keeps away oxide layer), after low boron injects (implantation dosage: 8.0e12, Implantation Energy: 80KeV), annealing (under 850 DEG C of nitrogen environments anneal 30 minutes), then wet-oxygen oxidation growth 4000 under 1050 DEG C of conditions
the oxide layer of left and right, after being removed by surface oxide layer, the region that alignment mark is corresponding is shorter than peripheral region by 1500
left and right, thus the alignment mark obtaining subsequent technique alignment.Next carry out the growth of second time N-epitaxial loayer, the thickness of this epitaxial loayer is 5
, impurity concentration is 2.5e15.Carry out the photoetching of second time P type interlayer after extension, burn into injects and annealing, reticle and other process conditions and for the first time P type interlayer the same.P type divider wall as reverse biased pn junction isolation needs by PBL(P type buried regions) and P_sink district (P type penetrating region) logical diffusion is formed, so PBL must be in the position that P type divider wall is corresponding before third time extension.Carry out third time N-outer layer growth after completing the alignment of PBL, burn into injection and annealing, the thickness of third layer extension is 11
, impurity concentration is 2.5e15.Then be carry out the alignment of N_sink district (N-type penetrating region) and P_sink district (P type penetrating region), burn into injects and annealing, N-type penetrating region is the base series resistor in order to the collector series resistance and PNP transistor reducing NPN transistor.While carrying out N-type penetrating region and the annealing of P type penetrating region, grow the thicker oxide layer of one deck at silicon chip surface, etch away the SiO in groove district
2after carry out grooving backfilling process, the width of groove is 1.6
, groove needs the N-epitaxial loayer of break-through top layer to arrive P type interlayer in the vertical, and at bottom land, some is embedded in P type interlayer.The medium of backfill is " SiO
2+ un-doped polysilicon ", first on cell wall, grow certain thickness SiO by thermal oxidation
2concrete thickness is by the withstand voltage decision of groove), then groove fills up by depositing polysilicon.By CMP(Chemical Mechanical Polishing after medium has backfilled, cmp) throw polysilicon and the SiO of silicon chip surface
2.So far the preparation of base material is completed.
Second step is the realization of various device and circuit.Polysilicon and the SiO on surface are thrown
2, and after surface planarisation, ensuing technique is all carried out on light dope epitaxial loayer (the thinning and back side metallization technology except last), and the processing step of these techniques and conventional BCD is basically identical.First be carry out P_well(P trap) alignment, injection and annealing; Next field oxidation and active area photoetching and etching is carried out; After etching active area window, in order to the thin gate oxide of the thick grating oxide layer and low pressure MOS that obtain VDMOS, (thickness is about 850 first to grow thicker gate oxide
), removed by the thick grating oxide layer of the grid corresponding region of low pressure MOS, (thickness is about 360 to the thin gate oxide of regrowth one deck
); Deposition thickness is 0.5
polysilicon, carry out etching polysilicon and oxidation, polysilicon doping is by follow-up NSD(N+ source/drain) autoregistration inject time complete together; Next the alignment in body district (tagma of VDMOS), etching, injection and annealing is carried out; Then carry out the heavily doped P-type district of ZP(Zener diode) alignment, etching, injection and annealing; Then be NSD alignment, etching, injection and annealing, PSD(P+ source/drain) district's alignment, etching, injection and annealing; Then LPCVD(low-pressure chemical vapor deposition is used) deposit 4500
silicon dioxide, under 960 DEG C of nitrogen environments, density is carried out 30 minutes to silicon dioxide, plays the annealing effect to NSD and PSD simultaneously; Then carry out contact hole photoetching and etching, deposited metal, metal level anti-carve, growing surface passivation layer, photoetching and etching TOPSIDE(output over the passivation layer as the window of pressure welding point or test point) window.Finally, by heavy doping substrate thinning to 300 ~ 350um, then carry out back face metalization.
The present invention is applicable to various single chip integrated power integrated circuit.
Claims (3)
1. the three-dimensional integrated power semiconductor based on epitaxy technology, it is characterized in that: described integrated power semiconductor comprises heavily doped N-type silicon chip from bottom to up successively, ground floor lightly doped n-type epitaxial loayer, second layer lightly doped n-type epitaxial loayer and third layer lightly doped n-type epitaxial loayer, P type interlayer is comprised between ground floor lightly doped n-type epitaxial loayer and third layer lightly doped n-type epitaxial loayer, P type interlayer is embedded in second layer lightly doped n-type epitaxial loayer, p type buried layer is comprised in third layer lightly doped n-type epitaxial loayer above P type interlayer, P type penetrating region and N-type penetrating region, second, filling slot is had in three layers of lightly doped n-type epitaxial loayer, be filled media in groove.
2. a kind of three-dimensional integrated power semiconductor based on epitaxy technology according to claim 1, is characterized in that: the filled media in filling slot comprises SiO
2or SiO
2with the composition of un-doped polysilicon.
3. make a method for integrated power semiconductor in claim 1 or 2, comprise BCD processing step, it is characterized in that: before BCD processing step, also comprise the step making base material:
First the heavily doped N-type silicon chip selecting impurity concentration to be greater than the 19 power orders of magnitude makes backing material, first on silicon substrate, grows one deck lightly doped n-type epitaxial loayer, next carries out photoetching, etching, boron impurity injection and annealing in P type interlayer corresponding region;
Second layer lightly doped n-type outer layer growth is carried out after removing surface oxide layer, and then carry out alignment, etching, boron impurity injection and annealing in P type interlayer corresponding region, p type buried layer alignment, etching, boron impurity injection and annealing is carried out in the position of P type interlayer being done to body extraction;
Third layer lightly doped n-type outer layer growth is carried out after removing surface oxide layer, then carry out the alignment of heavily doped N-type penetrating region in collector electrode extraction place of NPN transistor and base stage extraction place of PNP transistor, etching, phosphorus impurities inject, doing position that body draws to P type interlayer and carry out the alignment of P type penetrating region, etching, boron impurity inject;
One deck SiO is grown at silicon chip surface through oxidizing annealing
2, etch away the SiO in groove district
2after carry out grooving backfill, the medium of backfill comprises single SiO
2or SiO
2with the composition of un-doped polysilicon.
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| US9613878B2 (en) | 2013-12-06 | 2017-04-04 | Infineon Technologies Dresden Gmbh | Carrier and a method for processing a carrier |
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| US9560765B2 (en) | 2013-12-06 | 2017-01-31 | Infineon Technologies Dresden Gmbh | Electronic device, a method for manufacturing an electronic device, and a method for operating an electronic device |
| CN106092151A (en) * | 2015-06-29 | 2016-11-09 | 苏州森特克测控技术有限公司 | A kind of high pressure resistant process design method and high-voltage tolerant chip |
| CN107180829B (en) * | 2017-05-26 | 2019-12-27 | 电子科技大学 | BCD device and manufacturing method thereof |
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| CN113690318B (en) * | 2021-10-25 | 2022-05-03 | 陕西亚成微电子股份有限公司 | Longitudinal BCD device and preparation method thereof |
| CN113690319B (en) * | 2021-10-25 | 2022-05-03 | 陕西亚成微电子股份有限公司 | Longitudinal BCD device capable of inhibiting parasitism and preparation method thereof |
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| CN101764101A (en) * | 2008-12-25 | 2010-06-30 | 上海先进半导体制造股份有限公司 | BCD integration process |
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