CN106092151A - A kind of high pressure resistant process design method and high-voltage tolerant chip - Google Patents
A kind of high pressure resistant process design method and high-voltage tolerant chip Download PDFInfo
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- CN106092151A CN106092151A CN201610436842.0A CN201610436842A CN106092151A CN 106092151 A CN106092151 A CN 106092151A CN 201610436842 A CN201610436842 A CN 201610436842A CN 106092151 A CN106092151 A CN 106092151A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
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Abstract
The embodiment of the present application provides a kind of high pressure resistant process design method and high-voltage tolerant chip, wherein, high pressure resistant process design method by increasing the thickness of epitaxial layer, reducing its doping content, to improve the maximum of chip pressure.The present invention, on the premise of not significantly improving cost, increases the high voltage withstanding ability of chip.
Description
Technical field
The invention belongs to field of semiconductor technology, particularly relate to a kind of high pressure resistant process design method and high-voltage tolerant chip.
Background technology
Existing magnetic sensor chip many employings standard bipolar technique or the CMOS technology manufacture of standard.But it is currently based on
The high-voltage resistance capability of the chip that both technique manufactures obtain is relatively low, usually about 24V.Continuous increasing along with application scenarios
Adding, such voltage endurance capability the most can not meet needs.
In prior art, for obtaining higher voltage endurance capability, people select BCD technique, DMOS (Double therein
Diffused Metal Oxide Semiconductor) there is high voltage endurance capability.But the mask of about more than 30 layers easily,
With 10 layers of bipolar process of standard, compare with 16 layers of CMOS technology of standard, product cost is too high, about more than 30 layers simultaneously
Mask, also can cause a hidden trouble to the reliability of product.
Summary of the invention
The present invention provides a kind of high pressure resistant process design method and high-voltage tolerant chip, with in the premise not significantly improving cost
Under, increase the high-voltage resistance capability of chip.
For achieving the above object, the embodiment of the present invention provides a kind of high pressure resistant process design method, and the method is by increasing
The maximum that the thickness of epitaxial layer improves chip is pressure.
Preferably, method also includes that the maximum by reducing epitaxial layer n doping diffusion concentration raising chip is pressure；
And/or；
Described method also includes that the maximum of the thickness raising chip by increasing basic unit is pressure；
And/or；
Described method also includes that the maximum by reducing basic unit n doping diffusion concentration raising chip is pressure.
Preferably, described method also includes that the radius bottom the doped region extremely corresponding by increasing C, B, E improves chip
Maximum pressure.
Preferably, described method also includes carrying by the input pole module of chip and/or output stage module are carried out cascade
The maximum of high chip is pressure.
Preferably, input pole module or the output stage module of cascade includes the transistor that at least three is sequentially connected, wherein
The colelctor electrode of previous transistor is connected with the emitter stage of next transistor.
Preferably, the epitaxy layer thickness of the chip of described method design is 14um, and groundwork thickness is 3um, and doping content is not
More than 2.2X10^15/ cubic centimetre, the least radius bottom doped region that C, B, E are extremely corresponding is 2um.
Preferably, described method is applied in standard bipolar technique or standard CMOS process.
Another aspect of the present invention additionally provides a kind of high-voltage tolerant chip, and the epitaxy layer thickness of described chip is 14um, basic unit
Thickness is 3um, and doping content is not more than 2.2X10^15/ cubic centimetre, the least radius bottom doped region that C, B, E are extremely corresponding
For 2um.
Preferably, the input pole module of described chip and/or output stage module are cascade circuit, and cascade circuit includes at least
Three transistors being sequentially connected, the colelctor electrode of the most previous transistor is connected with the emitter stage of next transistor.
Preferably, described chip uses standard bipolar technique or standard CMOS process manufacture.
Preferably, described chip is by above-mentioned high pressure resistant process design method manufacture.
Pass through the embodiment of the present invention, it is possible on the premise of not significantly improving cost, improve the high-voltage resistance capability of chip.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this
Some embodiments described in application, for those of ordinary skill in the art, in the premise not paying creative work
Under, it is also possible to other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the cross sectional representation of the NPN type chip that the present invention provides；
Fig. 2 is the cross sectional representation of the LPNP cake core that the present invention provides；
Fig. 3 is two transistor level connection compositions；
Fig. 4 is three transistor level connection compositions.
Detailed description of the invention
For the technical scheme making those skilled in the art be more fully understood that in the application, real below in conjunction with the application
Execute the accompanying drawing in example, the technical scheme in the embodiment of the present application is clearly and completely described, it is clear that described enforcement
Example is only some embodiments of the present application rather than whole embodiments.Based on the embodiment in the application, this area is common
The every other embodiment that technical staff is obtained under not making creative work premise, all should belong to the application protection
Scope.
As shown in Figure 1, 2, for NPN type chip and LPNP type cross sectional representation.We are with standard bipolar technique as base
Plinth, carries out technological design.In order to high pressure resistant, semiconductor technology must provide for the PN junction with high breakdown voltage, and this can lead to
The optimal control crossing the degree of depth to epitaxial layer, fillet (radius of the bottom of the doped region that B, C, E are extremely corresponding) and doping content comes
Obtain.The maximum of magnetic sensing chip is pressure, is that the MBV (BVcs) tied by epitaxial layer to substrate determines, this be by
Thickness at this is the deepest, doping content is minimum；And minimum pressure determined by epitaxial layer to base junction (BVcbo).Therefore,
Applied voltage should not exceed this breakdown voltage.Increase the thickness of epitaxial layer respectively, reduce its doping content, and increase base
Thickness, its doping content less, increase fillet, eventually through not increasing process layer, only existing technique be optimized
Under conditions of, it is thus achieved that high breakdown voltage.Analog information, does not increase extra mask cost, simply to epitaxial layer, basic unit
Thickness, doping content, fillet are optimized, and can improve voltage endurance capability to about 42V.
In one specific embodiment of the present invention, epitaxy layer thickness is 14um, and groundwork thickness is 3um, and doping content is less than
Equal to 2.2X10^15 every cubic centimetre, the least radius of C, B, E pole is 2um.The most both the pressure of 42V can have been met.
Certainly, the mode of above-mentioned optimization technique improves the resistance to certain limit that is pressed with: in input stage and the output stage of sensing chip
Module, owing to factor, short-term and the transient voltages such as coupling, electrostatic can be higher.Pressure in order to improve further, we devise level
The mode of connection, can improve the pressure of key modules, meet the needs of high added value.
As it is shown on figure 3, Q1 configures for collector/emitter, for 12 volts of systems, biasing Vbias#1 is set to power supply
The 30% of voltage, when powering 60V, Q1 bears 18V voltage, and Q2 bears 42V voltage.
Under 2u36V enhance technique, Q2 can work reluctantly.But when 80V, Q1 bears 24V voltage, and Q2 bears
56V voltage, Q2 is easy to breakdown.To this end, as shown in Figure 4, we add Q3 transistor for being distributed higher operation electricity
Pressure, to guarantee reliability, controllability and linear.The principle of cascade circuit is as it can be seen, high pressure can be distributed in multiple crystalline substance by it
On body pipe, biasing Vbias#1 is set to the 30% of supply voltage, and Vbias#2 is set to the 40% of supply voltage, when powering 80V,
Q3 pressure-bearing be 24V, Q2 pressure-bearing be 32V, Q1 maximum pressure-bearing be 24V, within 3 audions are all operated in place of safety.When same
When design is used in power supply 12V, within whole audions are still operated in respective linear zone, to guarantee that circuit is working properly.
To sum up, the invention provides a kind of high pressure resistant process design method, the method carries by increasing the thickness of epitaxial layer
The maximum of high chip is pressure.
Preferably, method also includes that the maximum by reducing epitaxial layer n doping diffusion concentration raising chip is pressure；
And/or；
Described method also includes that the maximum of the thickness raising chip by increasing basic unit is pressure；
And/or；
Described method also includes that the maximum by reducing basic unit n doping diffusion concentration raising chip is pressure.
Preferably, described method also includes that the radius bottom the doped region extremely corresponding by increasing C, B, E improves chip
Maximum pressure.
Preferably, described method also includes carrying by the input pole module of chip and/or output stage module are carried out cascade
The maximum of high chip is pressure.
Preferably, input pole module or the output stage module of cascade includes the transistor that at least three is sequentially connected, wherein
The colelctor electrode of previous transistor is connected with the emitter stage of next transistor.
Preferably, the epitaxy layer thickness of the chip of described method design is 14um, and groundwork thickness is 3um, and doping content is not
More than 2.2X10^15/ cubic centimetre, the least radius bottom doped region that C, B, E are extremely corresponding is 2um.
Preferably, described method is applied in standard bipolar technique or standard CMOS process.
Another aspect of the present invention additionally provides a kind of high-voltage tolerant chip, and the epitaxy layer thickness of described chip is 14um, basic unit
Thickness is 3um, and doping content is not more than 2.2X10^15/ cubic centimetre, the least radius bottom doped region that C, B, E are extremely corresponding
For 2um.
Preferably, the input pole module of described chip and/or output stage module are cascade circuit, and cascade circuit includes at least
Three transistors being sequentially connected, the colelctor electrode of the most previous transistor is connected with the emitter stage of next transistor.
Preferably, described chip uses standard bipolar Bipolar technique or standard CMOS process manufacture.
High pressure resistant technological design: optimized by processing simulation, on the basis of existing technique, proposes to increase extension thickness
Degree, on the basis of reducing epitaxial layer n doping diffusion concentration, in the case of not increasing chip cost, can be by existing bipolar
The pressure of technique brings up to 40V.It addition, further through the design cascaded at input and output side, can further improve pressure
To 80V or more than.
In a word, combined process optimization and the cascaded design of key component, the magnetic sensor chip that can make us is pressure
Significantly improve, the most do not dramatically increase the cost of chip.
Although depicting the application by embodiment, it will be appreciated by the skilled addressee that the application have many deformation and
Change is without deviating from spirit herein, it is desirable to appended claim includes that these deformation and change are without deviating from the application's
Spirit.
Claims (11)
1. a high pressure resistant process design method, it is characterised in that described method improves chip by increasing the thickness of epitaxial layer
Maximum pressure.
High pressure resistant process design method the most as claimed in claim 1, it is characterised in that
Described method also includes that the maximum by reducing epitaxial layer n doping diffusion concentration raising chip is pressure；
And/or；
Described method also includes that the maximum of the thickness raising chip by increasing basic unit is pressure；
And/or；
Described method also includes that the maximum by reducing basic unit n doping diffusion concentration raising chip is pressure.
High pressure resistant process design method the most as claimed in claim 2, it is characterised in that described method also include by increase C,
The maximum that the radius bottom doped region that B, E are extremely corresponding improves chip is pressure.
4. the high pressure resistant process design method as described in any one of claim 1-3, it is characterised in that described method also includes leading to
Cross and chip is inputted pole module and/or output stage module carries out cascade to improve the maximum of chip pressure.
High pressure resistant process design method the most as claimed in claim 4, it is characterised in that the input pole module of cascade or output stage
Module includes the transistor that at least three is sequentially connected, the emitter stage phase of the colelctor electrode of the most previous transistor and next transistor
Even.
6. the high pressure resistant process design method as described in any one in claim 1-3 or 5, it is characterised in that described method
The epitaxy layer thickness of the chip of design is 14um, and groundwork thickness is 3um, and doping content is not more than 2.2X10^15/ cubic centimetre,
The least radius bottom doped region that C, B, E are extremely corresponding is 2um.
7. the high pressure resistant process design method as described in any one in claim 1-3 or 5, it is characterised in that described method
Apply in standard bipolar technique or standard CMOS process.
8. a high-voltage tolerant chip, it is characterised in that the epitaxy layer thickness of described chip is 14um, groundwork thickness is 3um, doping
Concentration is not more than 2.2X10^15/ cubic centimetre, and the least radius bottom doped region that C, B, E are extremely corresponding is 2um.
9. high-voltage tolerant chip as claimed in claim 8, it is characterised in that the input pole module of described chip and/or output stage
Module is cascade circuit, and cascade circuit includes the transistor that at least three is sequentially connected, the colelctor electrode of the most previous transistor with
The emitter stage of next transistor is connected.
10. high-voltage tolerant chip as claimed in claim 8, it is characterised in that described chip uses standard bipolar technique or mark
Quasi-CMOS technology manufacture.
11. high-voltage tolerant chip as described in any one of claim 8-10, it is characterised in that described chip passes through claim 1-
High pressure resistant process design method manufacture described in 5 any one.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510364228 | 2015-06-29 | ||
| CN2015103642283 | 2015-06-29 |
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| CN106092151A true CN106092151A (en) | 2016-11-09 |
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Citations (7)
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| US20060043417A1 (en) * | 2004-08-30 | 2006-03-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| EP1193767A3 (en) * | 2000-09-28 | 2008-09-10 | Kabushiki Kaisha Toshiba | Insulated gate bipolar transistor and method of making the same |
| CN102194832A (en) * | 2011-05-16 | 2011-09-21 | 重庆大学 | Silicon on insulator (SOI) pressure resistant structure with interface lateral variation doping |
| CN102623491A (en) * | 2012-04-26 | 2012-08-01 | 杭州士兰集成电路有限公司 | High-voltage withstanding device in bipolar low-voltage process and manufacturing method thereof |
| CN102891088A (en) * | 2012-09-17 | 2013-01-23 | 电子科技大学 | Method for manufacturing vertical double diffusion metal oxide semiconductor field effect transistor device |
| CN103022006A (en) * | 2013-01-21 | 2013-04-03 | 贵州大学 | Epitaxy technology based three-dimensional integrated power semiconductor and manufacturing method thereof |
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2016
- 2016-06-17 CN CN201610436842.0A patent/CN106092151A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1341968A (en) * | 2000-09-07 | 2002-03-27 | 三洋电机株式会社 | Semiconductor integrated circuit device and manufacturing method thereof |
| EP1193767A3 (en) * | 2000-09-28 | 2008-09-10 | Kabushiki Kaisha Toshiba | Insulated gate bipolar transistor and method of making the same |
| US20060043417A1 (en) * | 2004-08-30 | 2006-03-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| CN102194832A (en) * | 2011-05-16 | 2011-09-21 | 重庆大学 | Silicon on insulator (SOI) pressure resistant structure with interface lateral variation doping |
| CN102623491A (en) * | 2012-04-26 | 2012-08-01 | 杭州士兰集成电路有限公司 | High-voltage withstanding device in bipolar low-voltage process and manufacturing method thereof |
| CN102891088A (en) * | 2012-09-17 | 2013-01-23 | 电子科技大学 | Method for manufacturing vertical double diffusion metal oxide semiconductor field effect transistor device |
| CN103022006A (en) * | 2013-01-21 | 2013-04-03 | 贵州大学 | Epitaxy technology based three-dimensional integrated power semiconductor and manufacturing method thereof |
Non-Patent Citations (1)
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Application publication date: 20161109 |