CN101764101B

CN101764101B - BCD integration process

Info

Publication number: CN101764101B
Application number: CN2008102078363A
Authority: CN
Inventors: 永福; 龚大卫; 陈雪萌; 吕宇强
Original assignee: Shanghai Advanced Semiconductor Manufacturing Co Ltd
Current assignee: Shanghai Advanced Semiconductor Manufacturing Co Ltd
Priority date: 2008-12-25
Filing date: 2008-12-25
Publication date: 2012-05-23
Anticipated expiration: 2028-12-25
Also published as: CN101764101A

Abstract

The invention discloses a BCD integration process, which is characterized by adding a groove photoetching step after a partial oxide isolation step. In regard to a DMOS device in the BCD integration process, an oxide and a nitride formed in the partial oxide isolation step are used as barrier layers in the groove photoetching step, a gate oxide layer grows in a formed groove, and a polysilicon filling groove is deposited; and in regard to a bipolar device in the BCD integration process, and tungsten is filled into the groove formed in the groove photoetching step to form a collector region of the bipolar device. The BCD integration process can multiply enhance the properties of the DMOS device and a bipolar transistor, furthest develops the advantages of a BCD process, and has fewer additional process steps.

Description

The BCD integrated technique

Technical field

The present invention relates to semiconductor fabrication process, more particularly, relate to a kind of BCD integrated technique.

Background technology

BCD is a kind of monolithic integrated technique technology, and this technology can be made bipolar transistor (Bipolar Junction Transistor), CMOS and DMOS device on same chip.BCD technology not only combines the advantage of bipolar device high transconductance, strong load driving ability and the high and low power consumption of CMOS integrated level, and has integratedly advanced the very fast DMOS power device of switching speed.Because DMOS has at a high speed the characteristic with big current capacity simultaneously, and is withstand voltage also higher usually, thereby to be operated in the power management chip of BCD technology manufacturing be under high frequency, high pressure and the big electric current, is the desirable technology of manufacturing high-performance power supply chip.Adopt the monolithic integrated chip of BCD technology manufacturing can also improve systematic function, save the encapsulation overhead of circuit, and have better reliability.The main application fields of BCD technology is fields such as power management (power supply and battery control), display driver, automotive electronics, Industry Control.Because the continuous expansion of the application of BCD technology, to BCD technology require increasingly high.Recently, BCD technology is mainly towards high pressure, high power, high density direction differentiation development.

The DMOS device is a most important power-ourput device in the BCD technology, usually in chip, has taken the area about half, thus optimize the DMOS structure with technology so that the lower DMOS conducting resistance of acquisition is the improvement direction of BCD technology always.DMOS is a planar structure in the BCD technology of current popular, and surface channel has wherein not only been occupied suitable large tracts of land, and causes the JFET (junction field effect transistor) that has a series connection in the current path of DMOS, thereby has increased conducting resistance.

Bipolar device is an important analogue signal processor spare in the BCD technology, thus optimize bipolar transistor structure with technology so that bigger current capacity of acquisition and the cut-off frequency of Geng Gao are one of improvement directions of BCD technology always.Bipolar transistor is mostly drawn its each electrode for the isolation of pn knot with through injecting method of diffusion in the BCD technology of current popular; Collector electrode has wherein not only been occupied suitable large tracts of land; And cause the increase of bipolar transistor collector series resistance, thereby reduced cut-off frequency.

Summary of the invention

The present invention proposes a kind of BCD integrated technique, has comprised the technology of making groove DMOS and vertical bipolar device in this integrated technique.

According to embodiments of the invention, a kind of BCD integrated technique is provided, after the carrying out local oxide isolation step, increase the trench lithography step;

For the DMOS device in the BCD integrated technique, this trench lithography step utilizes the oxide that forms in the carrying out local oxide isolation step and nitride as the barrier layer, in the groove that forms, grow grid oxic horizon and deposit polysilicon filling groove;

For the bipolar device in the BCD integrated technique, in the groove that this trench lithography step forms, fill the collector region that tungsten forms bipolar device.

For the DMOS device, the technology of making the DMOS device comprises: form n type buried layer at substrate; Growth N type epitaxial loayer; Carry out carrying out local oxide isolation; Carry out trench lithography; Growth sacrificial oxide layer and corrode sacrificial oxide layer in the groove that forms; The grid oxic horizon of in the groove that forms, growing; Deposit polysilicon filling groove; Use the in-situ doped or method injected of polysilicon to polysilicon doping.

Wherein, n type buried layer is through on substrate, injecting arsenic or antimony formation.The sacrificial oxide layer of growth

in the groove that forms, and use this sacrificial oxide layer of wet etching.The thickness of growth grid oxic horizon is confirmed according to threshold voltage and the puncture voltage of DMOS in the groove that forms.

For the drain region of DMOS, after forming groove, in groove, fill tungsten.

For bipolar device, the technology of making bipolar device comprises: on substrate, form n type buried layer; Growth N type epitaxial loayer; Carry out carrying out local oxide isolation; The n/p trap that carries out CMOS technology is made, source-drain area injects; Utilize the base of the n/p trap of CMOS technology as said vertical bipolar device; The source-drain area that CMOS technology is carried out in utilization injects the making heavily doped region, and heavily doped region is as the emitter region and the base of vertical bipolar device.

Wherein, n type buried layer is to carry out through injection arsenic or antimony on substrate.

The n trap of CMOS technology is as the base of vertical PNP devices; The p trap of CMOS technology is as the base of vertical NPN device.

Also comprise the formation p type buried layer in this BCD integrated technique, the DMOS that makes in the BCD integrated technique, CMOS and bipolar device are isolated through p type buried layer and groove.

BCD integrated technique of the present invention can increase exponentially the performance of DMOS and bipolar transistor, farthest brings into play the advantage of BCD technology, and additional processing step is also less.

Description of drawings

Above-mentioned and other characteristic, character and advantage of the present invention will become more obvious through the description below in conjunction with accompanying drawing and embodiment, in the accompanying drawings, identical Reference numeral is represented identical characteristic all the time, wherein:

Fig. 1-Fig. 5 has disclosed the technical process according to the BCD integrated technique of one embodiment of the invention.

Embodiment

The present invention proposes a kind of BCD integrated technique, comprising making the technology of groove DMOS and vertical bipolar device.For the technical process aspect, change mainly comprises:

After the carrying out local oxide isolation step, increase the trench lithography step;

Further, for the DMOS device, the technology of making the DMOS device comprises: form n type buried layer at substrate; Growth N type epitaxial loayer; Carry out carrying out local oxide isolation; Carry out trench lithography; Growth sacrificial oxide layer and corrode sacrificial oxide layer in the groove that forms; The grid oxic horizon of in the groove that forms, growing; Deposit polysilicon filling groove; Use the in-situ doped or method injected of polysilicon to polysilicon doping.

Wherein, n type buried layer is through on substrate, injecting arsenic or antimony formation.

For sacrificial oxide layer; The sacrificial oxide layer of growth

in groove, and use this sacrificial oxide layer of wet etching.

For grid oxic horizon, the thickness of growth grid oxic horizon is confirmed according to threshold voltage and the puncture voltage of DMOS in groove.

The drain region of DMOS is after forming groove, in groove, fills tungsten.

For bipolar device, the technology of making bipolar device comprises: on substrate, form n type buried layer; Growth N type epitaxial loayer; Carry out carrying out local oxide isolation; The n/p trap that carries out CMOS technology is made, source-drain area injects; Utilize the base of the n/p trap of CMOS technology as vertical bipolar device; The source-drain area that CMOS technology is carried out in utilization injects the making heavily doped region, and heavily doped region is as the emitter region and the base of vertical bipolar device.

This BCD integrated technique also comprises the formation p type buried layer, and the DMOS that makes in the BCD integrated technique, CMOS and bipolar device are isolated through p type buried layer and groove.

With reference to figure 1-Fig. 5, disclosed technical process according to the BCD integrated technique of one embodiment of the invention.

BCD technology can integrated multiple DMOS power device and bipolar device, such as LDMOS, VDMOS and groove (Trench) DMOS, and horizontal and vertical bipolar transistor.This patent mainly proposes groove (Trench) DMOS and the manufacturing process of vertical bipolar device in a kind of BCD of being integrated in technology.On the BCD of standard integrated technique, increase by 3 lithography steps and just can accomplish groove (Trench) DMOS and vertical bipolar device, and technology and Bipolar/CMOS device technology compatibility fully.

At first, at substrate, upward form n type buried layer BNL through injecting arsenic As or antimony Sb such as P substrate P-Sub.

Inject boron and form p type buried layer BP, p type buried layer BP plays and isolates each device, such as the effect of DMOS, CMOS and bipolar device.

The N type of growing afterwards epitaxial loayer N-EPI; N type epitaxial loayer N-EPI is used to reduce the resistance of DMOS drain terminal and the resistance of double pole triode collector region, by the source drain breakdown voltage of groove (Trench) DMOS and thickness and the resistivity of conducting resistance decision N type epitaxial loayer N-EPI.Carry out the carrying out local oxide isolation LOCOS of CMOS technology after the making of completion N type epitaxial loayer N-EPI, simultaneously, form nitride/oxide layer Oxide/Nitride on the surface of silicon chip.The structure that forms is as shown in Figure 1.

Behind the carrying out local oxide isolation that the completes LOCOS; Carry out the trench lithography step,, utilize silicon dioxide layer and silicon nitride in the carrying out local oxide isolation LOCOS technology as the barrier layer of etching groove for the DMOS device; Through reactive ion etching groove Trench, form structure as shown in Figure 2.

After etching silicon dioxide layer and the silicon nitride barrier; The sacrificial oxide layer of growth

in groove Trench; And through this sacrificial oxide layer of wet etching, the process of growth and corrosion sacrificial oxide layer can be eliminated the pickup and the stress that possibly exist in the etching groove process.Grow the then grid oxic horizon Gate-Oxide of DMOS, the thickness of grid oxic horizon is decided by threshold voltage and the puncture voltage of DMOS.Deposit polysilicon Poly comes filling groove Trench then, forms the grid of DMOS.The polysilicon gate of DMOS is that method in-situ doped by polysilicon or that inject is come impurity, reduces its resistivity.In order to draw the grid polycrystalline silicon of DMOS, increase by the grid photoetching of one DMOS.The grid of DMOS is to connect on the polysilicon on the oxygen on the scene, and structure is as shown in Figure 3.

The mutual isolation of DMOS, bipolar device and CMOS is to realize jointly through p type buried layer BP and groove Trench, can further reduce the area of plane that needs owing to isolation like this.

The P type body p-body/ base of DMOS/ bipolar transistor and the formation of source region/emitter region (such as forming doped region P+, N+) fully can be compatible with the manufacture craft in p trap, n trap and the source/drain region of CMOS, and the structure of formation is as shown in Figure 4.Behind the grid polycrystalline silicon of DMOS, proceed the manufacture craft of CMOS so complete.

Among the present invention, the drain region of DMOS and the collector region of bipolar transistor are through etching groove Trench, fill then that tungsten Tungsten forms, and structure is as shown in Figure 5.Inject drain region and the collector region that diffusion forms compared with traditional passing through, the advantage of this structure is that the area that laterally occupies is little, and resistivity is low, thus higher performance the performance of groove DMOS and vertical bipolar transistor.

The foregoing description provides to being familiar with personnel in this area and realizes or use of the present invention; Being familiar with those skilled in the art can be under the situation that does not break away from invention thought of the present invention; The foregoing description is made various modifications or variation; Thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.

Claims

1. a BCD integrated technique is characterized in that, after the carrying out local oxide isolation step, increases the trench lithography step;

For the DMOS device in the BCD integrated technique; This trench lithography step utilizes the oxide that forms in the carrying out local oxide isolation step and nitride as the barrier layer; The grid oxic horizon of in the groove that forms, growing, and deposit polysilicon filling groove are as the grid of said DMOS device; After forming groove, fill tungsten therein, as the drain region of said DMOS device;

For the bipolar device in the BCD integrated technique, in the groove that this trench lithography step forms, fill the collector region that tungsten forms said bipolar device.

2. BCD integrated technique as claimed in claim 1 is characterized in that, for the DMOS device, the technology of making the DMOS device comprises:

Form n type buried layer at substrate;

Growth N type epitaxial loayer;

Carry out carrying out local oxide isolation;

Carry out trench lithography;

Growth sacrificial oxide layer and corrode sacrificial oxide layer in the groove that forms;

The grid oxic horizon of in the groove that forms, growing;

Deposit polysilicon filling groove;

Use the in-situ doped or method injected of polysilicon to polysilicon doping.

3. BCD integrated technique as claimed in claim 2 is characterized in that,

N type buried layer is through on substrate, injecting arsenic or antimony formation.

4. BCD integrated technique as claimed in claim 2 is characterized in that,

The sacrificial oxide layer of growth

in the groove that forms, and use this sacrificial oxide layer of wet etching.

5. BCD integrated technique as claimed in claim 2 is characterized in that,

The thickness of growth grid oxic horizon is confirmed according to threshold voltage and the puncture voltage of DMOS in the groove that forms.

6. BCD integrated technique as claimed in claim 1 is characterized in that, for bipolar device, the technology of making bipolar device comprises:

On substrate, form n type buried layer;

Growth N type epitaxial loayer;

Carry out carrying out local oxide isolation;

The n/p trap that carries out CMOS technology is made, source-drain area injects;

Utilize the base of the n/p trap of CMOS technology as said vertical bipolar device;

The source-drain area that CMOS technology is carried out in utilization injects the making heavily doped region, and heavily doped region is as the emitter region and the base of vertical bipolar device.

7. BCD integrated technique as claimed in claim 6 is characterized in that,

N type buried layer is to carry out through injection arsenic or antimony on substrate.

8. BCD integrated technique as claimed in claim 6 is characterized in that,

The n trap of said CMOS technology is as the base of vertical PNP devices;

The p trap of said CMOS technology is as the base of vertical NPN device.

9. BCD integrated technique as claimed in claim 1 is characterized in that, also comprises:

Form p type buried layer, DMOS, CMOS and the bipolar device made in the said BCD integrated technique are isolated through p type buried layer and groove.