CN101764099A - Groove DMOS manufacture process compatible with BCD integrated process - Google Patents

Abstract

The invention discloses a groove DMOS manufacture process compatible with a BCD integrated process. A groove-photoetching step is added after a partial oxidation and separation step and utilizes oxide and nitride which are formed in the partial oxidation and separation step as a barrier layer; a grid oxidation layer is grown in the formed groove; a polysilicon-filling groove is deposited; and then, the rest steps in the BCD integrated process are continued. The groove DMOS manufacture process integrated in the BCD process can exponentially decrease the on-resistance of a DMOS device, and the accessional process steps are less.

Description

Groove DMOS manufacture process with BCD integrated technique compatibility

Technical field

The present invention relates to semiconductor fabrication process, more particularly, relate to the DMOS manufacturing process in the BCD integrated technique.

Background technology

BCD is a kind of monolithic integrated technique technology, and this technology can be made bipolar transistor (Bipolar Junction Transistor), CMOS and DMOS device on same chip.BCD technology not only combines the advantage of bipolar device high transconductance, strong load driving ability and the high and low power consumption of CMOS integrated level, and has integratedly advanced the very fast DMOS power device of switching speed.Because DMOS has at a high speed simultaneously and the characteristic of big current capacity, and is withstand voltage also higher usually, thereby to be operated in the power management chip of BCD technology manufacturing be under high frequency, high pressure and the big electric current, is the desirable technology of manufacturing high-performance power supply chip.Adopt the monolithic integrated chip of BCD technology manufacturing can also improve systematic function, save the encapsulation overhead of circuit, and have better reliability.The main application fields of BCD technology is fields such as power management (power supply and battery control), display driver, automotive electronics, Industry Control.Because the continuous expansion of the application of BCD technology is more and more higher to the requirement of BCD technology.Recently, BCD technology mainly develops towards high pressure, high power, high density direction.

The DMOS device is a most important power-ourput device in the BCD technology, has usually taken the area about half in chip, thereby optimizes the DMOS structure and technology is the improvement direction of BCD technology so that obtain lower DMOS conducting resistance always.DMOS is a planar structure in the current BCD technology, and surface channel has wherein not only been occupied suitable large tracts of land, and makes the JFET (junction field effect transistor) that has a series connection in the current path of DMOS, thereby has increased conducting resistance.

Summary of the invention

The present invention aims to provide the groove DMOS manufacture process in a kind of BCD of being integrated in technology, and it can reduce the conducting resistance of DMOS device at double, and additional processing step is also less.

According to embodiments of the invention, disclosed a kind of and groove DMOS manufacture process BCD integrated technique compatibility,

Increase the trench lithography step after the carrying out local oxide isolation step, this trench lithography step utilizes the oxide that forms in the carrying out local oxide isolation step and nitride as the barrier layer;

The grid oxic horizon of in the groove that forms, growing;

Deposit polysilicon filling groove;

Proceed all the other steps in the BCD integrated technique afterwards.

According to an embodiment, comprise at this groove DMOS manufacture process:

Form n type buried layer at substrate;

Growth N type epitaxial loayer;

Carry out carrying out local oxide isolation;

Carry out trench lithography;

Growth sacrificial oxide layer and corrode sacrificial oxide layer in the groove that forms;

The grid oxic horizon of in the groove that forms, growing;

Deposit polysilicon filling groove;

Use the in-situ doped or method injected of polysilicon to polysilicon doping;

Continue the CMOS manufacture craft in the BCD integrated technique.

Wherein, n type buried layer is by inject arsenic or antimony formation on substrate.

In the groove that forms, grow

Sacrificial oxide layer, and use this sacrificial oxide layer of wet etching.

The thickness of growth grid oxic horizon is determined according to the threshold voltage and the puncture voltage of groove DMOS in the groove that forms.

For the drain region of groove DMOS, after forming groove, in groove, fill tungsten.

Groove DMOS manufacture process in the BCD of the being integrated in technology of the present invention can reduce the conducting resistance of DMOS device at double, and additional processing step is also less.

Description of drawings

The above and other features of the present invention, character and advantage will become more obvious by the description below in conjunction with drawings and Examples, in the accompanying drawings, identical Reference numeral is represented identical feature all the time, wherein:

Fig. 1-Fig. 5 has disclosed the technical process according to the groove DMOS manufacture process of one embodiment of the invention;

Fig. 6 has disclosed the structure of the groove DMOS that the groove DMOS manufacture process manufacturing according to one embodiment of the invention obtains.

Embodiment

BCD technology can integrated multiple DMOS power device, such as LDMOS, VDMOS and groove (Trench) DMOS, and main LDMOS and the VDMOS of using in high pressure BCD technology.Yet Trench DMOS is because its superior current handling capability has more attraction to high power BCD technology.But the particularity of Trench DMOS manufacture craft with poor more than LDMOS and VDMOS of the compatibility of CMOS technology, but does not also have the BCD technology that contains groove DMOS of volume production so far.

The invention provides the Trench DMOS manufacturing process in a kind of BCD of being integrated in technology.On the BCD of standard integrated technique, only increase a little step and just can finish this novel Trench DMOS, and technology and Bipolar/CMOS device technology are compatible fully.Set forth an embodiment of its manufacture craft below in conjunction with Fig. 1-Fig. 6:

At first, form n type buried layer BNL by injecting arsenic As or antimony Sb in that substrate (P type substrate) P-Sub is last, be used to reduce DMOS drain terminal resistance and NPN collector region resistance.The N type of growing then epitaxial loayer N-EPI is by the source drain breakdown voltage of Trench DMOS and thickness and the resistivity of conducting resistance decision N type epitaxial loayer N-EPI.Finish the carrying out local oxide isolation LOCOS that carries out CMOS technology after the making of N type epitaxial loayer N-EPI, simultaneously, formed after the oxide/nitride layer Oxide/Nitride above-mentioned steps structure as shown in Figure 1.

Behind the carrying out local oxide isolation that the completes LOCOS, increase the distinctive groove Trench of step Trench DMOS lithography step, in this trench lithography step, utilizing the oxide/nitride layer Oxide/Nitride that forms in the carrying out local oxide isolation technology, is the barrier layer of silicon dioxide layer/silicon nitride layer as groove Trench etching in this embodiment.The step of groove Trench etching forms structure as shown in Figure 2 by reactive ion etching groove Trench.

Behind etching silicon dioxide layer/silicon nitride layer barrier layer, in groove Trench, grow

Sacrificial oxidation eliminate the pickup in the etching groove process and the stress that may exist, afterwards, use wet etching sacrificial oxide layer (as silicon dioxide layer).After finishing the step of growth and corrosion sacrificial oxide layer, the grid oxic horizon Gate Oxide of growth Trench DMOS in groove Trench, the thickness of grid oxic horizon Gate Oxide is decided by threshold voltage and the puncture voltage of Trench DMOS.Deposit polysilicon Poly filling groove Trench then forms the grid of Trench DMOS.Poly returns quarter by polysilicon, etches away the polysilicon Poly of silicon chip plane domain, and the structure of formation as shown in Figure 3.

The polysilicon gate of Trench DMOS can method in-situ doped by polysilicon or that inject come impurity, to reduce its resistivity.The grid of Trench DMOS also is to draw by the polysilicon in the groove Trench, thereby can save the lithography step of Trench DMOS polycrystalline grid, and the structure of formation as shown in Figure 5.

The p district main body p-body of Trench DMOS and the formation in source/drain region fully can with the p trap of CMOS and the manufacture craft compatibility in source/drain region, the structure of formation is as shown in Figure 4.Behind the grid polycrystalline silicon of Trench DMOS, then carry out the manufacture craft of the CMOS in the BCD integrated technique so complete.

According to the present invention, the drain region formation method of Trench DMOS is as follows: at first (can fill the drain region that tungsten Tungsten forms Trench DMOS then with other groove Trench etching, structure as shown in Figure 5 for etching groove Trench.Inject the drain region that diffusion forms compared with traditional passing through, the advantage in the drain region of this structure is that the area that laterally occupies is little, and resistivity is low, thus higher performance the superior current handling capability of Trench DMOS.

The structure of the groove DMOS that groove DMOS manufacture process manufacturing according to the present invention obtains can be with reference to shown in Figure 6.

Groove DMOS manufacture process in the BCD of the being integrated in technology of the present invention can reduce the conducting resistance of DMOS device at double, and additional processing step is also less.

The foregoing description provides to being familiar with the person in the art and realizes or use of the present invention; those skilled in the art can be under the situation that does not break away from invention thought of the present invention; the foregoing description is made various modifications or variation; thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.

Claims (6)

1. the groove DMOS manufacture process with BCD integrated technique compatibility is characterized in that,

Increase the trench lithography step after the carrying out local oxide isolation step, this trench lithography step utilizes the oxide that forms in the carrying out local oxide isolation step and nitride as the barrier layer;

The grid oxic horizon of in the groove that forms, growing;

Deposit polysilicon filling groove;

Proceed all the other steps in the BCD integrated technique afterwards.

2. the groove DMOS manufacture process of as claimed in claim 1 and BCD integrated technique compatibility is characterized in that this technology comprises:

Form n type buried layer at substrate;

Growth N type epitaxial loayer;

Carry out carrying out local oxide isolation;

Carry out trench lithography;

Growth sacrificial oxide layer and corrode sacrificial oxide layer in the groove that forms;

The grid oxic horizon of in the groove that forms, growing;

Deposit polysilicon filling groove;

Use the in-situ doped or method injected of polysilicon to polysilicon doping;

Continue the CMOS manufacture craft in the BCD integrated technique.

3. the groove DMOS manufacture process of as claimed in claim 2 and BCD integrated technique compatibility is characterized in that,

N type buried layer is by inject arsenic or antimony formation on substrate.

4. the groove DMOS manufacture process of as claimed in claim 2 and BCD integrated technique compatibility is characterized in that,

In the groove that forms, grow Sacrificial oxide layer, and use this sacrificial oxide layer of wet etching.

5. the groove DMOS manufacture process of as claimed in claim 2 and BCD integrated technique compatibility is characterized in that,

The thickness of growth grid oxic horizon is determined according to the threshold voltage and the puncture voltage of groove DMOS in the groove that forms.

6. the groove DMOS manufacture process of as claimed in claim 2 and BCD integrated technique compatibility is characterized in that,

For the drain region of groove DMOS, after forming groove, in groove, fill tungsten.

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