CN112509982A

CN112509982A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN112509982A
Application number: CN201910867623.1A
Authority: CN
Inventors: 王昊; 陈洪雷; 夏志平; 姚国亮; 陈伟
Original assignee: Hangzhou Shilan Jixin Microelectronics Co ltd
Current assignee: Hangzhou Shilan Jixin Microelectronics Co ltd
Priority date: 2019-09-13
Filing date: 2019-09-13
Publication date: 2021-03-16

Abstract

The application discloses a semiconductor device and a method of manufacturing the same. The manufacturing method comprises the steps of forming a first gate stack and a second gate stack on a first well region, a second well region and a fourth well region of a substrate respectively, and forming a third gate stack on a third well region and a fourth well region of the substrate; forming a first source region and a first drain region of a second doping type in the first well region and forming a third source region and a third drain region of the second doping type in the third well region and the fourth well region by using a photoresist mask and using the first gate stack and the third gate stack as hard masks; and when the second source region and the second drain region are formed, the second doping type dopants of the first source region and the first drain region, and the third source region and the third drain region are compounded with the first doping type dopants. The method saves additional mask and photoetching steps when forming the second source region and the second drain region, does not affect the performance of the semiconductor device, and can reduce the manufacturing cost.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

The BCD (Bipolar-CMOS-DMOS) process can integrate diodes, CMOS (complementary metal oxide semiconductor) tubes, DMOS tubes, LDMOS tubes with various breakdown voltages, triodes, resistors and other devices into a same single chip, and the BCD device has the advantages of low power loss, high system performance, good stability, popularity in the fields of automobile electronics, power management, display driving and the like and wide market prospect.

The traditional BCD process simultaneously provides devices such as MOS tubes, diodes, triodes, resistors and the like, generally needs multiple mask and photoetching steps, and is complex in process and high in cost.

Accordingly, there is a need for a semiconductor device and a method of manufacturing the same that reduces masking and lithography operations and does not affect the performance of the semiconductor device.

Disclosure of Invention

In view of the above, the present application provides a semiconductor device and a method for manufacturing the same.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a first gate stack on a first well region of a first region of a substrate, the first well region being of a first doping type; forming a second gate stack over a second well region of a first region of a substrate, the second well region being of a second doping type, the first doping type being opposite to the second doping type, the first well region and the second well region being adjacent to each other; forming a third gate stack on a third well region and a fourth well region of a second region of the substrate, the third well region being of a second doping type, the fourth well region being of a first doping type, the fourth well region being located in the third well region, the first region and the second region being adjacent to each other; respectively forming a first source region and a first drain region of a second doping type in the first well region by using a photoresist mask and the first gate stack and the third gate stack as hard masks, forming a third drain region of the second doping type in the third well region, and forming a third source region of the second doping type in the fourth well region; and removing the photoresist mask, and performing normal injection to form a second source region and a second drain region of the first doping type in the second well region, wherein in the step of forming the second source region and the second drain region, the second doping type dopant in the first source region and the first drain region and in the third source region and the third drain region is compounded with the first doping type dopant, and equivalent dopants of the first source region and the first drain region and the third source region and the third drain region are maintained as the second doping type.

Preferably, the dopant amount of the dopant of the second doping type forming the first source region and the first drain region and the third source region and the third drain region is higher than the dopant amount of the dopant of the first doping type forming the second source region and the second drain region, so that the first source region and the first drain region and the third source region and the third drain region form ohmic contacts.

Preferably, after the step of forming the second source region and the second drain region, the method further includes: forming an interlayer dielectric layer on the first gate stack, the second gate stack and the third gate stack; forming a plurality of channel holes which penetrate through the interlayer dielectric layer and at least respectively reach the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region; and filling the plurality of via holes with a conductive material to form a plurality of conductive vias.

Preferably, after the conductive channel is formed, portions of the first source and drain regions exposed by the channel hole and in contact with the conductive channel serve as first source and drain ohmic contact regions, and portions of the third source and drain regions exposed by the channel hole and in contact with the conductive channel serve as third source and drain ohmic contact regions.

Preferably, between the steps of forming the channel hole and the conductive channel, further comprising: and implanting a first doping type dopant by using the plurality of channel holes as an implantation channel, and forming a second source ohmic contact region and a second drain ohmic contact region in the second well region, wherein the first source region and the first drain region are compounded with the first doping type dopant of the third source region and the third drain region, the equivalent dopant of the first source ohmic contact region and the equivalent dopant of the first drain region, which are exposed through the channel holes, of the first source region and the first drain region are maintained as the second doping type, and the equivalent dopant of the third source region and the third drain region, which are exposed through the channel holes, of the third source ohmic contact region and the third drain region are maintained as the second doping type.

Preferably, the method further comprises the following steps: in the step of forming the second source region and the second drain region, a first channel region of the first doping type is formed in the fourth well region, and a second channel region of the first doping type is formed in a fifth well region of the first doping type in the second region of the substrate, the fifth well region and the third well region being adjacent to each other.

Preferably, the plurality of via holes include via holes penetrating through the interlayer dielectric layer to reach the first channel region and the second channel region, respectively, and in the step of forming the second source ohmic contact region and the second drain ohmic contact region, a first channel contact region of the first doping type is formed in the first channel region, and a second channel contact region of the first doping type is formed in the second channel region.

Preferably, the method further comprises the following steps: forming a first doped region of a second doping type in the substrate in the step of forming the first source region and the first drain region and the third source region and the third drain region; in the step of forming the second source region and the second drain region, a second doping region of the first doping type extending outwards is formed in a sixth well region of the first region of the substrate, and a fourth doping region of the first doping type is formed in the sixth well region, the second doping region is in contact with the first doping region to form a PN structure, the sixth well region is adjacent to the second well region, the sixth well region is of the first doping type, dopants of the second doping type of the first doping region are combined with dopants of the first doping type, and equivalent dopants of the first doping region are maintained as the second doping type.

Preferably, the plurality of channel holes include channel holes penetrating through the interlayer dielectric layer to reach the first doped region and the fourth doped region, respectively, after the conductive channel is formed, a portion of the first doped region exposed by the channel hole and in contact with the conductive channel is used as a first doped contact region, in the step of forming the second source ohmic contact region and the second drain ohmic contact region, a fourth doped contact region is formed in the fourth doped region, a portion of the dopant of the second doping type in the first doped region is combined with the dopant of the first doping type, and an equivalent dopant of the first doped contact region in the first doped region is maintained as the second doping type.

Preferably, the method further comprises the following steps: in the step of forming the second source region and the second drain region, a third doped region of the first doping type is formed in a seventh well region of the second doping type of the first region of the substrate to form a body resistor, the seventh well region and a sixth well region in the first region being adjacent to each other.

Preferably, the first gate stack, the second gate stack, and the third gate stack respectively include a gate conductor and a gate dielectric, the gate dielectric is located between the gate conductor and the substrate, the gate conductor is a polysilicon layer, and an equivalent dopant of the gate conductor in the semiconductor device is a first doping type or a second doping type.

Preferably, in the process of forming the first gate stack, the second gate stack and the third gate stack, the gate conductor is polysilicon of a second doping type; in the process of forming the second source region and the second drain region, the second doping type dopant in the gate conductor is combined with the first doping type dopant; the plurality of channel holes include at least one channel hole penetrating through the interlayer dielectric layer to reach the gate conductor, and in the step of forming the second source ohmic contact region and the second drain ohmic contact region, the dopant of the second doping type of the gate conductor is combined with the dopant of the first doping type, and the equivalent dopant of the gate conductor is maintained to be the second doping type.

Preferably, in the process of forming the first gate stack, the second gate stack and the third gate stack, the gate conductor is polysilicon of a first doping type, and in the process of forming the first source region, the first drain region, the third source region and the third drain region, at least a dopant of the first doping type in the gate conductor in the first gate stack is combined with a dopant of a second doping type; in the process of forming the second source region and the second drain region, the dopant of the first doping type is injected into the gate conductor; the plurality of channel holes comprise at least one channel hole penetrating through the interlayer dielectric layer to reach the gate conductor, and in the step of forming the second source ohmic contact region and the second drain ohmic contact region, the first doping type dopant is injected into the gate conductor, and the equivalent dopant of the gate conductor is maintained to be the first doping type.

Preferably, before the step of forming the first gate stack, the second gate stack and the third gate stack, the method further includes: forming the second well region and a seventh well region of a second doping type in a first region of the substrate, and forming the third well region of the second doping type in a second region of the substrate; forming a first well region and a sixth well region of a first doping type in a first region of the substrate, and forming a fourth well region and a fifth well region of the first doping type in a second region of the substrate, wherein the well regions in the first region are arranged in parallel, the third well region and the fifth well region in the second region are adjacent to each other, and the fourth well region is located in the third well region; forming isolation structures extending downward from the substrate surface between adjacent well regions, the isolation structures serving as part of the hard mask in the step of forming the first source and first drain regions, the second source and second drain regions, and the third source and third drain regions.

Preferably, the forming of the well region of the first doping type includes: forming an active region in a first region and a second region on the substrate using a first photoresist mask; removing the first photoresist mask, shielding at least a part of the substrate, which forms the well region of the second doping type, by using a second photoresist mask, forming a first well region and a sixth well region of the first doping type in the first region of the substrate, and forming a fourth well region and a fifth well region of the first doping type in the second region of the substrate; and shielding by adopting the second photoresist mask, forming a compensation region of the first doping type on part of the surface of the well region of the first doping type by adopting the active region as a hard mask, and then removing the second photoresist mask, wherein in the process of forming the isolation structure, the active region is used as a part of the hard mask, and then the active region is removed.

Preferably, the forming of the well region of the second doping type and the well region of the first doping type includes: forming an active region in a first region and a second region on the substrate using a first photoresist mask; removing the first photoresist mask, adopting a third photoresist mask for shielding so as to form the second well region and a seventh well region of a second doping type in the first region of the substrate, and form the third well region of the second doping type in the second region of the substrate, and then removing the third photoresist mask; shielding at least a part of the substrate where the well region of the second doping type is formed by using a second photoresist mask, forming a first well region and a sixth well region of the first doping type in the first region of the substrate, and forming a fourth well region and a fifth well region of the first doping type in the second region of the substrate; and shielding by adopting the second photoresist mask, forming a compensation region of the first doping type on part of the surface of the well region of the first doping type by adopting the active region as a hard mask, and then removing the second photoresist mask, wherein in the process of forming the isolation structure, the active region is used as a part of the hard mask, and then the active region is removed.

Preferably, the implantation energy of the dopant of the first doping type forming the well region of the first doping type is such that the dopant is able to penetrate the active region.

Preferably, the implantation energy of the dopant of the first doping type implanted when forming the compensation region is such that the dopant is not able to penetrate the active region.

Preferably, the method further comprises the following steps: in the step of forming the isolation structure, a field oxide region extending downward is formed on a surface in the third well region, a surface of the fourth well region, and a surface of the sixth well region.

Preferably, the method further comprises the following steps: in the step of forming the first gate stack, the second gate stack, and the third gate stack, a fourth gate stack is formed on the field oxide region to serve as a field plate, and the third gate stack includes a portion that is at least on the field oxide region to serve as a field plate.

Preferably, the isolation structure includes at least one of a field oxide region and a trench isolation.

Preferably, the first doping type is P-type, and the second doping type is N-type.

According to another aspect of the present invention, there is provided a semiconductor device including: a substrate; the semiconductor device comprises a first well region and a fourth well region, wherein the first well region and the second well region are located in a first region of a substrate and are of a first doping type, the third well region and the fourth well region are located in a second region of the substrate and are of a second doping type and a first doping type, the first doping type is opposite to the second doping type, the first region and the second region are adjacent to each other, the first well region and the second well region are adjacent to each other, and the fourth well region is located in the third well region; a first gate stack over the first well region, a second gate stack over the second well region, and a third gate stack over the third well region and the fourth well region; the semiconductor device comprises a first source region and a first drain region of a second doping type, a second source region and a second drain region of the first doping type, a third source region and a third drain region of the second doping type, wherein the first source region and the first drain region are located in the first well region, the second source region and the second drain region of the first doping type are located in the second well region, the third source region and the third drain region of the second doping type are located in the third well region and the fourth well region, the second doping type dopants of the first source region and the first drain region are compounded with the first doping type dopants of the second source region and the second drain region, and the second doping type dopants of the third source region and the third drain region are compounded with the first doping type dopants of the second source region and the second drain region.

Preferably, the second drain region and the second source region have the same dopant amount.

Preferably, the method further comprises the following steps: the interlayer dielectric layer is positioned above the first gate stack, the second gate stack and the third gate stack; a plurality of channel holes penetrating through the interlayer dielectric layer and reaching at least the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region, respectively; and a plurality of conductive vias formed by filling the plurality of via holes with a conductive material.

Preferably, the portions of the first source region and the first drain region, which are in contact with the conductive channel, serve as a first source ohmic contact region and a first drain ohmic contact region, the portions of the second source region and the second drain region, which are in contact with the conductive channel, serve as a second source ohmic contact region and a second drain ohmic contact region, and the portions of the third source region and the third drain region, which are in contact with the conductive channel, serve as a third source ohmic contact region and a third drain ohmic contact region.

Preferably, the method further comprises the following steps: a fifth well region of the first doping type located in the substrate second region, the fifth well region and the third well region being adjacent to each other; the first channel region of the first doping type is positioned in the fourth well region, the second channel region of the first doping type is positioned in the fifth well region, and the doping amount in the first channel region and the second channel region is the same as that in the second source region and the second drain region.

Preferably, the plurality of via holes include via holes penetrating through the interlayer dielectric layer and reaching the first channel region and the second channel region, respectively, where the first channel region includes a first channel contact region, and the second channel region includes a second channel contact region.

Preferably, the method further comprises the following steps: a sixth well region of the first doping type located in the first region of the substrate, the sixth well region being adjacent to the second well region; a first doped region of a second doping type located in the substrate; and forming a second doping region of the first doping type extending outwards from the sixth well region, wherein the first doping region is in contact with the second doping region to form a PN structure, the second doping type of the first doping region is combined with the first doping type of the second source region and the second drain region, and the doping amount in the second doping region is the same as that in the second source region and the second drain region.

Preferably, the method further comprises the following steps: the plurality of channel holes comprise channel holes penetrating through the interlayer dielectric layer and reaching the first doped region and the fourth doped region respectively, the fourth doped region comprises a fourth doped contact region, the first doped region comprises a first doped contact region, and the doping amount in the fourth doped region is the same as the doping amount in the second source region and the second drain region.

Preferably, the method further comprises the following steps: a seventh well region of the second doping type located in the first region of the substrate, the seventh well region being arranged in parallel with the well region in the first region; and forming a third doped region of the first doping type in the seventh well region to form a body resistor, wherein the doping amount in the third doped region is the same as the doping amount in the second source region and the second drain region.

Preferably, the first gate stack and the second gate stack respectively include a gate conductor and a gate dielectric, the gate dielectric is located between the gate conductor and the substrate, an equivalent dopant of the gate conductor is of a first doping type or a second doping type, and the plurality of via holes include at least one via hole penetrating through the interlayer dielectric layer to reach the gate conductor.

Preferably, the method further comprises the following steps: and the isolation structure is positioned between the adjacent well regions and extends downwards from the surface of the substrate.

Preferably, the method further comprises the following steps: and the compensation region of the first doping type is positioned on part of the surface of the well region of the first doping type.

Preferably, the method further comprises the following steps: the field oxide region is positioned on the middle surface of the third well region and extends downwards; and the fourth gate stack is positioned on the field oxide region and used as a field plate, and the third gate stack comprises a part which is positioned on the field oxide region and used as the field plate.

Preferably, the semiconductor device is a BCD device.

Preferably, the semiconductor device comprises at least a CMOS device and at least one of a diode, a resistor, a capacitor, a low voltage triac, a high voltage semiconductor device.

Preferably, the high voltage semiconductor device includes, but is not limited to: high-voltage JFET device, gate oxide high-voltage MOS device and field oxide high-voltage MOS device.

The invention provides a semiconductor device and a manufacturing method thereof.A first semiconductor device structure and a second semiconductor device structure are formed in a first area of a substrate, and a fifth semiconductor device structure is formed in a second area of the substrate. After forming the first source region and the first drain region in the first semiconductor device structure and the third source region and the third drain region in the fifth semiconductor device structure and removing the photoresist mask, a dopant of the first doping type is implanted on the substrate to form a second source region and a second drain region in the second semiconductor device. And compounding the dopants of the second doping type, which are implanted into the second source region and the second drain region in the second semiconductor device structure in the step, in the first source region and the first drain region and the third source region and the third drain region, and maintaining equivalent dopants of the first source region and the first drain region and the third source region and the third drain region as the second doping type. Therefore, when the second source region and the second drain region in the second semiconductor device structure are formed, an additional mask is not needed to shield the first semiconductor device structure and the fifth semiconductor device structure, compared with the conventional method, the photoetching times are reduced, the manufacturing cost is reduced, and meanwhile, the performance of the semiconductor device manufactured by the method can be guaranteed.

Preferably, when the second source ohmic contact region, the second drain ohmic contact region and the channel contact region are formed, a channel hole penetrating through the interlayer dielectric layer and reaching the first source region, the first drain region, the second source region, the second drain region, the third source region and the third drain region is used as an injection channel to inject a dopant of the first doping type, so as to form the second source ohmic contact region and the second drain ohmic contact region. Further, the dopants of the second doping type implanted into the second source region and the second drain region in the second semiconductor device structure in this step are compounded by the dopants of the second doping type in the first source region and the first drain region and the dopants of the second doping type implanted into the second source region and the second drain region in the third source region and the third drain region, and the equivalent dopants of at least a partial region of the first source region and the first drain region are maintained as the second doping type to serve as the first source ohmic contact region and the first drain ohmic contact region and the equivalent dopants of at least a partial region of the third source region and the third drain region are maintained as the second doping type to serve as the third source ohmic contact region and the third drain ohmic contact region. Therefore, when the second source ohmic contact region and the second drain ohmic contact region in the second semiconductor device structure are formed, an additional mask is not needed to shield the first semiconductor device structure and the fifth semiconductor device structure, and the second source ohmic contact region and the second drain ohmic contact region are formed through a photoetching step.

Preferably, the isolation structure is formed between each adjacent well region, before the field oxide region serving as the isolation structure is formed, an active region is formed before the well region of the first doping type is formed, and then a compensation region of the first doping type is formed on a part of the surface of the well region of the first doping type by using the active region as a hard mask, so as to compensate for the loss of the dopant of the well region of the first doping type due to the formation of the field oxide region. Meanwhile, when the compensation region is formed, an active region is formed before a well region of a first doping type is formed, then a photoresist mask used for shielding a well region of a second doping type is not removed after the well region of the first doping type is formed, the compensation region is continuously formed, the well region of the first doping type is formed by adopting high-energy injection through one-time photoetching, the compensation region is formed on at least part of the surface of the well region of the first doping type by adopting low-energy injection, an additional mask is not needed to shield the well region of the second doping type, and the compensation region is formed through the photoetching step.

Preferably, in the step of forming the second source region and the second drain region, the invention can simultaneously manufacture and form the bulk resistor with high resistivity, thereby realizing larger voltage drop, namely, the resistor with high resistivity can be manufactured and formed without additional mask and photoetching operation during resistor formation, and reducing the manufacturing cost. And simultaneously in the step of forming the second source region and the second drain region, forming the second doping region of the first doping type in contact with the first doping region of the second doping type to form a PN structure of a diode device structure, namely, a diode with equivalent voltage resistance to the existing voltage resistance, such as a diode in a specific region in a voltage stabilizing diode or a triode, can be manufactured under the current simple process of reducing photoetching. Therefore, additional mask and photoetching steps are not needed to form the PN structure, and the manufacturing cost is reduced. Furthermore, when the PN structure is formed, a part of the dopant of the second doping type in the first doping region is compounded with the dopant of the first doping type, and the equivalent dopant of the first doping region is maintained to be the second doping type, so that when the PN structure of the diode is formed, additional masks and photoetching steps are not needed, compared with the conventional method, the photoetching times are reduced, and the manufacturing cost is reduced.

Preferably, when the gate conductor in the semiconductor device of the present invention is a polysilicon layer of the second doping type, the equivalent dopant of the final gate conductor in the semiconductor device is maintained at the second doping type. When the gate conductor in the semiconductor device is formed as a polysilicon layer of the first doping type, the equivalent dopant of the final gate conductor in the semiconductor device is maintained at the first doping type. That is, the polysilicon in the gate conductor is simultaneously implanted with a dopant during the formation of the source and drain regions, the dopant being the same as the dopant during the formation of the source and drain regions, the dopant being recombined with a portion of the initial dopant in the gate conductor to maintain the initial doping type.

Preferably, the semiconductor device in the present invention includes a BCD device, a Bi-CMOS device, a CMOS device.

Drawings

The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of a semiconductor device of an embodiment of the present invention.

Fig. 2 is a schematic flow chart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 3A to 3H are schematic structural diagrams showing each specific step in the semiconductor device manufacturing process.

Fig. 4 is a schematic flow chart illustrating the formation of the first to seventh well regions according to another embodiment of the present invention.

Fig. 5A to 5E are schematic structural diagrams showing each specific step in the process of forming the first to seventh well regions.

Detailed Description

The present application will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.

Numerous specific details of the present application are set forth below in order to provide a more thorough understanding of the present application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.

When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of semiconductor devices, are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

As shown in fig. 1, the semiconductor device includes a substrate 100, a first semiconductor device 101, a second semiconductor device 102, a third semiconductor device 103, a fourth semiconductor device 104, and a fifth semiconductor device 105, which are located in a first region of the substrate and are arranged adjacently in a lateral direction, and an isolation structure extending downward from a surface of the substrate 100 is disposed between the adjacent devices. A first region and a second region in the substrate 100 are adjacent to each other, the first region being a low voltage device region, and the second region being a high voltage device region.

In the present embodiment, in the first region, the first semiconductor device is a low voltage NMOS device 101, the second semiconductor device is a low voltage PMOS device 102, the third semiconductor device is a diode 103, and the fourth semiconductor device is a resistor 104, and adjacent devices are isolated from each other by a field oxide region 200 that is located on the surface of the substrate 100 and extends downward. In other embodiments, other low-voltage devices such as a triode, a capacitor and the like can be integrated into the first region, and diodes, resistors and the like can be removed according to actual needs. Additionally, in other embodiments, the high voltage devices in the second region may be eliminated, and only the low voltage devices in the first region may be made. And the high voltage semiconductor devices of the second region include, but are not limited to: high-voltage JFET device, gate oxide high-voltage MOS device and field oxide high-voltage MOS device. In other embodiments, adjacent devices are isolated from each other by a trench extending downward from the surface of the substrate 100, and the depth of the trench is set based on the depth of the well region of each of the two adjacent devices to achieve the isolation effect.

The low-voltage NMOS device 101 includes a first well region 110 of a P-type low voltage in a first region of a substrate, a first gate stack over the first well region 110, a first source region 711 and a first drain region 712 of an N-type located on two sides of the first gate stack and in the first well region 110, and an interlayer dielectric layer 810 over the first gate stack. The first gate stack includes a gate conductor 320 in the first region, a gate dielectric 310 between the gate conductor 320 and the first well region 110 in the first region, and gate sidewall spacers 330 at sidewalls of both ends of the gate conductor 320 and the gate dielectric 310 in the first region, wherein the gate conductor 320 is polysilicon. The low voltage NMOS device 101 further includes a conductive via 820 penetrating through the interlayer dielectric layer 810 and electrically connected to the gate conductor 320, the first source region 711, and the first drain region 712, respectively, and a passivation layer 900 on the surfaces of the interlayer dielectric layer 810 and the conductive via 820 in the low voltage NMOS device 101. A partial region of the first source region 711 contacting the conductive channel 820 is used as a first source ohmic contact region, a partial region of the first drain region 712 contacting the conductive channel 820 is used as a first drain ohmic contact region, and the first source ohmic contact region and the first drain ohmic contact region are doped N-type. In other embodiments, at least a portion of the surface of the first well region 110 under the field oxide region 200 is used as a P-type compensation region to enhance the isolation effect.

The low-voltage PMOS device 102 includes a second well region 120 of N-type high voltage in the first region of the substrate, a second gate stack over the second well region 120, a second source region 721 and a second drain region 722 of P-type respectively on two sides of the second gate stack and in the second well region 120, and an interlayer dielectric layer 810 over the second gate stack. The second gate stack includes a gate conductor 320 in the first region, a gate dielectric 310 between the gate conductor 320 and the second well region 120 in the first region, and gate sidewall spacers 330 at sidewalls of both ends of the gate conductor 320 and the gate dielectric 310 in the first region, wherein the gate conductor 320 is polysilicon. The low voltage PMOS device 102 further includes a conductive via 820 electrically connected to the gate conductor 320, the second source region 721, and the second drain region 722 through the interlayer dielectric layer 810, and a passivation layer 900 on the surface of the interlayer dielectric layer 810 and the conductive via 820 in the low voltage PMOS device 102. A partial region of the second source region 721 in contact with the conductive via 820 is used as a second source ohmic contact region, a partial region of the second drain region 722 in contact with the conductive via 820 is used as a second drain ohmic contact region, and the second source ohmic contact region and the second drain ohmic contact region are P-type.

The diode 103 includes a sixth well 130 of P-type low voltage in the first region of the substrate, a second doped region 732 of P-type at least partially in the sixth well 130, a first doped region 731 of N-type laterally in contact with the second doped region 732, a fourth doped region 733 of P-type in the sixth well 130 isolated from the second doped region 732, and an interlayer dielectric layer 810 above the substrate. Wherein the P-type second doped region 732 contacts the N-type first doped region 731 to form a PN structure. The diode 103 further includes a conductive channel 820 penetrating the interlayer dielectric layer 810 and electrically connected to the first doped region 731 and the fourth doped region 733, respectively, and a passivation layer 900 on the surface of the interlayer dielectric layer 810 and the conductive channel 820 of the diode 103. A portion of the first doped region 731 contacting the conductive via 820 is used as a first doped contact region, a portion of the fourth doped region 733 contacting the conductive via 820 is used as a fourth doped contact region, the first doped contact region is N-type, and the fourth doped contact region is P-type. In other embodiments, at least a portion of the surface of the sixth well region 130 under the field oxide region 200 is used as a P-type compensation region to enhance the isolation effect.

The resistor 104 includes a seventh well 140 of N-type high voltage in the first region of the substrate, a third doped region 741 of P-type in the seventh well 140, and an interlayer dielectric layer 810 over the substrate. The resistor 104 further includes a passivation layer 900 on the surface of the interlayer dielectric layer 810.

The fifth semiconductor device of the high-voltage device in the second region, which is laterally arranged adjacent to the semiconductor device in the first region, is a high-voltage LDMOS device 105, the high-voltage LDMOS device 105 is adjacent to the resistor 104, and the high-voltage LDMOS device 105 and the resistor 104 are isolated from each other by a field oxide region 200 which is located on the surface of the substrate 100 and extends downward. In other embodiments, for example, a high voltage JFET device, a gate oxide high voltage MOS device, a field oxide high voltage MOS device, or the like may also be integrated in the second region. In other embodiments, adjacent devices are isolated from each other by a trench extending downward from the surface of the substrate 100, and the depth of the trench is set based on the depth of the well region of each of the two adjacent devices to achieve the isolation effect.

The high-voltage LDMOS device 105 includes a third well region 150 of N-type high voltage and a fifth well region 170 of P-type low voltage located adjacent to each other in the second region of the substrate, a fourth well region 160 of P-type low voltage located in the third well region 150, the fourth well region 160 being located at a first boundary of the third well region 150 and being close to the fifth well region 170 located in the second region of the substrate, a field oxide region 200 extending downward along the surface of the substrate 100 between the adjacently disposed third well region 150 and the fifth well region 170, a third drain region 751 of N-type located in the third well region 150 and being close to a second boundary of the third well region 150, a fourth gate stack serving as a field plate and extending to the third well region 150 and the fourth well region 160 along the surface of the field oxide region 200, a third source well region 752 and a first channel region 753 of P-type located in the fourth well region 160, a second channel region 754 of P-type located in the fifth well region 170, a first channel region 753 of P-type located in the fifth well region 170, and a second channel region 754 of N-type, And an interlayer dielectric layer 810 positioned above the substrate 100 in the region where the high-voltage LDMOS device 105 is positioned. The fourth gate stack includes a gate conductor 320 located on the field oxide region 200, a gate dielectric 310 located between the gate conductor 320 and the field oxide region 200, and gate sidewalls 330 located at two end sidewalls of the gate conductor 320 and the gate dielectric 310, wherein the gate conductor 320 is polysilicon. The third gate stack includes a gate conductor 320 over the field oxide region 200 and extending along the field oxide region 200 to the third well region 150 and the fourth well region 160, a gate dielectric 310 over the third well region 150, the fourth well region 160, and the field oxide region 200, wherein the gate dielectric 310 is under the gate conductor 320, and gate sidewalls 330 at sidewalls of both ends of the gate conductor 320 and the gate dielectric 310, and the gate conductor 320 is polysilicon. The fourth gate stack and a part of the third gate stack located on the field oxide region 200 are used as field plates to facilitate optimizing the electric field on the surface of the device, and the part of the third gate stack located in the well region forms a channel of the device. The high-voltage LDMOS device 105 further includes a conductive channel 820 penetrating through the interlayer dielectric layer 810 and electrically connected to the third drain region 751, the third source region 752, the first channel region 753, the second channel region 754, and the fourth gate stack, respectively, and a conductive channel (not shown) electrically connected to the third gate stack, and a passivation layer 900 on the surface of the interlayer dielectric layer 810 and the conductive channel 820 in the high-voltage LDMOS device 105. A partial region of the third source region 752, which is in contact with the conductive channel 820, serves as a third source ohmic contact region, a partial region of the third drain region 751, which is in contact with the conductive channel 820, serves as a third drain ohmic contact region, and the third source ohmic contact region and the third drain ohmic contact region are N-type. A portion of the first channel region 753 in contact with the conductive via 820 serves as a first channel contact region, which is P-type. A portion of the second channel region 754 in contact with the conductive via 820 serves as a second channel contact region, which is P-type.

The doping type of the gate conductor 320 in this embodiment may be P-type or N-type.

Fig. 2 is a schematic flow chart showing a method for manufacturing a semiconductor structure according to an embodiment of the present invention, and fig. 3A to 3H are schematic structural diagrams showing each specific step in a semiconductor device manufacturing process.

In this embodiment, a manufacturing step of the semiconductor device provided in fig. 1 is explained as an example.

As shown in fig. 2, the method for manufacturing the semiconductor device provided in fig. 1 includes the steps of:

in step S10, at least one well region of a second doping type is formed in the first and second regions of the substrate, respectively. As shown in fig. 3A, two second well regions 120 and a seventh well region 140 of N-type high voltage are formed in parallel in a first region 111 of a substrate 100, and a third well region 150 of N-type high voltage is formed in a second region 112 adjacent to the first region 111. The first region 111 is a low-voltage device region, the second region 112 is a high-voltage device region, and a plurality of N-type well regions are formed and distributed in parallel.

In step S20, at least one well region of a first doping type is formed in the first and second regions of the substrate, respectively. As shown in fig. 3B, in the structure shown in fig. 3A, the first well region 110 and the sixth well region 130 of P-type low voltage are formed in the first region 111 of the substrate 100 and arranged in parallel, and the fifth well region 170 of P-type low voltage and the fourth well region 160 of P-type low voltage are formed in the second region 112 of the substrate and arranged in parallel with the third well region 150 and located near the first boundary in the third well region 150.

In step S30, isolation structures extending downward from the substrate surface are formed between and in adjacent well regions. As shown in fig. 3C, a field oxide region 200 extending downward from the upper surface of the substrate 100 is formed between adjacent well regions by local Oxidation of Silicon (LOCOS) or Chemical Vapor Deposition (CVD) to achieve isolation between the adjacent well regions. Further, an oxide layer is grown with the active region as a hard mask to form the field oxide region 200. In other embodiments, a trench is formed between adjacent well regions to serve as an isolation structure to achieve isolation, wherein the depth of the trench is related to the depth of the adjacent well regions or doped regions, for example. The active region is then removed.

In step S40, a gate stack and a field plate are formed on the corresponding well regions, respectively. As shown in fig. 3D, a first gate stack and a second gate stack are formed over the first well region 110 and the second well region 120, respectively, a fourth gate stack serving as a field plate is formed over the field oxide region 200 on the third well region 150, and a third gate stack is formed over the field oxide region 200 on the third well region 150 and extending to the third well region 150 and a portion of the fourth well region 160, wherein a portion of the third gate stack over the field oxide region 200 serves as a field plate, and a portion of the third gate stack over the third well region and the fourth well region is used for forming a device channel. Further, impurities and formed oxide layers of the substrate 100 exposed to the air are cleaned, and the substrate enters an oxidation furnace to grow into a silicon dioxide layer. The substrate 100 is then placed in a low pressure CVD apparatus with silane introduced, which decomposes to deposit a layer of polysilicon on the surface of the gate dielectric 310. And (4) etching the polysilicon in the photoetching area by utilizing a deep ultraviolet photoetching technology. Then, a silicon dioxide layer is deposited, and the deposited silicon dioxide is etched by using an anisotropic plasma etcher to obtain a first gate stack including the gate dielectric 310 and the gate conductor 320 above the first well region 110, a second gate stack including the gate dielectric 310 and the gate conductor 320 above the second well region 120, a fourth gate stack including the gate dielectric 310 and the gate conductor 320 above the field oxide region above the third well region 150, and a third gate stack including the gate dielectric 310 and the gate conductor 320 above the fourth well region 160, the third well region 150, and a portion of the surface of the field oxide region, in a vertical cross section. And then, gate spacers 330 are formed on the sidewalls of the two ends of the first to fourth gate stacks, respectively. The polysilicon of the gate conductor 320 may be doped P-type or N-type. In other embodiments, the polysilicon of the gate conductor is doped with the second doping type during the formation of the first source and first drain regions and the third source and third drain regions, and in this embodiment, the equivalent doping type of the gate conductor in the semiconductor device is the same as the initial doping type of the gate conductor. In other embodiments, the polysilicon of the gate conductor may be doped with the first doping type during the formation of the second source region and the second drain region such that the equivalent doping type of the gate conductor in the semiconductor device is consistent with the initial doping type of the gate conductor.

In step S50, a first source region and a first drain region of the second doping type, a first doped region, a third source region and a third drain region are formed in the first well region, the substrate and the third well region. As shown in fig. 3E, the second well region 120, the sixth well region 130, the seventh well region 140, the fifth well region 170, and a portion of the fourth well region 160 in the substrate 100 are masked by a photoresist mask, and dopants of the second doping type are implanted using the first gate stack, the third gate stack, the fourth gate stack, and the field oxide region 200 as hard masks to form a first source region 711 and a first drain region 712 of the second doping type in the first well region 110, a third source region 752 and a third drain region 751 of the second doping type in the third well region 150 and the fourth well region 160, respectively, and a first doping region 731 of the second doping type in a region of the substrate 100 near the sixth well region 130. The implantation energy, the dopant amount, and the implantation angle of the dopant for forming the second doping type doped region may be further selected according to the requirements of the semiconductor device on voltage resistance, size, current, and the like. The photoresist mask is then removed.

In step S60, a second source region and a second drain region of the first doping type, a second to fourth doping regions, a second channel region, and a first channel region are formed in the second well region and the fourth to seventh well regions, respectively. As shown in fig. 3F, a field oxide region 200 is used as a hard mask to implant dopants of the first doping type in a blanket implantation manner to form a second source region 721 and a second drain region 722 of the first doping type in the second well 120, respectively, a first channel region 753 and a second channel region 754 of the first doping type in the fourth well 160 and the fifth well 170, respectively, a second doping region 732 of the first doping type extending outward to contact the first doping region 731 to form a PN structure in the diode 103, a fourth doping region 733 of the first doping type in the sixth well 130, and a third doping region 741 of the first doping type in the seventh well 140 to form a bulk resistance structure in the resistor 104, wherein the resistor 104 has a resistance range of 300-2000 Ω. Wherein the dopant amount of the N-type dopant implanted in step S50 is higher than the dopant amount of the first doping type dopant so that the first source and drain regions and the third source and drain regions form ohmic contacts. Further, in step S60, the dopants of the first doping type implanted into the first source region 711 and the first drain region 712 in the first well region 110 are combined (combine) by the dopants of the second doping type in the first source region 711 and the first drain region 712, and the equivalent dopants of the first source region 711 and the first drain region 712 obtained in this step are maintained as the second doping type, that is, the dopants of the second doping type in the first source region 711 and the first drain region 712 include the dopants of the first doping type. In step S60, the dopants of the first doping type implanted into the third drain region 751 in the third well region 150 and the third source region 752 in the fourth well region 160 are recombined by the dopants of the second doping type in the third source region 752 and the third drain region 751, and the equivalent dopants of the third source region 752 and the third drain region 751 obtained in this step are maintained as the second doping type, that is, the dopants of the second doping type in the third source region 752 and the third drain region 751 comprise the dopants of the first doping type. In step S60, the dopants of the first doping type implanted into the first doping region 731 in the substrate 100 are recombined by the portion of the dopants of the second doping type in the first doping region 731, and the equivalent dopants of the first doping region 731 obtained in this step are maintained as the second doping type. The manufacturing method does not affect the performance of the semiconductor device, and therefore, a photoresist mask is not required to be used for shielding in the step to form the doped region of the first doping type.

In step S70, a plurality of via holes are formed through the interlayer dielectric layer over the gate stack and the field plate region. As shown in fig. 3G, an interlayer dielectric layer 810 is deposited and formed over the structure shown in fig. 3F, and a via hole 811 reaching the first source region 711, the first drain region 712, the gate conductor 320 of the first gate stack, the second source region 721, the second drain region 722, the gate conductor 320 of the second gate stack, the first doped region 731, the fourth doped region 733, the third drain region 751, the third source region 752, the first channel region 753, the second channel region 754, and the gate conductor 320 of the fourth gate stack is formed through the interlayer dielectric layer 810. In other embodiments, the resistor 104 connects the third doped region 741 with an external via hole and the gate conductor 320 in the third gate stack with an external via hole, which are not shown in the figure, in this step only the via hole 811 reaching the first source region 711, the first drain region 712, the second source region 721, the second drain region 722, the first doped region 731, the fourth doped region 733, the third drain region 751, the third source region 752, the first channel region 753, and the second channel region 754 is formed through the interlayer dielectric layer 810, and after the ohmic contact of the first doping type is formed in the doped regions, the via hole 811 further penetrating the interlayer dielectric layer 810 and reaching the gate conductor 320 of the first gate stack, the gate conductor 320 of the second gate stack, and the gate conductor 320 in the fourth gate stack is formed.

In step S80, a conductive via is formed by forming a second source ohmic contact region, a second drain ohmic contact region, a fourth doped contact region, a first channel contact region, a second channel contact region and filling the via hole with the via hole as an implantation via. As shown in fig. 3H, the interlayer dielectric layer 810 is used as a hard mask, and the channel hole 811 is used as an injection channel to inject the first doping type dopant, so as to form a second source ohmic contact region, a second drain ohmic contact region, a fourth doping contact region, a first channel contact region, and a second channel contact region of the first doping type in the second source region 721, the second drain region 722, the fourth doping region 733, the first channel region 753, and the second channel region 754, respectively. Further, in the step of forming the ohmic contact of the first doping type, the first doping type dopant injected into the first source region 711 and the first drain region 712 is combined with a portion of the equivalent dopant of the second doping type in the first source region 711 and the first drain region 712, so as to serve as a first source ohmic contact region and a first drain ohmic contact region in a portion of the first source region and a portion of the first drain region in contact with the channel hole 811, respectively, and the equivalent dopant of the first source ohmic contact region and the first drain ohmic contact region is maintained as the second doping type. In the step of forming the ohmic contact of the first doping type, the first doping type dopant implanted into the third source region 752 and the third drain region 751 is combined with a part of the equivalent dopant of the second doping type in the third source region 752 and the third drain region 751, so that the part of the regions of the third source region and the third drain region respectively contacting with the channel hole 811 serve as a third source ohmic contact region and a third drain ohmic contact region, and the equivalent dopant of the third source ohmic contact region and the third drain ohmic contact region is maintained at the second doping type. In the step of forming the ohmic contact region of the first doping type, the equivalent dopant of the second doping type in the first doping region 731 is compositely implanted into the dopant of the first doping type in the first doping region 731, so that a portion of the first doping region 731 contacting the via hole 811 serves as the first doping ohmic contact region, and the equivalent dopant of the first doping ohmic contact region is maintained as the second doping type. The doping dose of the ions implanted this time is lower than that of the second doping type dopant implanted when the N-type doping region is formed. When the gate conductor 320 in the semiconductor device is formed as a polysilicon layer of the second doping type during the formation of the gate stack, the equivalent dopant of the final gate conductor in the semiconductor device is maintained as the second doping type. In other embodiments, when the gate conductor 320 in the semiconductor device is formed as a polysilicon layer of the first doping type during the formation of the gate stack, the equivalent dopant of the final gate conductor in the semiconductor device remains at the first doping type. The polysilicon in the gate conductor is simultaneously implanted with a dopant during the process of forming the source and drain regions, the dopant is the same as the dopant during the process of forming the source and drain regions, and the dopant is compounded by the initial dopant in the gate conductor 320 to maintain the initial doping type. Then, the via hole is filled to form a conductive via. A conductive channel 820 is formed in the channel hole 811 using a conductive material such that the first source region 711, the first drain region 712, the gate conductor 320 of the first gate stack, the second source region 721, the second drain region 722, the gate conductor 320 of the second gate stack, the first doped region 731, the fourth doped region 733, the third drain region 751, the third source region 752, the first channel region 753, and the second channel region 754 are connected to the outside through the conductive channel 820. Further, a low voltage NMOS device 101, a low voltage PMOS device 102, a diode 103, and a resistor 104 are formed adjacent to each other in a first region 111 of the substrate 100, and a high voltage LDMOS device 105 is formed in a second region 112 of the substrate 100, the first region 111 being adjacent to the second region 112.

In step S90, a passivation layer is formed. As shown in fig. 2, photolithography is deposited over the structure shown in fig. 3H to form a passivation layer 900, the passivation layer 900 being, for example, at least one of silicon nitride or silicon dioxide.

Fig. 4 is a schematic flow chart illustrating formation of the first to seventh well regions according to another embodiment of the present invention, and fig. 5A to 5E are schematic structural diagrams illustrating each specific step in the process of forming the first to seventh well regions.

This embodiment is based on the above embodiment, wherein the compensation region of the first doping type is formed on at least a portion of the surface of the well region of the first doping type, so that the isolation structure formed on the surface of the well region of the first doping type and extending downward contacts the compensation region, so that the doping of the well region of the first doping type is compensated when the isolation structure is formed. In the embodiments described below, the compensation region is formed on at least a portion of the surface of the well region of the first doping type without additional mask and photolithography steps on the basis of not affecting the performance of the semiconductor device, thereby enhancing the isolation effect of the isolation structure.

As shown in fig. 4 and fig. 5A to 5E, the process of forming the first to seventh well regions in this embodiment includes the following steps:

step S121: and forming a second well region and a seventh well region of the second doping type in the first region of the substrate, and forming a third well region of the second doping type in the second region. Further, as shown in fig. 5A, a first oxide layer is formed on the P-type substrate 100, for example, a silicon dioxide layer is formed by a thermal oxidation method; and etching the first oxide layer by using a third photoresist mask 330, positioning the position of the well region of the second doping type in the substrate 100, removing the photoresist, then performing high-energy N-type ion implantation, annealing, and removing the first oxide layer, thereby forming an N-type high-voltage second well region 120 and a seventh well region 140 in the first region 111 of the substrate 100, and an N-type high-voltage third well region 150 in the second region 112 of the substrate 100, wherein a step difference is formed at the removed part of the first oxide layer, so that the method can be used for subsequent photoetching alignment, and the conventional alignment photoetching step is omitted. The third photoresist mask 330 is then removed.

Step S122: an oxide layer is formed on the substrate and a nitride layer is formed on the oxide layer. Next, as shown in fig. 5B, an oxide layer 201 and a nitride layer 202 are sequentially deposited on the surface of the substrate 100, wherein the oxide layer 201 is, for example, a silicon dioxide layer, and the nitride layer 202 is, for example, a silicon nitride layer.

Step S123: active regions are formed in the first and second regions of the substrate. Next, as shown in fig. 5C, the oxide layer 201 and the nitride layer 202 are etched using the first photoresist mask 310 to form active regions in the first region 111 and the second region 113 of the substrate 100, respectively. The active region after the photoetching is used as a hard mask for forming a compensation region and an isolation structure. The first photoresist mask is then removed.

Step S124: and a photoresist mask is adopted to at least shield the well region of the second doping type on the substrate so as to form a first well region and a sixth well region of the first doping type in the first region and form a fourth well region and a fifth well region of the first doping type in the second region. Further, as shown in fig. 5D, a second photoresist mask 320 is used to mask at least the second well region 120 and the seventh well region 140 of the second doping type in the first region 111 and the third well region 150 of the second doping type in the second region 112 in the substrate 100, and a high energy implantation is performed to form the first well region 110 and the sixth well region 130 of the first doping type in the first region 111 of the substrate 100 and to form the fourth well region 160 and the fifth well region 170 of the first doping type in the second region 112 of the substrate 100, wherein the implantation energy of the dopant of the first doping type which is performed with the high energy implantation enables the dopant to penetrate the active region.

Step S125: and forming a compensation region of the first doping type on at least part of the surface of the well region of the first doping type by adopting a photoresist mask and adopting the active region as a hard mask. As shown in fig. 5E, further, on the basis of not removing the second photoresist mask 320, the active region is simultaneously used as a hard mask to form a compensation region of the first doping type in the well region of the first doping type at least in a region below the field oxide region, and the implantation energy of the dopant of the first doping type forming the compensation region is such that the dopant cannot penetrate the active region. The second photoresist mask is then removed. Then, when forming the isolation structure, the active region as shown in the structure of fig. 5E is used as a hard mask to form the isolation structure 200, and then the active region is removed, and the subsequent steps are completed according to the above-mentioned manufacturing method of the semiconductor device to form the semiconductor device.

In other embodiments, in the process of forming the first to seventh well regions, an active region may be formed on the substrate by using a first photoresist mask, then the active region is blocked by using a third photoresist mask and high-energy implantation is performed to form a second doping type well region, then the high-energy implantation is performed by using a second photoresist mask to form a first doping type well region, then the second photoresist mask is continued to be blocked and the active region is used as a hard mask, and a first doping type compensation region is formed on at least a part of the surface of the first doping type well region. The single photolithography step is the same as the single step process for forming the first to seventh well regions provided above. Preferably, in the high-energy implantation process, the high-energy implantation may be performed in multiple times to form the first doping type well region and the second doping type well region.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In accordance with the embodiments of the present application, as set forth above, these embodiments are not intended to be exhaustive or to limit the disclosure to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated.

Claims

1. A semiconductor device manufacturing method, comprising:

forming a first gate stack on a first well region of a first region of a substrate, the first well region being of a first doping type;

forming a second gate stack over a second well region of a first region of a substrate, the second well region being of a second doping type, the first doping type being opposite to the second doping type, the first well region and the second well region being adjacent to each other;

forming a third gate stack on a third well region and a fourth well region of a second region of the substrate, the third well region being of a second doping type, the fourth well region being of a first doping type, the fourth well region being located in the third well region, the first region and the second region being adjacent to each other;

respectively forming a first source region and a first drain region of a second doping type in the first well region by using a photoresist mask and the first gate stack and the third gate stack as hard masks, forming a third drain region of the second doping type in the third well region, and forming a third source region of the second doping type in the fourth well region; and

removing the photoresist mask, performing normal injection to form a second source region and a second drain region of the first doping type in the second well region,

in the step of forming the second source region and the second drain region, the second doping type dopant in the first source region and the first drain region and the third source region and the third drain region is combined with the first doping type dopant, and the equivalent dopants of the first source region and the first drain region and the third source region and the third drain region are maintained as the second doping type.

2. The manufacturing method of claim 1, wherein a dopant dose of the second doping type dopant forming the first source and drain regions and the third source and drain regions is higher than a dopant dose of the first doping type dopant forming the second source and drain regions such that the first source and drain regions and the third source and drain regions form ohmic contacts.

3. The manufacturing method according to claim 1, further comprising, after the step of forming the second source region and the second drain region:

forming an interlayer dielectric layer on the first gate stack, the second gate stack and the third gate stack;

forming a plurality of channel holes which penetrate through the interlayer dielectric layer and at least respectively reach the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region; and

filling the plurality of via holes with a conductive material to form a plurality of conductive vias.

4. A manufacturing method according to claim 3, wherein, after forming a conductive channel, portions of the first source and drain regions exposed by the channel hole and in contact with the conductive channel serve as first source and drain ohmic contact regions, and portions of the third source and drain regions exposed by the channel hole and in contact with the conductive channel serve as third source and drain ohmic contact regions.

5. The manufacturing method according to claim 4, further comprising, between the step of forming the passage hole and the conductive passage:

implanting a dopant of a first doping type using the plurality of channel holes as an implantation channel to form a second source ohmic contact region and a second drain ohmic contact region in the second well region,

the first source region and the first drain region and the third source region and the third drain region are compounded with the first doping type dopant, equivalent dopants of the first source region and the first drain region, which are exposed through the channel hole and are used as a partial region of the first source ohmic contact region and the first drain ohmic contact region, are maintained as a second doping type, and equivalent dopants of the third source region and the third drain region, which are exposed through the channel hole and are used as a partial region of the third source ohmic contact region and the third drain ohmic contact region, are maintained as a second doping type.

6. The manufacturing method according to claim 5, further comprising:

in the step of forming the second source region and the second drain region, a first channel region of the first doping type is formed in the fourth well region, and a second channel region of the first doping type is formed in a fifth well region of the first doping type in the second region of the substrate, the fifth well region and the third well region being adjacent to each other.

7. The manufacturing method according to claim 6,

the plurality of channel holes comprise channel holes penetrating through the interlayer dielectric layer and reaching the first channel region and the second channel region respectively,

in the step of forming the second source ohmic contact region and the second drain ohmic contact region, a first channel contact region of the first doping type is formed in the first channel region, and a second channel contact region of the first doping type is formed in the second channel region.

8. The manufacturing method according to claim 5, further comprising:

forming a first doped region of a second doping type in the substrate in the step of forming the first source region and the first drain region and the third source region and the third drain region;

in the step of forming the second source region and the second drain region, a second doping region of the first doping type extending to the outside is formed in a sixth well region of the first region of the substrate, and a fourth doping region of the first doping type is formed in the sixth well region, the second doping region being in contact with the first doping region to form a PN structure, the sixth well region being adjacent to the second well region, the sixth well region being of the first doping type,

the second doping type dopant of the first doping region is combined with the first doping type dopant, and the equivalent dopant of the first doping region is maintained as the second doping type.

9. The manufacturing method according to claim 8, wherein the plurality of via holes include via holes penetrating the interlayer dielectric layer to reach the first doped region and the fourth doped region, respectively,

after forming the conductive via, a portion of the first doped region exposed by the via hole and in contact with the conductive via serves as a first doped contact region,

forming a fourth doped contact region in the fourth doped region in the step of forming the second source ohmic contact region and the second drain ohmic contact region,

a portion of the dopants of the second doping type in the first doped region recombine with the dopants of the first doping type and an equivalent dopant of the first doped contact region in the first doped region remains at the second doping type.

10. The manufacturing method according to claim 5, further comprising:

in the step of forming the second source region and the second drain region, a third doped region of the first doping type is formed in a seventh well region of the second doping type of the first region of the substrate to form a body resistor, the seventh well region and a sixth well region in the first region being adjacent to each other.

11. The manufacturing method of claim 5, wherein the first, second and third gate stacks comprise a gate conductor and a gate dielectric, respectively, the gate dielectric being between the gate conductor and the substrate, the gate conductor being a polysilicon layer, and an equivalent dopant of the gate conductor in the semiconductor device being of the first doping type or the second doping type.

12. The manufacturing method according to claim 11,

in the process of forming the first gate stack, the second gate stack and the third gate stack, the gate conductor is polysilicon of a second doping type;

in the process of forming the second source region and the second drain region, the second doping type dopant in the gate conductor is combined with the first doping type dopant;

the plurality of via holes includes at least one via hole extending through the interlevel dielectric layer to the gate conductor,

in the step of forming the second source ohmic contact region and the second drain ohmic contact region, the dopant of the second doping type of the gate conductor is combined with the dopant of the first doping type, and an equivalent dopant of the gate conductor is maintained as the second doping type.

13. The manufacturing method according to claim 11,

in the process of forming the first gate stack, the second gate stack and the third gate stack, the gate conductor is polysilicon of a first doping type,

in the process of forming the first source region, the first drain region, the third source region and the third drain region, at least the first doping type dopant in the gate conductor in the first gate stack is combined with the second doping type dopant;

in the process of forming the second source region and the second drain region, the dopant of the first doping type is injected into the gate conductor;

in the step of forming the second source ohmic contact region and the second drain ohmic contact region, the dopant of the first doping type is implanted into the gate conductor,

the equivalent dopant of the gate conductor is maintained at the first doping type.

14. The method of manufacturing of claim 1, wherein prior to the step of forming the first, second, and third gate stacks, further comprising:

forming the second well region and a seventh well region of a second doping type in a first region of the substrate, and forming the third well region of the second doping type in a second region of the substrate;

forming a first well region and a sixth well region of a first doping type in a first region of the substrate, and forming a fourth well region and a fifth well region of the first doping type in a second region of the substrate, wherein the well regions in the first region are arranged in parallel, the third well region and the fifth well region in the second region are adjacent to each other, and the fourth well region is located in the third well region;

isolation structures extending downward from the substrate surface are formed between adjacent well regions,

the isolation structure is used as a part of the hard mask in the step of forming the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region.

15. The method of manufacturing of claim 14, wherein in forming the well region of the first doping type comprises:

forming an active region in a first region and a second region on the substrate using a first photoresist mask;

removing the first photoresist mask, shielding at least a part of the substrate, which forms the well region of the second doping type, by using a second photoresist mask, forming a first well region and a sixth well region of the first doping type in the first region of the substrate, and forming a fourth well region and a fifth well region of the first doping type in the second region of the substrate;

forming a compensation region of the first doping type on part of the surface of the well region of the first doping type by using the second photoresist mask for shielding and the active region as a hard mask, and then removing the second photoresist mask,

and in the process of forming the isolation structure, the active region is used as a part of a hard mask, and then the active region is removed.

16. The method of manufacturing of claim 14, wherein forming the well region of the second doping type and the well region of the first doping type comprises:

removing the first photoresist mask, adopting a third photoresist mask for shielding so as to form the second well region and a seventh well region of a second doping type in the first region of the substrate, and form the third well region of the second doping type in the second region of the substrate, and then removing the third photoresist mask;

shielding at least a part of the substrate where the well region of the second doping type is formed by using a second photoresist mask, forming a first well region and a sixth well region of the first doping type in the first region of the substrate, and forming a fourth well region and a fifth well region of the first doping type in the second region of the substrate;

17. The manufacturing method according to claim 15 or 16, wherein the implantation energy of the dopant of the first doping type forming the well region of the first doping type enables the dopant to penetrate the active region.

18. The manufacturing method according to claim 15 or 16, wherein the implantation energy of the dopant of the first doping type implanted when forming the compensation region is such that the dopant is not able to penetrate the active region.

19. The manufacturing method according to claim 14, further comprising:

in the step of forming the isolation structure, a field oxide region extending downward is formed on a surface in the third well region, a surface of the fourth well region, and a surface of the sixth well region.

20. The manufacturing method according to claim 19, further comprising:

in the step of forming the first gate stack, the second gate stack, and the third gate stack, a fourth gate stack is formed on the field oxide region to serve as a field plate, and the third gate stack includes a portion that is at least on the field oxide region to serve as a field plate.

21. The method of manufacturing of claim 14, wherein the isolation structure comprises at least one of a field oxide region and a trench isolation.

22. The method of manufacturing of claim 1, wherein the first doping type is P-type and the second doping type is N-type.

23. A semiconductor device, comprising:

a substrate;

the semiconductor device comprises a first well region and a fourth well region, wherein the first well region and the second well region are located in a first region of a substrate and are of a first doping type, the third well region and the fourth well region are located in a second region of the substrate and are of a second doping type and a first doping type, the first doping type is opposite to the second doping type, the first region and the second region are adjacent to each other, the first well region and the second well region are adjacent to each other, and the fourth well region is located in the third well region;

a first gate stack over the first well region, a second gate stack over the second well region, and a third gate stack over the third well region and the fourth well region;

a first source region and a first drain region of a second doping type located in the first well region, a second source region and a second drain region of the first doping type located in the second well region, and a third source region and a third drain region of the second doping type located in the third well region and the fourth well region,

and the second doping type dopants of the third source region and the third drain region are compounded with the first doping type dopants of the second source region and the second drain region.

24. The semiconductor device of claim 23, wherein the second drain region and the second source region have the same dopant dose.

25. The semiconductor device of claim 23, further comprising:

the interlayer dielectric layer is positioned above the first gate stack, the second gate stack and the third gate stack;

a plurality of channel holes penetrating through the interlayer dielectric layer and reaching at least the first source region and the first drain region, the second source region and the second drain region, and the third source region and the third drain region, respectively; and

a plurality of conductive vias formed by filling the plurality of via holes with a conductive material.

26. The semiconductor device of claim 25, wherein portions of the first source and drain regions in contact with the conductive channel serve as first source and drain ohmic contact regions, portions of the second source and drain regions in contact with the conductive channel serve as second source and drain ohmic contact regions, and portions of the third source and drain regions in contact with the conductive channel serve as third source and drain ohmic contact regions.

27. The semiconductor device of claim 25, further comprising:

a fifth well region of the first doping type located in the substrate second region, the fifth well region and the third well region being adjacent to each other;

the first channel region of the first doping type is positioned in the fourth well region, the second channel region of the first doping type is positioned in the fifth well region, and the doping amount in the first channel region and the second channel region is the same as that in the second source region and the second drain region.

28. The semiconductor device of claim 27, wherein the plurality of via holes comprises via holes through the interlevel dielectric layer to the first channel region comprising a first channel contact region and the second channel region comprising a second channel contact region, respectively.

29. The semiconductor device of claim 25, further comprising:

a sixth well region of the first doping type located in the first region of the substrate, the sixth well region being adjacent to the second well region;

a first doped region of a second doping type located in the substrate; and

forming a second doped region of the first doping type extending to the outside from the sixth well region, the first doped region being in contact with the second doped region to form a PN structure,

and the second doping type dopant of the first doping region is compounded with the first doping type dopant in the second source region and the second drain region, and the doping amount in the second doping region is the same as that in the second source region and the second drain region.

30. The semiconductor device of claim 29, further comprising:

the plurality of channel holes comprise channel holes penetrating through the interlayer dielectric layer and reaching the first doped region and the fourth doped region respectively, the fourth doped region comprises a fourth doped contact region, the first doped region comprises a first doped contact region, and the doping amount in the fourth doped region is the same as the doping amount in the second source region and the second drain region.

31. The semiconductor device of claim 25, further comprising:

a seventh well region of the second doping type located in the first region of the substrate, the seventh well region being arranged in parallel with the well region in the first region; and

and forming a third doped region of the first doping type in the seventh well region to form a body resistor, wherein the doping amount in the third doped region is the same as the doping amount in the second source region and the second drain region.

32. The semiconductor device of claim 26, wherein the first and second gate stacks comprise a gate conductor and a gate dielectric, respectively, the gate dielectric being between the gate conductor and the substrate, an equivalent dopant of the gate conductor being of a first doping type or a second doping type, the plurality of via holes comprising at least one via hole through the interlevel dielectric layer to the gate conductor.

33. The semiconductor device of claim 23, further comprising:

and the isolation structure is positioned between the adjacent well regions and extends downwards from the surface of the substrate.

34. The semiconductor device of claim 23, further comprising:

and the compensation region of the first doping type is positioned on part of the surface of the well region of the first doping type.

35. The semiconductor device of claim 33, wherein the isolation structure comprises at least one of a field oxide region and a trench isolation.

36. The semiconductor device of claim 23, further comprising:

the field oxide region is positioned on the middle surface of the third well region and extends downwards;

and the fourth gate stack is positioned on the field oxide region and used as a field plate, and the third gate stack comprises a part which is positioned on the field oxide region and used as the field plate.

37. The semiconductor device of claim 23, wherein the first doping type is P-type and the second doping type is N-type.

38. The semiconductor device of claim 23, wherein the semiconductor device is a BCD device.

39. The semiconductor device of claim 23, wherein the semiconductor device comprises at least a CMOS device and at least one of a diode, a resistor, a capacitor, a low voltage triac, a high voltage semiconductor device.

40. The semiconductor device of claim 39 wherein the high voltage semiconductor device includes but is not limited to: high-voltage JFET device, gate oxide high-voltage MOS device and field oxide high-voltage MOS device.