CN112509983B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112509983B CN112509983B CN201910867631.6A CN201910867631A CN112509983B CN 112509983 B CN112509983 B CN 112509983B CN 201910867631 A CN201910867631 A CN 201910867631A CN 112509983 B CN112509983 B CN 112509983B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Abstract
The application discloses a semiconductor device and a method of manufacturing the same. Forming a first gate stack on the first well region of the substrate; shielding at least part of the second region of the substrate by adopting a photoresist mask, and respectively forming a first source region, a drain region and a first doped region of a second doping type in the first well region and the second region of the substrate by adopting the first gate stack layer as a hard mask; and removing the photoresist mask, forming a second doping region of the first doping type in a second well region of the second region by using the first gate stack as a hard mask, wherein the second doping region is in contact with the first doping region to form a PN structure, and in the step of forming the second doping region, the second doping type dopants of the first source, drain and first doping regions are compounded with the first doping type dopant, and the equivalent dopants of the first source, drain and first doping regions are maintained as the second doping type. The manufacturing method can save additional mask and photoetching steps when forming the PN structure, thereby reducing the manufacturing cost.
Description
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
The diode mainly comprises a PN structure, and the reverse breakdown voltage of the diode is generally equal to that of the PN structure. At present, a heavily doped N region (or P region) and a lightly doped P region (or N region) are provided to adjust the doping concentration of the lightly doped region to achieve the required reverse breakdown voltage.
The stable voltage of the diode mainly depends on the doping concentration of the lightly doped P region (or N region), and in the practical process, it is found that the ion implantation dosage of the lightly doped P region (or N region) is low, and the ion implantation process of this order of magnitude requires a special photolithography and doping (ion implantation) process step, resulting in a relatively high manufacturing cost of the semiconductor device.
Disclosure of Invention
In view of the above, the present application provides a semiconductor device and a method for manufacturing the same.
According to an aspect of the present invention, there is provided a semiconductor device manufacturing method including: forming a first gate stack on a first well region of a first region of a substrate, wherein the first well region is of a first doping type; shielding at least part of a second region of the substrate by adopting a photoresist mask, forming a first source region and a first drain region of a second doping type in the first well region by adopting the first gate stack as a hard mask, and forming a first doping region of the second doping type in the second region of the substrate; and removing the photoresist mask, and performing normal injection to form a second doped region of the first doping type in a second well region of the second region, wherein the second doped region extends outwards along the second well region and contacts with the first doped region to form a PN structure, and the second well region is of the first doping type, in the step of forming the second doped region, the dopants of the second doping type in the first source region, the first drain region and the first doped region are combined with the dopants of the first doping type, and the equivalent dopants of the first source region, the first drain region and the first doped region are maintained as the second doping type.
Preferably, the dopant amount of the dopant of the second doping type forming the first source and drain regions and the first doping region is higher than the dopant amount of the dopant of the first doping type forming the second doping region, so that the first source and drain regions form an ohmic contact.
Preferably, in the process of forming the first gate stack, a second gate stack is formed on a third well region of a third region of the substrate, where the third well region is of a second doping type, the first region, the second region, and the third region are distributed in parallel with each other, and the third well region is adjacent to the first well region and the second well region, respectively; in the process of forming the second doped region, a second source region and a second drain region of the first doping type are formed in the third well region, and a channel region of the first doping type is formed in the second well region.
Preferably, after the first source region and the first drain region, the second source region and the second drain region, and the PN structure are formed, the method further includes: forming an interlayer dielectric layer on the first gate stack and the second gate stack; forming a plurality of channel holes which penetrate through the interlayer dielectric layer and at least respectively reach the first source region and the first drain region, the second source region and the second drain region, the first doped region and the channel region; and filling the plurality of via holes with a conductive material to form a plurality of conductive vias.
Preferably, after the conductive channel is formed, portions of the first source and drain regions exposed by the channel hole and in contact with the conductive channel serve as first source and drain ohmic contact regions, and portions of the first doped region exposed by the channel hole and in contact with the conductive channel serve as first doped contact regions.
Preferably, between the steps of forming the channel hole and the conductive channel, further comprising: and injecting a first doping type dopant by using the plurality of channel holes as injection channels, forming a second source ohmic contact region and a second drain ohmic contact region in the third well region and forming a channel contact region in the second well region of the substrate, wherein the first doping type dopant of the first source region, the first drain region and the first doping region is compounded with the first doping type dopant, and equivalent dopants of the first source region, the first drain region and the first doping region, which are exposed through the channel holes and are used as a part of the first source ohmic contact region, the first drain ohmic contact region and the first doping contact region, are maintained as the second doping type.
Preferably, the first gate stack and the second gate stack respectively include a gate conductor and a gate dielectric, the gate dielectric is located between the gate conductor and the substrate, the gate conductor is a polysilicon layer, and an equivalent dopant of the gate conductor in the semiconductor device is a first doping type or a second doping type.
Preferably, in the process of forming the first gate stack and the second gate stack, the gate conductor is polysilicon of a second doping type; in the process of forming the second doping region, the second doping type dopant in the gate conductor is combined with the first doping type dopant; the plurality of via holes include at least one via hole penetrating through the interlayer dielectric layer to the gate conductor, and in the step of forming the second source and drain ohmic contact regions and the channel contact region, the dopant of the second doping type of the gate conductor is combined with the dopant of the first doping type, and the equivalent dopant of the gate conductor is maintained as the second doping type.
Preferably, in the process of forming the first gate stack and the second gate stack, the gate conductor is polysilicon of a first doping type, and in the process of forming the first source region, the first drain region and the first doping region, at least a dopant of the first doping type in the gate conductor in the first gate stack is combined with a dopant of a second doping type; implanting dopants of the first doping type into the gate conductor during formation of the second doped region; the plurality of channel holes comprise at least one channel hole penetrating through the interlayer dielectric layer to reach the gate conductor, and in the step of forming the second source ohmic contact region, the second drain ohmic contact region and the channel contact region, the first doping type dopant is injected into the gate conductor, and the equivalent dopant of the gate conductor is maintained to be the first doping type.
Preferably, before the step of forming the first gate stack and the second gate stack, the method further comprises: forming a first well region in a first region of the substrate, forming a second well region in a second region of the substrate, and forming a third well region in a third region of the substrate, the third well region being adjacent to the first well region and the second well region, respectively; the isolation structure is used as a part of the hard mask in the step of forming the first source region and the first drain region, the second source region and the second drain region, the first doping region and the channel region.
Preferably, the process of forming the first well region, the second well region and the third well region includes: shielding by using a third photoresist mask to form a third well region of a second doping type in a third region of the substrate; removing the third photoresist mask, and forming active regions in the first region, the second region and the third region on the substrate by using the first photoresist mask; removing the first photoresist mask, adopting a second photoresist mask to shield the third well region in the substrate, forming a first well region of a first doping type in a first region of the substrate, and forming a second well region of the first doping type in a second region of the substrate; and shielding by using the second photoresist mask, forming a compensation region of a first doping type on partial surfaces of the first well region and the second well region by using the active region as a hard mask, and removing the second photoresist mask, wherein in the process of forming the isolation structure, the active region is used as a part of the hard mask, and then the active region is removed.
Preferably, the process of forming the first well region, the second well region and the third well region includes: forming active regions in a first region, a second region and a third region on the substrate by using a first photoresist mask; removing the first photoresist mask, shielding by adopting a third photoresist mask, and forming a third well region of a second doping type in a third region of the substrate; shielding a third well region in the substrate by using a second photoresist mask, forming a first well region of a first doping type in a first region of the substrate, and forming a second well region of the first doping type in a second region of the substrate; and shielding by adopting the second photoresist mask, forming a compensation region of a first doping type on partial surfaces of the first well region and the second well region by adopting the active region as a hard mask, and then removing the second photoresist mask, wherein in the process of forming the isolation structure, the active region is used as a part of the hard mask, and then the active region is removed.
Preferably, the implantation energy of the dopants of the first doping type forming the first and second well regions of the first doping type is such that the dopants are able to penetrate the active region.
Preferably, the implantation energy of the dopant of the first doping type implanted when forming the compensation region is such that the dopant is not able to penetrate the active region.
Preferably, the isolation structure includes at least one of a field oxide region and a shallow trench isolation.
Preferably, the first doping type is opposite to the second doping type, the first doping type is P-type, and the second doping type is N-type.
According to another aspect of the present invention, there is provided a semiconductor device including: a substrate; a first well region of the first doping type located in the first region of the substrate and a second well region of the first doping type located in the second region; a first gate stack over the first well region; the semiconductor device comprises a first source region and a first drain region of a second doping type, a first doping region of the second doping type, and a second doping region of the first doping type, wherein the first source region and the first drain region are located in the first well region, the first doping region of the second doping type is located in the second region, the second doping region of the first doping type is located in the second well region, at least part of the second doping region is located in the second well region, extends outwards to be in contact with the first doping region to form a PN structure, and dopants of the second doping type of the first source region, the first drain region and the first doping region are compounded with dopants of the first doping type in the second doping region.
Preferably, the method further comprises the following steps: the first region, the second region and the third region are distributed in parallel, and the third well region is respectively adjacent to the first well region and the second well region; a second gate stack over the third well region; and a second source region and a second drain region of the first doping type located in the third well region, and a channel region of the first doping type located in the second well region and isolated from the second doping region, wherein the doping dose of the channel region, the second source region, and the second drain region is the same as the doping dose of the second doping region.
Preferably, the method further comprises the following steps: the interlayer dielectric layer is positioned above the first gate stack and the second gate stack; a plurality of channel holes penetrating through the interlayer dielectric layer and reaching at least the first source region and the first drain region, the second source region and the second drain region, the first doped region and the channel region, respectively; and a plurality of conductive vias formed by filling the plurality of via holes with a conductive material.
Preferably, the first source region and the first drain region respectively include a first source ohmic contact region and a first drain ohmic contact region, the second source region and the second drain region respectively include a second source ohmic contact region and a second drain ohmic contact region, the first doped region includes a first doped contact region, and the channel region includes a channel contact region.
Preferably, the first gate stack and the second gate stack respectively include a gate conductor and a gate dielectric, the gate dielectric is located between the gate conductor and the substrate, the plurality of via holes include at least one via hole penetrating through the interlayer dielectric layer to reach the gate conductor, and an equivalent dopant of the gate conductor is of a first doping type or a second doping type.
Preferably, the method further comprises the following steps: and the isolation structure is positioned on the surface of the substrate between the adjacent well regions and extends downwards along the surface of the substrate.
Preferably, the method further comprises the following steps: and the compensation region is positioned on part of the surface of the first well region and has the first doping type.
Preferably, the isolation structure includes at least one of a field oxide region and a shallow trench isolation.
Preferably, the first doping type is opposite to the second doping type, the first doping type is P-type, and the second doping type is N-type.
Preferably, the semiconductor device is a BCD device.
Preferably, the semiconductor device comprises at least a CMOS device and at least one of a diode, a resistor, a capacitor, a low voltage triac, a high voltage semiconductor device.
Preferably, the high voltage semiconductor device includes, but is not limited to: high-voltage JFET device, gate oxide high-voltage MOS device and field oxide high-voltage MOS device.
The invention provides a semiconductor device and a manufacturing method thereof.A first semiconductor device structure is formed in a first region of a substrate, a third semiconductor device structure is formed in a third region of the substrate, and a diode device structure is formed in a second region of the substrate. After forming a first source region and a first drain region in the first semiconductor device structure and a first doping region in the second semiconductor device structure and removing the photoresist mask, implanting a first doping type dopant into the substrate to form a PN structure in the second semiconductor device and a channel region of the first doping type. And compounding the first source region and the first drain region implanted into the first semiconductor device structure and the first doping type dopant implanted into the first doping region in the second semiconductor device structure in the step by using the first doping type dopant in the first source region, the first drain region and the first doping region, and maintaining the equivalent dopants of the first source region, the first drain region and the first doping region as the second doping type. Therefore, when the PN structure and the channel region are formed in the second region, the second doping region which is in contact with the first doping region is formed without using additional masks and photoetching operation, namely, a diode with equivalent voltage resistance to the existing diode, such as a diode in a specific region in a voltage stabilizing diode or a triode, can be manufactured under the current simple process of reducing photoetching. Compared with the conventional method, the method has the advantages of reducing the photoetching times and reducing the manufacturing cost.
Preferably, in the process of forming the PN structure, the second source region and the second drain region of the first doping type are simultaneously formed in the third well region of the third region, and for the above reasons, when the second source region and the second drain region of the second semiconductor device structure are formed, additional masks and photolithography operations are not required, so that the manufacturing cost is reduced.
Preferably, when the second source ohmic contact region, the second drain ohmic contact region and the channel contact region are formed, a channel hole penetrating through the interlayer dielectric layer and reaching the first source region and the first drain region, the second source region and the second drain region, the first doping region and the channel region is used as an injection channel to inject a dopant of the first doping type, so as to form the second source ohmic contact region, the second drain ohmic contact region and the channel contact region. Further, the first source region, the first drain region, and the equivalent dopant of the second doping type in the first doping region are compounded with the dopant of the first doping type implanted into the first source region and the first drain region in the first semiconductor device structure and the dopant of the first doping type implanted into the first doping region in the second semiconductor device structure in this step, and the equivalent dopant of at least partial regions of the first source region, the first drain region, and the first doping region is maintained as the second doping type to serve as the first source ohmic contact region, the first drain ohmic contact region, and the first doping contact region. Therefore, when the second source contact, the second drain ohmic contact region and the channel contact region are formed, additional masks and photoetching steps are not needed to form the second source ohmic contact region, the second drain ohmic contact region and the channel contact region, and the manufacturing cost is reduced.
Preferably, the isolation structure is formed between each adjacent well region, before the field oxide region serving as the isolation structure is formed, an active region is formed before the well region of the first doping type is formed, and then a compensation region of the first doping type is formed on a part of the surface of the well region of the first doping type by using the active region as a hard mask, so as to compensate for the loss of the dopant of the well region of the first doping type due to the formation of the field oxide region. Meanwhile, when the compensation region is formed, the active region is formed before the first doping type well region is formed, then the photoresist mask used for shielding the second doping type well region is not removed after the first doping type well region is formed, the first doping type well region is formed through one-time photoetching by adopting high-energy injection, the compensation region is formed on at least part of the surface of the first doping type well region by adopting low-energy injection, an additional mask is not needed to shield the second doping type well region, and the compensation region is formed through photoetching, so that the process steps are simplified, and the manufacturing cost is reduced.
Preferably, the doping step of the gate conductor in the present invention can be completed in the process of forming the first source region, the first drain region, and the first doped region of the second doping type, or can be completed in the process of forming the second source region, the second drain region, the second doped region, and the channel region of the first doping type, without additional control of the doping amount of the polysilicon doping, thereby simplifying the manufacturing process.
On the basis of the manufacturing process of the semiconductor device, semiconductor devices such as BCD devices, bi-CMOS devices, CMOS devices and the like are formed according to the requirements of different occasions.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 shows a schematic structural diagram of a semiconductor device of an embodiment of the present invention.
Fig. 2 is a schematic flow chart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 3A to 3G show schematic structural diagrams of each specific step in the semiconductor device manufacturing process.
Fig. 4 is a flow chart illustrating the formation of the first to third well regions according to another embodiment of the present invention.
Fig. 5A to 5E are schematic structural views showing each detailed step in forming the first to third well regions.
Detailed Description
The present application will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
Numerous specific details of the present application are set forth below in order to provide a more thorough understanding of the present application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of semiconductor devices, are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 shows a schematic structural diagram of a semiconductor device of an embodiment of the present invention.
As shown in fig. 1, the semiconductor device includes a substrate 100, a first semiconductor device structure formed in a first region 111 of the substrate, a third semiconductor device structure formed in a third region 112 of the substrate, and a second semiconductor device formed in a second region 113 of the substrate, the third region 112 in the substrate 100 being adjacent to each other between the first region 111 and the second region 113, respectively.
The semiconductor device at least comprises a CMOS device and at least one of a diode, a resistor, a capacitor, a low-voltage transverse triode, a low-voltage longitudinal triode and a high-voltage semiconductor device. The high voltage semiconductor devices include, but are not limited to: high-voltage JFET device, gate oxide high-voltage MOS device and field oxide high-voltage MOS device.
The first semiconductor device structure includes a first well region 110 of a first doping type in a first region 111 of a substrate, a first gate stack located above the first well region 110, a first source region 711 and a first drain region 712 of a second doping type located on two sides of the first gate stack and in the first well region 110, respectively, and an interlayer dielectric layer 810 located above the first gate stack, where the first gate stack includes a gate conductor 320 located in the first region 111, a gate dielectric 310 located between the gate conductor 320 and the first well region 110 in the first region 111, and gate sidewalls 330 located at two side walls of the gate conductor 320 and the gate dielectric 310 in the first region 111, and the gate conductor 320 is polysilicon. The first semiconductor device structure further includes a conductive via 820 penetrating the interlayer dielectric layer 810 and electrically connected to the gate conductor 320, the first source region 711, and the first drain region 712, respectively. A partial region of the first source region 711 contacting the conductive via 820 is used as a first source ohmic contact region, a partial region of the first drain region 712 contacting the conductive via 820 is used as a first drain ohmic contact region, and the first source ohmic contact region and the first drain ohmic contact region are of a second doping type. At least a portion of the surface of the first well region 110 under the field oxide region 200 is used as a P-shaped compensation region.
The second semiconductor device structure includes a second well region 130 of the first doping type located in the substrate second region 113, a second doping region 732 of the first doping type located at least partially in the second well region 130, a first doping region 731 of the second doping type laterally in face contact with the second doping region 732, a channel region 733 of the first doping type located in the second well region 130 and isolated from the second doping region 732, and an interlayer dielectric layer 810 located over the substrate 100. Wherein the second doped region 732 of the first doping type is in contact with the first doped region 731 of the second doping type to form a PN junction. The second semiconductor device structure further includes a conductive via 820 penetrating the interlayer dielectric layer 810 and electrically connected to the first doped region 731 and the channel region 733, respectively. A portion of the first doped region 731 contacting the conductive via 820 is used as a first doped contact region, a portion of the channel region 733 contacting the conductive via 820 is used as a channel contact region, the first doped contact region is of the second doping type, and the channel contact region is of the first doping type. At least a portion of the surface of the second well 130 under the field oxide region 200 is a P-type compensation region.
The third semiconductor device structure includes a third well region 120 of the second doping type located in the third region 112 of the substrate, a second gate stack located above the third well region 120, a second source region 721 and a second drain region 722 of the first doping type located on both sides of the second gate stack and located in the third well region 120, and an interlayer dielectric layer 810 located above the second gate stack, where the second gate stack includes a gate conductor 320 located in the third region 112, a gate dielectric 310 located between the gate conductor 320 and the third well region 120 in the third region 112, and gate spacers 330 located on both side walls of the gate conductor 320 and the gate dielectric 310 in the third region 112, and the gate conductor 320 is polysilicon. The third semiconductor device structure further includes a conductive via 820 extending through the interlayer dielectric layer 810 and electrically connected to the gate conductor 320, the second source region 721, and the second drain region 722, respectively. A portion of the second source region 721 in contact with the conductive via 820 is used as a second source ohmic contact region, a portion of the second drain region 722 in contact with the conductive via 820 is used as a second drain ohmic contact region, and the second source ohmic contact region and the second drain ohmic contact region are of the first doping type.
The first to third regions are distributed in parallel, the third well region 120 is adjacent to the first well region 110 and the second well region 130, and the adjacent well regions are isolated by a field oxide region 200 located on the upper surface of the substrate 100 and extending downward along the upper surface of the substrate.
The dopants of the second source region 721, the second drain region 722, the second doped region 732 and the channel region 733 are of the first doping type, the dopants of the second doping type in the first source region 711, the first drain region 712, the first doped region 731 and the first source ohmic contact region, the first drain ohmic contact region and the first doped contact region are combined (combine), the dopants of the first doping type in the second source region 721, the second drain region 722, the second doped region 732 and the channel region 733, and the equivalent dopants of the first source region 711, the first drain region 712 and the first doped region 731 are maintained as the second doping type. The dopants in the first source ohmic contact region, the first drain ohmic contact region, and the first doped contact region include dopants of the second doping type, dopants of the first doping type in the second source region 721, the second drain region 722, the second doping region 732, and the channel region 733, and dopants of the first doping type in the second source ohmic contact region, the second drain ohmic contact region, and the channel contact region, and equivalent dopants of the first source ohmic contact region, the first drain ohmic contact region, and the first doped contact region are maintained at the second doping type. The gate conductor 320 in the first and second gate stacks is polysilicon of either the first doping type or the second doping type. The first doping type is P type, and the second doping type is N type. In other embodiments, the first doping type is N-type and the second doping type is P-type.
Fig. 2 is a schematic flow chart showing a method for manufacturing a semiconductor structure according to an embodiment of the present invention, and fig. 3A to 3G are schematic structural diagrams showing each specific step in a semiconductor device manufacturing process.
In this embodiment, a manufacturing step of the semiconductor device provided in fig. 1 is explained as an example.
As shown in fig. 2, in step S10, a first well region is formed in a first region of the substrate, a second well region is formed in a second region, and a third well region is formed in a third region of the substrate. As shown in fig. 3A, a first well region 110 of the first doping type is formed in a first region 111 of the substrate 100, a second well region 130 of the first doping type is formed in a second region 113, and a third well region 120 of the second doping type is formed in a third region 112. The third well region 120 is adjacent to the first well region 110 and the second well region 130.
In step S20, isolation structures are formed between the first well region, the second well region, and the third well region and in the second well region, respectively, extending downward on and along the substrate surface. As shown in fig. 3B, a local Oxidation of Silicon (LOCOS) or Chemical Vapor Deposition (CVD) is used to form a field oxide region 200 as an isolation structure at least between the first well region 110 and the third well region 120, between the third well region 120 and the second region 113, and in the second well region 130, on and along the upper surface of the substrate 100. In other embodiments, a trench is formed between adjacent well regions to serve as an isolation structure to achieve isolation, wherein the depth of the trench is related to the depth of the adjacent well regions or doped regions, for example.
In step S30, a first gate stack is formed over the first well region and a second gate stack is formed over the third well region. As shown in fig. 3C, a first gate stack and a second gate stack are formed over the first well region 110 and the third well region 120, respectively. Further, impurities and formed oxide layers in the substrate 100 exposed to the air are cleaned, and the substrate enters an oxidation furnace to grow a gate dielectric 310. The substrate 100 is then placed in a low pressure CVD apparatus with silane being introduced and the silane decomposed to deposit a layer of polysilicon on the surface of the gate dielectric 310. And (4) utilizing deep ultraviolet lithography technology to imprint the polysilicon in the lithography area. The deposited polysilicon is etched by using an anisotropic plasma etcher to obtain the gate dielectric 310 and the gate conductor 320 over the first well region 110, and the gate dielectric 310 and the gate conductor 320 over the third well region 120, respectively. Then, gate spacers 330 are formed on the sidewalls of the two ends of the gate conductor 320 and the gate dielectric 310 in the first region 111, respectively, to form a first gate stack, and gate spacers 330 are formed on the sidewalls of the two ends of the gate conductor 320 and the gate dielectric 310 in the third region 112, to form a second gate stack. The polysilicon of the gate conductor 320 may be doped P-type or N-type. In other embodiments, the polysilicon of the gate conductor is doped with the second doping type during the formation of the first source and first drain regions and the third source and third drain regions, and in this embodiment, the equivalent doping type of the gate conductor in the semiconductor device is the same as the initial doping type of the gate conductor. In other embodiments, the polysilicon of the gate conductor may be doped with the first doping type during the formation of the second source region and the second drain region such that the equivalent doping type of the gate conductor in the semiconductor device is consistent with the initial doping type of the gate conductor.
In step S40, a first source region and a first drain region of the second doping type are formed in the first well region, and a first doping region of the second doping type is formed in the second region. As shown in fig. 3D, the substrate third region 112 is masked with a photoresist mask to mask the third well region 120, the second gate stack, and at least a portion of the second region 113, and a second doping type dopant is implanted using the first gate stack and the field oxide region 200 as a hard mask to form a first source region 711 and a first drain region 712 of the second doping type in the first well region 110, and a first doping region 731 of the second doping type in the second region 113 near the third well region 120. The implantation energy, the dopant amount, and the implantation angle of the dopants forming the first source region 711, the first drain region 712, and the first doped region 731 of the first doping type may be further selected according to the requirements of the semiconductor device on voltage endurance, size, current, and the like.
In step S50, a second source region and a second drain region of the first doping type are formed in the third well region, and a PN structure is formed in the second region and a channel region is formed in the second well region. As shown in fig. 3E, using the first gate stack in the first region 111, the second gate stack in the third region 112, and the field oxide region 200 as a hard mask, a first doping type dopant is implanted in a blanket implantation manner to form a second source region 721 and a second drain region 722 of the first doping type in the third well region 120, a second doping region 732 of the first doping type extending laterally outward is formed in the second well region 130, and a channel region 733 isolated from the second doping region 732 by the field oxide region 200 is formed in the second well region 130. The second doped region 732 contacts the first doped region 731 to form a PN structure. Wherein the dopant amount of the N-type dopant implanted in step S04 is higher than the dopant amount of the P-type dopant so that the first source region and the first drain region and the third source region and the third drain region form ohmic contacts. Further, in step S50, the dopant of the first doping type implanted into the first source region 711, the first drain region 712, and the first doping region 731 in the second region 113 of the first region 111 is recombined with the dopant of the second doping type implanted into the first source region 711, the first drain region 712, and the first doping region 731 in the first region 111, the first drain region 712, and the second doping region 113 in step S40, and the equivalent dopant of the first source region 711, the first drain region 712, and the first doping region 731 obtained in this step is maintained as the second doping type. In forming the second source region 721 and the second drain region 722 of the P-type third semiconductor device, since the first doping type dopant implanted into the first semiconductor device structure and the second semiconductor device structure can be recombined and does not affect the performance of the first semiconductor device and the second semiconductor device, it is not necessary to use a photoresist mask to block the first region 111 and at least a portion of the second region 113 to form the second source region 721 and the second drain region 722 in the third region 112, to form the PN structure in the second region 113, and to form the channel region 733 in the second well region 130 in this step.
In step S60, a plurality of via holes penetrating the interlayer dielectric layer are formed over the first gate stack and the second gate stack. As shown in fig. 3F, an interlayer dielectric layer 810 is deposited and formed over the structure shown in fig. 3E, and a via hole 811 reaching the gate conductor 320, the second source region 721, the second drain region 722, the first doped region 731, and the channel region 733 on the first source region 711, the first drain region 712, the first region 111, and the third region 112 is formed through the interlayer dielectric layer 810. In other embodiments, the via hole 811 reaching the first source region 711, the first drain region 712, the second source region 721, the second drain region 722, the first doped region 731, and the channel region 733 is formed through the interlayer dielectric layer 810 in this step, and the via hole 811 reaching the gate conductor 320 on the first region 111 and the third region 112 is further formed through the interlayer dielectric layer 810 after step S70.
In step S70, second source and drain ohmic contact regions are formed at the second source and drain regions and a channel contact region is formed at the channel region. As shown in fig. 3G, a first doping type dopant is implanted using the interlayer dielectric layer 810 as a hard mask and using the channel hole 811 as an implantation channel, so as to form a second source ohmic contact region and a second drain ohmic contact region in a portion of the third region 112 where the second source region and the second drain region contact the channel hole 811, and form a channel contact region in a portion of the second region 113 where the channel region 733 contacts the channel hole 811. The P-type dopant injected into the first source region 711 and the first drain region 712 in the first region 111 and the first doping region 731 in the second region 113 in this step is recombined, so that equivalent dopants of the first source ohmic contact region, the first drain ohmic contact region, and the first doping contact region respectively formed in the first source region 711 and the first drain region 712 in the first region 111 and the partial region where the first doping region 731 in the second region 113 is in contact with the channel hole 811 in step S40 are maintained as the second doping type. The doping dose of the ions implanted this time is lower than the doping dose of the N-type dopant implanted when the first source region, the first drain region and the first doping region are formed. Wherein if the gate conductor 320 in forming the first gate stack and the second gate stack in the semiconductor device is a polysilicon layer of the second doping type, the equivalent dopant of the final gate conductor in the semiconductor device is maintained at the second doping type. When the gate conductor 320 in the semiconductor device is formed as a polysilicon layer of the first doping type during the formation of the gate stack, the equivalent dopant of the final gate conductor in the semiconductor device remains at the first doping type. The polysilicon in the gate conductor is simultaneously implanted with a dopant during the process of forming the source and drain regions, the dopant is the same as the dopant during the process of forming the source and drain regions, and the dopant is compounded by a part of the initial dopant in the gate conductor 320 to maintain the initial doping type.
In step S80, the via hole is filled to form a conductive via. As shown in fig. 1, a conductive channel 820 is formed in the channel hole 811 using a conductive material such that the gate conductor 320, the first source region 711, and the first drain region 712 in the first semiconductor device structure are connected to the outside through the conductive channel 820, the gate conductor 320, the second source region 721, and the second drain region 722 in the third semiconductor device structure are connected to the outside through the conductive channel 820, and the first doped region 731 and the channel region 733 in the second semiconductor device structure are connected to the outside through the conductive channel 820.
Next, a passivation layer may also be formed over the conductive via 820 in the structure shown in fig. 1.
Fig. 4 is a schematic flow chart illustrating formation of the first to third well regions in another embodiment of the present invention, and fig. 5A to 5E are schematic structural diagrams illustrating each specific step in the process of forming the first to third well regions.
As shown in fig. 4 and fig. 5A to 5E, the process of forming the first to third well regions in this embodiment includes the following steps:
in step S11, a third well region of the second doping type is formed in a third region of the substrate. Further, as shown in fig. 5A, a first oxide layer is formed on the P-type substrate 100, for example, a silicon dioxide layer is formed by a thermal oxidation method; and etching the first oxide layer by using a third photoresist mask 330, positioning the second doping type third well region 120 in the substrate 100, removing the photoresist, then performing high-energy N-type ion implantation, annealing, removing the first oxide layer, further forming the third well region 120 in the third region 112 of the substrate 100, and simultaneously forming a step difference on the removed part of the oxide layer, so that the third well region can be used for subsequent photoetching alignment and the conventional alignment photoetching step is omitted. The third photoresist mask 330 is then removed.
In step S12, an oxide layer is formed on the substrate and a nitride layer is formed on the oxide layer. Next, as shown in fig. 5B, an oxide layer 201 and a nitride layer 202 are sequentially deposited on the surface of the substrate 100, wherein the oxide layer 201 is, for example, a silicon dioxide layer, and the nitride layer 202 is, for example, a silicon nitride layer.
In step S13, active regions are formed in the first region, the second region, and the third region of the substrate. Next, as shown in fig. 5C, the oxide layer 201 and the nitride layer 202 are etched by using the first photoresist mask 310 to expose portions of the surfaces of the first region 111, the third region 112 and the second region 113 of the substrate 100 to form active regions. The active area after photoetching is used as a hard mask for forming a compensation area and an isolation structure in the subsequent process.
In step S14, a photoresist mask is used to mask the third well region, and a first well region of the first doping type is formed in the first region and a second well region of the first doping type is formed in the second region. Further, as shown in fig. 5D, a second photoresist mask 320 is used to shield the third well region 120 in the substrate 100, and a high energy implantation is performed to form the first well region 110 of the first doping type in the first region 111 and the second well region 130 of the first doping type in the second region 113 of the substrate 100, wherein the implantation energy of the first doping type dopant subjected to the high energy implantation enables the dopant to penetrate through the active region. In other embodiments, a process of multiple high energy implants may be employed to form the first well region 110.
In step S15, the compensation regions of the first doping type are formed in the first well region and the second well region by using the photoresist mask and the active region as a hard mask. As shown in fig. 5E, further, on the basis of not removing the second photoresist mask 320, the active region is simultaneously used as a hard mask to form the compensation region of the first doping type on at least a portion of the surfaces of the first well region 110 and the second well region 130 of the first doping type, and then the second photoresist mask 320 is removed. The implantation energy of the dopant of the first doping type forming the compensation region is such that the dopant is not able to penetrate the active region. The second photoresist mask is then removed. Then, when forming the isolation structure, the active region as shown in the structure of fig. 5E is used as a hard mask to form the isolation structure 200, and then the active region is removed, and the subsequent steps are completed according to the above-mentioned manufacturing method of the semiconductor device to form the semiconductor device.
In other embodiments, in the process of forming the first to third well regions, an active region may be formed on the substrate by using a first photoresist mask, then a third photoresist mask is used to shield and perform high-energy implantation to form a third well region of the second doping type, then a second photoresist mask is used to perform high-energy implantation to form a first well region and a second well region of the first doping type, then the second photoresist mask is continuously used to shield and the active region is used as a hard mask, and a compensation region of the first doping type is formed on at least part of surfaces of the first well region and the second well region of the first doping type. The single photolithography step is the same as the single step process for forming the first to third well regions provided above. Preferably, in the process of high-energy implantation of the first well region, the second well region and the third well region of the first doping type, the high-energy implantation may be performed a plurality of times to form the second well region.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
In accordance with the embodiments of the present application, as set forth above, these embodiments are not intended to be exhaustive or to limit the disclosure to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated.
Claims (28)
1. A semiconductor device manufacturing method, comprising:
forming a first gate stack on a first well region of a first region of a substrate, wherein the first well region is of a first doping type;
shielding at least part of a second region of the substrate by adopting a photoresist mask, forming a first source region and a first drain region of a second doping type in the first well region by adopting the first gate stack as a hard mask, and forming a first doping region of the second doping type in the second region of the substrate; and
removing the photoresist mask, performing normal injection to form a second doped region of the first doping type in a second well region of the second region, wherein the second doped region extends outwards along the second well region and contacts with the first doped region to form a PN structure, the second well region is of the first doping type,
in the step of forming the second doping region, the second doping type dopants of the first source region and the first drain region and the first doping region are combined with the first doping type dopants, and the equivalent dopants of the first source region and the first drain region and the first doping region are maintained as the second doping type.
2. The manufacturing method according to claim 1, wherein a dopant amount of the dopant of the second doping type forming the first source and drain regions and the first doping region is higher than a dopant amount of the dopant of the first doping type forming the second doping region so that the first source and drain regions form an ohmic contact.
3. The manufacturing method according to claim 1, wherein in the process of forming the first gate stack, a second gate stack is formed on a third well region of a third region of the substrate, the third well region being of a second doping type, the first region, the second region and the third region being distributed in parallel with each other, the third well region being adjacent to the first well region and the second well region, respectively;
in the process of forming the second doped region, a second source region and a second drain region of the first doping type are formed in the third well region, and a channel region of the first doping type is formed in the second well region.
4. The manufacturing method of claim 3, wherein after forming the first source and drain regions, the second source and drain regions, and the PN structure, further comprising:
forming an interlayer dielectric layer on the first gate stack and the second gate stack;
forming a plurality of channel holes which penetrate through the interlayer dielectric layer and at least respectively reach the first source region and the first drain region, the second source region and the second drain region, the first doped region and the channel region; and
filling the plurality of via holes with a conductive material to form a plurality of conductive vias.
5. A manufacturing method according to claim 4, wherein, after forming a conductive channel, portions of the first source and drain regions exposed by the channel hole and in contact with the conductive channel serve as first source and drain ohmic contact regions, and portions of the first doped region exposed by the channel hole and in contact with the conductive channel serve as first doped contact regions.
6. The manufacturing method according to claim 5, wherein, between the step of forming the passage hole and the conductive passage, further comprising:
implanting a dopant of a first doping type using the plurality of channel holes as an implantation channel to form a second source ohmic contact region and a second drain ohmic contact region in the third well region and a channel contact region in the second well region of the substrate,
the second doping type dopants of the first source region, the first drain region and the first doping region are compounded with the first doping type dopants, and equivalent dopants of a part of regions, exposed through the channel hole, of the first source region, the first drain region and the first doping region, serving as the first source ohmic contact region, the first drain ohmic contact region and the first doping contact region, are maintained as the second doping type.
7. The manufacturing method of claim 6, wherein the first gate stack and the second gate stack comprise a gate conductor and a gate dielectric, respectively, the gate dielectric being between the gate conductor and the substrate, the gate conductor being a polysilicon layer, and an equivalent dopant of the gate conductor in the semiconductor device being of the first doping type or the second doping type.
8. The manufacturing method according to claim 7, wherein in the process of forming the first gate stack and the second gate stack, the gate conductor is polysilicon of a second doping type;
in the process of forming the second doping region, the second doping type dopant in the gate conductor is combined with the first doping type dopant;
the plurality of via holes includes at least one via hole extending through the interlevel dielectric layer to the gate conductor,
in the step of forming the second source and drain ohmic contact regions and the channel contact region, the dopant of the second doping type of the gate conductor is combined with the dopant of the first doping type, and the equivalent dopant of the gate conductor is maintained at the second doping type.
9. The manufacturing method of claim 7, wherein the gate conductor is polysilicon of a first doping type during the forming of the first and second gate stacks,
in the process of forming the first source region, the first drain region and the first doping region, at least the first doping type dopant in the gate conductor in the first gate stack is combined with the second doping type dopant;
implanting dopants of the first doping type into the gate conductor during formation of the second doped region;
the plurality of via holes includes at least one via hole extending through the interlevel dielectric layer to the gate conductor,
in the step of forming the second source and drain ohmic contact regions and the channel contact region, the dopant of the first doping type is implanted into the gate conductor,
the equivalent dopant of the gate conductor is maintained at the first doping type.
10. The method of manufacturing of claim 3, wherein prior to the step of forming the first and second gate stacks, further comprising:
forming a first well region in a first region of the substrate, forming a second well region in a second region of the substrate, and forming a third well region in a third region of the substrate, the third well regions being adjacent to the first well region and the second well region, respectively;
a substrate surface formed between adjacent well regions and an isolation structure extending down the substrate surface,
the isolation structure is used as a part of the hard mask in the step of forming the first source region and the first drain region, the second source region and the second drain region, the first doping region and the channel region.
11. The manufacturing method according to claim 10,
the process of forming the first well region, the second well region and the third well region comprises the following steps:
shielding by using a third photoresist mask to form a third well region of a second doping type in a third region of the substrate;
removing the third photoresist mask, and forming active regions in the first region, the second region and the third region on the substrate by using the first photoresist mask;
removing the first photoresist mask, adopting a second photoresist mask to shield the third well region in the substrate, forming a first well region of a first doping type in a first region of the substrate, and forming a second well region of the first doping type in a second region of the substrate;
forming a compensation region of a first doping type on partial surfaces of the first well region and the second well region by using the second photoresist mask for shielding and the active region as a hard mask, and then removing the second photoresist mask,
and in the process of forming the isolation structure, the active region is used as a part of a hard mask, and then the active region is removed.
12. The method of manufacturing of claim 10, wherein forming the first, second, and third well regions comprises:
forming active regions in a first region, a second region and a third region on the substrate by using a first photoresist mask;
removing the first photoresist mask, adopting a third photoresist mask for shielding, and forming a third well region of a second doping type in a third region of the substrate;
shielding a third well region in the substrate by using a second photoresist mask, forming a first well region of a first doping type in a first region of the substrate, and forming a second well region of the first doping type in a second region of the substrate;
forming a compensation region of a first doping type on partial surfaces of the first well region and the second well region by using the second photoresist mask as a hard mask and the active region as a mask, and removing the second photoresist mask,
and in the process of forming the isolation structure, the active region is used as a part of a hard mask, and then the active region is removed.
13. A method of manufacturing according to claim 11 or 12, wherein the implantation energy of the dopants of the first doping type forming the first and second well regions of the first doping type is such that the dopants can penetrate the active region.
14. The manufacturing method according to claim 11 or 12, wherein the implantation energy of the dopant of the first doping type implanted when forming the compensation region is such that the dopant is not able to penetrate the active region.
15. The method of manufacturing of claim 10, wherein the isolation structure comprises at least one of a field oxide region and a shallow trench isolation.
16. The method of manufacturing of claim 1, wherein the first doping type is opposite to the second doping type, the first doping type being P-type and the second doping type being N-type.
17. A semiconductor device, comprising:
a substrate;
a first well region of the first doping type located in the first region of the substrate and a second well region of the first doping type located in the second region;
a first gate stack over the first well region;
a first source region and a first drain region of a second doping type located in the first well region, a first doping region of the second doping type located in the second region, and a second doping region of the first doping type located at least partially in the second well region and extending outward to contact the first doping region to form a PN structure, the second doping region being located in the second region, and the first drain region being spaced apart from the first doping region,
and the second doping type dopants of the first source region, the first drain region and the first doping region are compounded with the first doping type dopants in the second doping region.
18. The semiconductor device of claim 17, further comprising:
the first region, the second region and the third region are distributed in parallel, and the third well region is respectively adjacent to the first well region and the second well region;
a second gate stack over the third well region; and
the second well region comprises a second source region and a second drain region which are positioned in the third well region and are of the first doping type, and a channel region which is positioned in the second well region and is isolated from the second doping region and is of the first doping type, wherein the doping doses of the channel region, the second source region and the second drain region are the same as the doping dose of the second doping region.
19. The semiconductor device of claim 18, further comprising:
the interlayer dielectric layer is positioned above the first gate stack and the second gate stack;
a plurality of channel holes penetrating through the interlayer dielectric layer and reaching at least the first source region and the first drain region, the second source region and the second drain region, the first doped region and the channel region, respectively; and
a plurality of conductive vias formed by filling the plurality of via holes with a conductive material.
20. The semiconductor device of claim 19, wherein the first source and first drain regions include a first source ohmic contact region and a first drain ohmic contact region, respectively, the second source and second drain regions include a second source ohmic contact region and a second drain ohmic contact region, respectively, and the first doped region includes a first doped contact region therein, and the channel region includes a channel contact region therein.
21. The semiconductor device of claim 20, wherein the first and second gate stacks comprise a gate conductor and a gate dielectric, respectively, the gate dielectric being between the gate conductor and the substrate, the plurality of via holes comprising at least one via hole through the interlevel dielectric layer to the gate conductor, the equivalent dopant of the gate conductor being either of the first doping type or the second doping type.
22. The semiconductor device of claim 17, further comprising:
and the isolation structure is positioned on the surface of the substrate between the adjacent well regions and extends downwards along the surface of the substrate.
23. The semiconductor device of claim 17, further comprising:
and the compensation region is positioned on part of the surface of the first well region and has the first doping type.
24. The semiconductor device of claim 22, wherein the isolation structure comprises at least one of a field oxide region and a shallow trench isolation.
25. The semiconductor device of claim 17, wherein the first doping type is opposite to the second doping type, the first doping type being P-type and the second doping type being N-type.
26. The semiconductor device of claim 17, wherein the semiconductor device is a BCD device.
27. The semiconductor device of claim 17, wherein the semiconductor device comprises at least a CMOS device and at least one of a diode, a resistor, a capacitor, a low voltage triac, a high voltage semiconductor device.
28. The semiconductor device of claim 27, wherein the high voltage semiconductor device includes, but is not limited to: high-voltage JFET device, gate oxide high-voltage MOS device and field oxide high-voltage MOS device.
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| EP0146181B1 (en) * | 1983-12-16 | 1989-03-15 | Koninklijke Philips Electronics N.V. | Semiconductor device comprising a combined bipolar-field effect transistor |
| US6071775A (en) * | 1997-02-21 | 2000-06-06 | Samsung Electronics Co., Ltd. | Methods for forming peripheral circuits including high voltage transistors with LDD structures |
| US9324785B2 (en) * | 2014-04-10 | 2016-04-26 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
| CN105185834B (en) * | 2015-10-19 | 2018-01-26 | 杭州士兰微电子股份有限公司 | Composite high pressure semiconductor devices |
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2019
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