CN106298981A - The double polycrystalline capacitance structures integrated with metal-oxide-semiconductor and manufacture method - Google Patents
The double polycrystalline capacitance structures integrated with metal-oxide-semiconductor and manufacture method Download PDFInfo
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- CN106298981A CN106298981A CN201610676009.3A CN201610676009A CN106298981A CN 106298981 A CN106298981 A CN 106298981A CN 201610676009 A CN201610676009 A CN 201610676009A CN 106298981 A CN106298981 A CN 106298981A
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 119
- 229920005591 polysilicon Polymers 0.000 claims abstract description 118
- 238000005530 etching Methods 0.000 claims abstract description 25
- 230000003647 oxidation Effects 0.000 claims description 23
- 238000007254 oxidation reaction Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 description 13
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 230000001590 oxidative effect Effects 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000000717 retained effect Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
The present invention provides a kind of double polycrystalline capacitance structures integrated with metal-oxide-semiconductor and manufacture method, first the method makes bottom crown and the dielectric layer of double polycrystalline electric capacity, then while making the polysilicon gate of metal-oxide-semiconductor, make double polycrystalline electric capacity top crown, thus can reduce the sidewall residual of metal-oxide-semiconductor polysilicon gate, additionally, compared to making double polycrystalline electric capacity bottom crown while making the polysilicon gate of metal-oxide-semiconductor, polycrystalline electric capacity top crown thickness can be improved, the double polycrystalline capacitance short-circuits caused when so can avoid contact with hole over etching, it is possible to reduce contact resistance.
Description
Technical field
The invention belongs to semiconductor integrated circuit field, be specifically related to the integrated double polycrystalline capacitance structures of a kind of metal-oxide-semiconductor and
Manufacture method.
Background technology
In field of manufacturing semiconductor devices, Analogous Integrated Electronic Circuits progressively develops to high-speed, high precision direction, circuit design
In need to use high-precision capacitor.At present frequently with electric capacity have: capacitance of PN junction, mos capacitance, double polycrystalline electric capacity and gold
Genus-metal capacitance.Capacitance of PN junction and mos capacitance use diffusion layer as bottom crown, there is substrate parasitics electric capacity, limit electric capacity
Caned additional voltage.Although metal-metal capacitor electrology characteristic is good, but manufacturing cost is high, complex process.Conventional double many
Brilliant electric capacity uses polysilicon to make bottom crown, has more preferable capacitor voltage characteristic, and tool compared to capacitance of PN junction and mos capacitance
There are the advantages such as high speed, low parasitism, low cost of manufacture.Integrated knot along with the development of semiconductor technology, double polycrystalline electric capacity and metal-oxide-semiconductor
The characteristic of structure and economic benefit are better than above-mentioned three kinds of electric capacity, thus are increasingly widely applied.
But, after the integrated morphology of the most double polycrystalline electric capacity and metal-oxide-semiconductor is made, past on the polysilicon gate sidewall of its metal-oxide-semiconductor
Toward there is sidewall residual, thus affect the pattern of metal-oxide-semiconductor polysilicon gate；It addition, when etching is for depositing the contact hole of metal,
Easily lead to double polycrystalline capacitance short-circuit.
Summary of the invention
The present invention provides a kind of double polycrystalline capacitance structures integrated with metal-oxide-semiconductor and manufacture method, to solve the most double polycrystalline
Electric capacity polysilicon gate pattern is poor, and the problem that double polycrystalline electric capacity are easy to short circuit when etching is for depositing the contact hole of metal.
First aspect according to embodiments of the present invention, it is provided that a kind of double polycrystalline capacitance structure manufacturers integrated with metal-oxide-semiconductor
Method, described method includes:
Trap is formed at substrate surface；
Field oxide is formed on described trap surface；
Bottom crown and the dielectric layer of double polycrystalline electric capacity is upwards sequentially formed on the surface of selected field oxide；
Gate oxide is formed in the described unlapped region of selected field oxide；
At surface deposition first polysilicon layer of described gate oxide and described dielectric layer, so that at described gate oxide
The polysilicon that surface is formed constitutes the polysilicon gate of metal-oxide-semiconductor with described gate oxide, is formed many on the surface of described dielectric layer
Crystal silicon constitutes the top crown of described pair of polycrystalline electric capacity；
Form the doped source drain region of described metal-oxide-semiconductor.
In the optional implementation of one, upwards sequentially form double polycrystalline electric capacity on the surface of selected field oxide
Before bottom crown and dielectric layer, described method also includes: form shielding protection in the unlapped region surface of described field oxide
Layer；Before the unlapped region of described field oxide forms gate oxide, described method also includes: remove described shielding protection
Layer.
In the optional implementation of another kind, the described surface at selected field oxide upwards sequentially forms double polycrystalline
Bottom crown and the dielectric layer of electric capacity include:
The second polysilicon layer is deposited above described trap；
The surface of described second polysilicon layer is carried out oxidation processes, to form polysilicon oxide layer；
Surface deposition second medium material layer at described polysilicon oxide layer；
Use photoetching and etching technics, upwards sequentially form the lower pole of double polycrystalline electric capacity on the surface of selected field oxide
Plate, first medium layer and second dielectric layer, the second polysilicon layer structure wherein formed on the surface of described selected field oxide
Becoming described bottom crown, the polysilicon oxide layer that described bottom crown surface is formed constitutes described first medium layer, described first medium
The second medium material layer that layer surface is formed constitutes described second dielectric layer.
In the optional implementation of another kind, the thickness of described top crown is 250～350nm, the thickness of described bottom crown
Degree is 100～150nm.
In the optional implementation of another kind, the thickness of described first medium layer is 4～5nm, described second dielectric layer
Thickness be 25～35nm.
Second aspect according to embodiments of the present invention, it is provided that a kind of double polycrystalline capacitance structures integrated with metal-oxide-semiconductor, including lining
The end, it is formed with trap at described substrate surface, is formed with field oxide on described trap surface, on selected field oxide surface upwards
It is sequentially formed with bottom crown and the dielectric layer of double polycrystalline electric capacity, is formed with grid in the described unlapped region of selected field oxide
Oxide layer, is formed with the first polysilicon layer, wherein at described gate oxide on the surface of described gate oxide and described dielectric layer
The surface polysilicon and the described gate oxide that are formed constitute the polysilicon gate of metal-oxide-semiconductor, formed on the surface of described dielectric layer
Polysilicon constitutes the top crown of described pair of polycrystalline electric capacity.
In the optional implementation of one, described dielectric layer includes first medium layer and second dielectric layer, described first
Dielectric layer be the polysilicon in described bottom crown is aoxidized after formed polysilicon oxide layer, described second dielectric layer is positioned at
Described first medium layer surface.
In the optional implementation of another kind, the thickness of described top crown is 250～350nm, the thickness of described bottom crown
Degree is 100～150nm.
In the optional implementation of another kind, the thickness of described first medium layer is 4～5nm, described second dielectric layer
Thickness be 25～35nm.
The invention has the beneficial effects as follows:
1, the present invention is by after the bottom crown of double polycrystalline electric capacity and dielectric layer complete, at the polycrystalline making metal-oxide-semiconductor
Double polycrystalline electric capacity top crown is made, it is possible to reduce the sidewall residual of metal-oxide-semiconductor polysilicon gate, it addition, the present invention is led to while Si-gate
Cross while forming polysilicon gate, form top crown, polycrystalline electric capacity top crown thickness can be improved, so can avoid contact with
Double polycrystalline capacitance short-circuits that hole over etching causes, it is possible to reduce contact resistance；
2, the present invention by upwards sequentially forming bottom crown and the medium of double polycrystalline electric capacity on selected field oxide surface
Before Ceng, form shielding protection layer in the unlapped region surface of field oxide, can avoid double polycrystalline electric capacity bottom crown and
Trap is polluted by dielectric layer forming process；It addition, the present invention by formed the bottom crown of double polycrystalline electric capacity and dielectric layer it
After, first this shielding protection layer is removed, then form the gate oxide being used for making the polysilicon gate of metal-oxide-semiconductor, polycrystalline can be improved
The making yield of Si-gate；
3, the present invention by carrying out oxidation processes to the bottom crown formed by polysilicon, and many by being formed after oxidation processes
Crystal silicon oxide layer, as first medium layer, can reduce the thickness of first medium layer, be effectively improved unit capacitance values and quality because of
Number；
4, the thickness that by the present invention in that top crown is 250～350nm, and the thickness of bottom crown is 100～150nm, permissible
On the basis of ensureing double polycrystalline electric capacity electrology characteristic, it is to avoid double polycrystalline capacitance short-circuits that top crown over etching causes.
Accompanying drawing explanation
Fig. 1-Fig. 7 is to be formed in each step in double polycrystalline capacitance structure manufacture processes that the present invention is integrated with metal-oxide-semiconductor
One embodiment schematic diagram of structure；
Fig. 8 is an example structure schematic diagram of the present invention double polycrystalline capacitance structures integrated with metal-oxide-semiconductor.
Detailed description of the invention
For the technical scheme making those skilled in the art be more fully understood that in the embodiment of the present invention, and make the present invention real
Execute the above-mentioned purpose of example, feature and advantage can become apparent from understandable, below in conjunction with the accompanying drawings to technical side in the embodiment of the present invention
Case is described in further detail.
In describing the invention, unless otherwise prescribed and limit, it should be noted that term " connects " should do broad sense manage
Solve, for example, it may be mechanically connected or electrical connection, it is also possible to be the connection of two element internals, can be to be joined directly together, it is possible to
To be indirectly connected to by intermediary, for the ordinary skill in the art, can understand as the case may be above-mentioned
The concrete meaning of term.
The present invention provides the manufacture method of a kind of double polycrystalline capacitance structures integrated with metal-oxide-semiconductor, including:
Step S101, substrate surface formed trap, and described trap surface formed field oxide.
In the present embodiment, with reference to Fig. 1, form trap 12 on substrate 100 surface, and form field oxide on the surface of trap 12
11, form shielding protection layer 13 in the unlapped region surface of field oxide 11, wherein this shielding protection layer 13 can be hot oxygen
Change layer.It should be noted that therefore in the embodiment of the present invention, this structure can owing to metal-oxide-semiconductor can be divided into PMOS and NMOS tube
Integrated with PMOS to include double polycrystalline electric capacity, double polycrystalline electric capacity are integrated with NMOS tube, or the while of double polycrystalline electric capacity and PMOS
Pipe and NMOS tube are integrated.When double polycrystalline electric capacity and PMOS are integrated, the trap in this step refers to N trap；When double polycrystalline electric capacity with
When NMOS tube is integrated, the trap in this step refers to p-well；When double polycrystalline electric capacity are the most integrated with PMOS and NMOS tube, this step
Trap in Zhou is the general name of N trap and p-well.In all accompanying drawings of the present invention, all with double polycrystalline electric capacity simultaneously with PMOS and NMOS
Manage integrated as a example by illustrate, those skilled in the art will appreciate that other two kinds of structures by description and the accompanying drawing of embodiment
Composition and manufacture method.
Step S102, the bottom crown upwards sequentially forming double polycrystalline electric capacity on the surface of selected field oxide and medium
Layer.
In the present embodiment, first, see Fig. 2, use conventional SPM+SC1+SC2 mode, field oxide 11 and shielding are protected
The surface of sheath 13 is deposited front cleaning, at surface (the i.e. trap of field oxide 11 and shielding protection layer 13 after having cleaned
The top of 12) deposit the second polysilicon layer 14, and inject high dose phosphorus, wherein the thickness of this second polysilicon layer 14 can be
100～150nm.The present invention, by before surface deposition second polysilicon layer of field oxide and shielding protection layer, is formed sediment
Clean before long-pending, the second polysilicon layer can be avoided to mix impurity in deposition process；By injecting phosphorus in the second polysilicon layer
Element, can improve the electric conductivity of this layer of polysilicon.
Secondly, see Fig. 3, use conventional SPM+SC1+SC2 mode, the surface of this second polysilicon layer 14 of deposit is entered
Clean before row oxidation, after cleaning completes, use the mode of boiler tube thermal oxide that the surface of this second polysilicon layer 14 is carried out oxygen
Change processes, and to form polysilicon oxide layer 15, wherein oxidizing temperature during oxidation processes can be 800 ± 10 DEG C, oxidizing atmosphere
For dry oxygen, the polysilicon oxide layer 15 formed after oxidation processes can be silicon dioxide layer, and its thickness can be 4～5nm.This
After, use conventional SPM+SC1+SC2 mode, polysilicon oxide layer 15 is deposited front cleaning, use vertical after cleaning completes
Formula boiler tube chemical vapor deposition method, at the surface deposition second medium material layer 16 of polysilicon oxide layer 15, wherein deposited
In journey, deposition temperature can be 760 ± 10 DEG C, and this second medium material layer can be silicon nitride layer, and its thickness can be 25～
35nm.The present invention is by, before the surface of this second polysilicon layer is carried out oxidation processes, carrying out aoxidizing front cleaning, can keep away
Exempt to mix impurity in the second polysilicon layer oxidizing process；By before deposit second medium material layer, clear before being deposited
Wash, second medium material layer can be avoided to mix impurity in deposition process.
Finally, see Fig. 4, use photoetching process and etching technics (such as dry method polycrystal etching machine), to the second polysilicon layer
14, polysilicon oxide layer 15 and second medium material layer 16 perform etching, except sequentially forming on selected field oxide 11 surface
Polysilicon, oxidation polysilicon and second medium material outside, by the polysilicon of other positions, oxidation polysilicon and second medium
Material all etches away, thus the polysilicon retained on selected field oxide 11 surface constitutes the bottom crown of double polycrystalline electric capacity, under
The oxidation polysilicon that polar board surface is formed constitutes the first medium layer of double polycrystalline electric capacity, second Jie that first medium layer surface is formed
Material constitutes the second dielectric layer of double polycrystalline electric capacity.Thus, upwards sequentially form on the surface of selected field oxide double many
The bottom crown of brilliant electric capacity and the dielectric layer being made up of first medium layer and second dielectric layer.
It is to be noted that the present embodiment is at the second polysilicon layer, polysilicon oxide layer and second medium material layer
After being completely formed, then use photoetching and etching technics, by the polysilicon of other positions in addition to above selected field oxide,
Oxidation polysilicon and second medium material all etch away, but those skilled in the art can also use and often form one layer of material
Material, just uses photoetching and etching technics to process this layer material.Such as, after forming the second polysilicon layer, light is first used
Carve and this second polysilicon layer is performed etching, in addition to the polysilicon on selected field oxide surface, by other positions by etching technics
The polysilicon at the place of putting all etches away, then the polysilicon on selected oxide layer surface is carried out oxidation processes, by that analogy.
Step S103, form gate oxide in the described unlapped region of selected field oxide, and at described gate oxidation
Layer and surface deposition first polysilicon layer of described dielectric layer, so that the polysilicon formed on the surface of described gate oxide and institute
Stating gate oxide and constitute the polysilicon gate of metal-oxide-semiconductor, the polysilicon formed on the surface of described dielectric layer constitutes described pair of polycrystalline electricity
The top crown held.
In the present embodiment, see Fig. 5, first remove shielding protection layer 13, then use conventional SPM+SC1+SC2 mode, to going
Except the surface of the trap 12 after shielding protection layer 13 is carried out, after having cleaned, carry out oxygen in the unlapped region of field oxide 11
Change processes, thus forms gate oxide 17, and wherein in oxidation processes, oxidizing temperature can be 850 ± 10 DEG C, oxidizing atmosphere
Can be dry oxygen, the thickness of the gate oxide 17 that oxidation processes is formed can be 7～10nm.Hereafter, low pressure chemical phase is used
Deposition growing technique, deposits the first polysilicon layer 18 on the surface of gate oxide 17 and second dielectric layer 16, and injects phosphorus, its
In the thickness of the first polysilicon layer 18 can be 250～350nm.The present invention is by injecting phosphorus in the first polysilicon layer, permissible
Improve the electric conductivity of this layer of polysilicon.
Due to during the bottom crown making double polycrystalline electric capacity and dielectric layer, it is possible to trap is polluted, therefore
The present invention passes through before selected field oxide surface upwards sequentially forms bottom crown and the dielectric layer of double polycrystalline electric capacity, on the scene
The unlapped region surface of oxide layer forms shielding protection layer, and the bottom crown of double polycrystalline electric capacity and dielectric layer can be avoided to be formed
Trap is polluted by journey.Further, since shielding protection layer may be made by the bottom crown of double polycrystalline electric capacity and dielectric layer forming process
Becoming to pollute, if directly using shielding protection layer to make the polysilicon gate of metal-oxide-semiconductor, then may cause the workability of polysilicon gate
Can be poor, therefore the present invention is by, after the bottom crown forming double polycrystalline electric capacity and dielectric layer, first going this shielding protection layer
Remove, then form the gate oxide being used for making the polysilicon gate of metal-oxide-semiconductor, the making yield of polysilicon gate can be improved.
See Fig. 6, use photoetching and etching technics (such as dry method polycrystal etching machine), the first polysilicon layer 18 is carved
Erosion, wherein in addition to the polysilicon on gate oxide 17 and second dielectric layer 16 surface, the polysilicon on other surface of positions all by
Etch away, thus the polysilicon being retained on second dielectric layer 16 surface constitutes the top crown of double polycrystalline electric capacity, is retained in grid
The polysilicon on oxide layer 17 surface and gate oxide 17 constitute the polysilicon gate of metal-oxide-semiconductor.Etching gas in etch processes
Body can be Cl2 and HBr, and flow can be in the range of 60～100SCCM.Discovery, double polycrystalline electric capacity and MOS is studied through applicant
After the integrated morphology of pipe is made, why on the polysilicon gate sidewall of metal-oxide-semiconductor, there is residual, be because in integrated morphology manufacture
During while making the polysilicon gate of metal-oxide-semiconductor, generally the most formed the bottom crown of double polycrystalline electric capacity, so at follow-up quarter
When erosion makes dielectric layer and the top crown of double polycrystalline electric capacity, generation substantial amounts of sidewall residual is retained in the polysilicon gate of metal-oxide-semiconductor
On.The present invention by after the bottom crown of double polycrystalline electric capacity and dielectric layer complete, is making polysilicon gate same of metal-oxide-semiconductor
Time make double polycrystalline electric capacity top crown, it is possible to reduce the sidewall residual on metal-oxide-semiconductor polysilicon gate.
Step S104, the doped source drain region of formation metal-oxide-semiconductor.
In the present embodiment, see Fig. 7, form lightly-doped source drain region (in diagram initially with photoetching, ion implantation technology
The content of the "-" ion in N-, P-mark is low), secondly deposit the thin film identical with first medium layer material, and lead to
Cross this thin film of anisotropic etching and at least form the side wall 19 being positioned at polysilicon gate 141 both sides, then use photoetching, ion implanting
Technique formed heavy-doped source drain region (in diagram in N+, P+ mark "+" content of ion is high), hereafter carry out annealing treatment
Reason, thus can define the doped source drain region of metal-oxide-semiconductor.Certainly, except using aforesaid way, it is also possible to use its other party existing
Formula forms the doped source drain region of metal-oxide-semiconductor.Hereafter, initially with low-pressure chemical vapor deposition growth technique, deposit the 3rd dielectric layer,
And use photoetching and etching technics, the 3rd dielectric layer is performed etching, thus forms the contact hole 20 for depositing metal, so
After by Metal deposition in contact hole 20, wherein this metal can use Ti/TiN/AlSiCu/TiN structure, and AlSiCu can use
AlSi or AlCu substitutes, and thickness is between 300～400nm.
At present polysilicon layer in the polysilicon gate of metal-oxide-semiconductor is had certain thickness requirement, and is generally forming polysilicon
Form double polycrystalline electric capacity bottom crown while grid, so make thickness and the thickness phase of polysilicon layer in polysilicon gate of bottom crown
Deng, in addition in view of cost of manufacture and the impact on the electric property of double polycrystalline electric capacity of the upper bottom crown general thickness, the most double many
In brilliant electric capacity, the thickness of top crown is typically smaller than the thickness of bottom crown.When making the contact hole 20 for depositing metal, due to
Top crown is relatively thin, and therefore top crown is easy to by over etching, thus causes double polycrystalline capacitance short-circuit.Directly thicken if used
The mode of pole plate avoids top crown over etching, then can increase cost of manufacture and can affect the electric property of double polycrystalline electric capacity.This
Invent by forming top crown while forming polysilicon gate, thickness and the polysilicon layer in polysilicon gate of top crown can be made
Thickness equal, and in the present invention, the thickness of top crown, more than the thickness of top crown in prior art, thus can avoid pole
Double polycrystalline capacitance short-circuits that plate over etching causes, and by when making bottom crown, making the thickness etc. of bottom crown in the present invention
The thickness of top crown in prior art, can make upper bottom crown general thickness in polysilicon capacitance not change, thus can
Not increase cost of manufacture, and on the basis of not affecting the electric property of double polycrystalline electric capacity, it is to avoid top crown over etching causes
Double polycrystalline capacitance short-circuits, and contact resistance can be reduced.Additionally, by the present invention in that the thickness of top crown is 250～350nm,
The thickness of bottom crown is 100～150nm, can be on the basis of ensureing double polycrystalline electric capacity electrology characteristic, it is to avoid quarter spent by top crown
Double polycrystalline capacitance short-circuits that erosion causes.
Owing to generally using depositing technics to be formed when currently forming first medium layer, limited by depositing technics, formed
The thickness of first medium layer the biggest, the present invention by carrying out oxidation processes to the bottom crown formed by polysilicon, and general
The dense multicrystalline silicon oxide layer formed after oxidation processes, as first medium layer, can reduce the thickness of first medium layer, effectively
Improve unit capacitance values and quality factor.
The present invention also provides for a kind of double polycrystalline capacitance structures integrated with metal-oxide-semiconductor, sees Fig. 8, and it can include substrate
100, it is formed with trap 12 on described substrate 100 surface, is formed with field oxide 11 on described trap 12 surface, in selected field oxidation
Layer 11 surface are upwards sequentially formed with bottom crown 14 and the dielectric layer of double polycrystalline electric capacity, do not cover at described selected field oxide 11
The region of lid is formed with gate oxide 17, is formed with the first polysilicon layer on the surface of described gate oxide 17 and described dielectric layer
18, the polysilicon 18 and the described gate oxide 17 that are wherein formed on the surface of described gate oxide 17 constitute the polysilicon of metal-oxide-semiconductor
Grid, the polysilicon 18 formed on the surface of described dielectric layer constitutes the top crown of double polycrystalline electric capacity.
Wherein, described dielectric layer includes first medium layer 15 and second dielectric layer 16, and described first medium layer 15 is for institute
Stating the polysilicon oxide layer formed after the polysilicon in bottom crown aoxidizes, described second dielectric layer 16 is positioned at described first and is situated between
Matter layer 15 surface.The thickness of described top crown is 250～350nm, and the thickness of described bottom crown is 100～150nm.Described first
The thickness of dielectric layer is 4～5nm, and the thickness of described second dielectric layer is 25～35nm.
As seen from the above-described embodiment, the present invention by after the bottom crown of double polycrystalline electric capacity and dielectric layer complete,
Double polycrystalline electric capacity top crown is made, it is possible to reduce the sidewall of metal-oxide-semiconductor polysilicon gate is residual while making the polysilicon gate of metal-oxide-semiconductor
Stay, it addition, the present invention is by forming top crown while forming polysilicon gate, the thickness of top crown can be improved, thus can
The double polycrystalline capacitance short-circuits caused during to avoid top crown over etching, it is possible to reduce contact resistance.It addition, the present invention is by right
The bottom crown formed by polysilicon carries out oxidation processes, and using the polysilicon oxide layer that formed after oxidation processes as first medium
Layer, can reduce the thickness of first medium layer, so can obtain compact oxidation layer as capacitor dielectric, such that it is able to improve double
The electrology characteristics such as the unit capacitance values of polycrystalline electric capacity and quality factor.
Those skilled in the art, after considering description and putting into practice invention disclosed herein, will readily occur to its of the present invention
Its embodiment.The application is intended to any modification, purposes or the adaptations of the present invention, these modification, purposes or
Person's adaptations is followed the general principle of the present invention and includes the undocumented common knowledge in the art of the present invention
Or conventional techniques means.Description and embodiments is considered only as exemplary, and true scope and spirit of the invention are by following
Claim is pointed out.
It should be appreciated that the invention is not limited in precision architecture described above and illustrated in the accompanying drawings, and
And various modifications and changes can carried out without departing from the scope.The scope of the present invention is only limited by appended claim.
Claims (9)
1. double polycrystalline capacitance structure manufacture methods integrated with metal-oxide-semiconductor, it is characterised in that described method includes:
Trap is formed at substrate surface；
Field oxide is formed on described trap surface；
Bottom crown and the dielectric layer of double polycrystalline electric capacity is upwards sequentially formed on the surface of selected field oxide；
Gate oxide is formed in the described unlapped region of selected field oxide；
At surface deposition first polysilicon layer of described gate oxide and described dielectric layer, so that on the surface of described gate oxide
The polysilicon formed constitutes the polysilicon gate of metal-oxide-semiconductor with described gate oxide, the polysilicon formed on the surface of described dielectric layer
Constitute the top crown of described pair of polycrystalline electric capacity；
Form the doped source drain region of described metal-oxide-semiconductor.
Method the most according to claim 1, it is characterised in that upwards sequentially form double on the surface of selected field oxide
Before the bottom crown of polycrystalline electric capacity and dielectric layer, described method also includes: in described field oxide unlapped region surface shape
Become shielding protection layer；Before the unlapped region of described field oxide forms gate oxide, described method also includes: remove institute
State shielding protection layer.
Method the most according to claim 1, it is characterised in that the described surface at selected field oxide shape the most successively
The bottom crown and the dielectric layer that become double polycrystalline electric capacity include:
The second polysilicon layer is deposited above described trap；
The surface of described second polysilicon layer is carried out oxidation processes, to form polysilicon oxide layer；
Surface deposition second medium material layer at described polysilicon oxide layer；
Use photoetching and etching technics, upwards sequentially form on the surface of selected field oxide double polycrystalline electric capacity bottom crown,
First medium layer and second dielectric layer, the second polysilicon layer wherein formed on the surface of described selected field oxide constitutes institute
Stating bottom crown, the polysilicon oxide layer that described bottom crown surface is formed constitutes described first medium layer, described first medium layer table
The second medium material layer that face is formed constitutes described second dielectric layer.
Method the most according to claim 1, it is characterised in that the thickness of described top crown is 250～350nm, described under
The thickness of pole plate is 100～150nm.
Method the most according to claim 3, it is characterised in that the thickness of described first medium layer is 4～5nm, described
The thickness of second medium layer is 25～35nm.
6. double polycrystalline capacitance structures integrated with metal-oxide-semiconductor, it is characterised in that include substrate, formed at described substrate surface
There is trap, be formed with field oxide on described trap surface, be upwards sequentially formed with double polycrystalline electric capacity on selected field oxide surface
Bottom crown and dielectric layer, be formed with gate oxide, at described gate oxidation in the described unlapped region of selected field oxide
Layer and the surface of described dielectric layer are formed with the first polysilicon layer, the polysilicon wherein formed on the surface of described gate oxide with
Described gate oxide constitutes the polysilicon gate of metal-oxide-semiconductor, and the polysilicon formed on the surface of described dielectric layer constitutes described pair of polycrystalline
The top crown of electric capacity.
Structure the most according to claim 6, it is characterised in that described dielectric layer includes first medium layer and second medium
Layer, described first medium layer be the polysilicon in described bottom crown is aoxidized after the polysilicon oxide layer that formed, described the
Second medium layer is positioned at described first medium layer surface.
Method the most according to claim 6, it is characterised in that the thickness of described top crown is 250～350nm, described under
The thickness of pole plate is 100～150nm.
Method the most according to claim 7, it is characterised in that the thickness of described first medium layer is 4～5nm, described
The thickness of second medium layer is 25～35nm.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311241A (en) * | 2012-03-16 | 2013-09-18 | 北大方正集团有限公司 | Integrated structure of double polycrystal capacitor and MOS (Metal Oxide Semiconductor) tube and manufacturing method of integrated structure |
| CN103489830A (en) * | 2012-06-08 | 2014-01-01 | 北大方正集团有限公司 | Method for manufacturing integrated circuit |
| CN105261657A (en) * | 2015-10-30 | 2016-01-20 | 中国振华集团云科电子有限公司 | Manufacturing process for MIS thin-film capacitors |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311241A (en) * | 2012-03-16 | 2013-09-18 | 北大方正集团有限公司 | Integrated structure of double polycrystal capacitor and MOS (Metal Oxide Semiconductor) tube and manufacturing method of integrated structure |
| CN103489830A (en) * | 2012-06-08 | 2014-01-01 | 北大方正集团有限公司 | Method for manufacturing integrated circuit |
| CN105261657A (en) * | 2015-10-30 | 2016-01-20 | 中国振华集团云科电子有限公司 | Manufacturing process for MIS thin-film capacitors |
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