CN103633026A - Semiconductor device structure and manufacturing method thereof - Google Patents
Semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN103633026A CN103633026A CN201210303054.6A CN201210303054A CN103633026A CN 103633026 A CN103633026 A CN 103633026A CN 201210303054 A CN201210303054 A CN 201210303054A CN 103633026 A CN103633026 A CN 103633026A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device structure. The method comprises: providing a substrate including an active region and an isolation region, and forming on the substrate a first gate structure disposed above the active region and a second gate structure disposed above the isolation region as a dummy gate structure, wherein gap wall structures are formed at the two sides of the first gate structure and the two sides of the second gate structure, and a gate mask layer is at least formed on the top surface of the second gate structure; forming an internal interconnection material layer above the substrate, the first gate structure and the second gate structure; at least etching and removing all the internal interconnection material layer portion disposed on the first gate structure to form an internal interconnection layer electrically isolated from the first gate structure and the second gate structure; and forming an active/drain region contact hole on the internal interconnection layer. According to the method provided by the invention, the distance between a gate structure and an STI structure can be shortened, the dimension of a semiconductor device can be reduced, the utilization rate of a semiconductor wafer is improved, and the manufacturing cost is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of semiconductor device structure and for making the method for this semiconductor device structure.
Background technology
The device density that continues in integrated circuit to increase impels updating of device performance and cost.In order to be conducive to the further increase of device density, constantly need new technology to reduce the size of semiconductor device.
At present, conventional CMOS (Complementary Metal Oxide Semiconductor) (CMOS) technological process is roughly: STI formation → trap formation → gate oxide (GOX) formation → polysilicon gate formation → clearance wall formation → self-aligned silicide formation → contact hole forms.Yet the spacing between grid structure and shallow-trench isolation (STI) structure is subject to the effects limit such as grid gap wall (spacer), contact hole size and contact hole-active area rule, thereby brought difficulty to the area that further dwindles chip.
Therefore, need a kind of novel semiconductor device structure and preparation method thereof, to solve problems of the prior art.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
For solving above-mentioned problems of the prior art, according to an aspect of the present invention, provide a kind of for making the method for semiconductor device structure, comprise: substrate is provided, described substrate includes source region and isolated area, on described substrate, be formed with and be positioned at the first grid structure above described active area and be positioned at the second grid structure as dummy gate electrode structure above described isolated area, wherein, in described first grid structure both sides and described second grid structure both sides be formed with clearance wall structure, and at least on the top surface of described second grid structure, be formed with grid masking layer, above described substrate, described the first and second grid structures, form intraconnection material layer, at least etching is removed and to be positioned at the structural whole described intraconnection material layers of described first grid, to form the intraconnection layer with described the first and second grid structure electrical isolation, and on described intraconnection layer formation source/drain region contact hole.
Preferably, the step that forms described source/drain region contact hole comprises: above described substrate, form interlayer dielectric layer; And in described interlayer dielectric layer, forming the source/drain region contact hole corresponding with described intraconnection layer, described source/drain region contact hole is connected to via described intraconnection layer the source/drain region that is arranged in described active area.
Preferably, when forming described source/drain region contact hole in described interlayer dielectric layer, in described interlayer dielectric layer, form the gate contact hole with described first grid structural correspondence.
Preferably, described the first and second grid structures include gate dielectric and are positioned at the gate material layers on described gate dielectric.
Preferably, the constituent material of described intraconnection material layer is identical with the constituent material of described gate material layers.
Preferably, the constituent material of described gate material layers is polysilicon.
Preferably, the constituent material of described grid masking layer is at least one in nitride, oxide and nitrogen oxide.
Preferably, described second grid structure is to adopt identical processing step to form with described first grid structure simultaneously.
Preferably, the step that described intraconnection material layer and described grid masking layer are removed in etching comprises: on described intraconnection material layer, form intraconnection layer masking layer; Intraconnection layer masking layer, described intraconnection material layer and described grid masking layer described in etching successively, to form described intraconnection layer; And remove described intraconnection layer masking layer.
Preferably, remove described intraconnection layer masking layer and adopt wet etching process.
Preferably, described isolated area adopts shallow grooved-isolation technique to form.
Preferably, before forming described intraconnection material layer above described substrate, also comprise pre-wash step.
Preferably, between described intraconnection layer and described second grid structure, remain the described grid masking layer of part.
According to another aspect of the present invention, provide a kind of semiconductor device structure, comprising: substrate, described substrate includes source region and isolated area; First grid structure, described first grid structure is positioned at top, described active area; Second grid structure, described second grid structure is positioned at described isolated area top, and is dummy gate electrode structure; With intraconnection layer, described intraconnection layer is electrically connected with being arranged in the source of described active area/drain region, and with described the first and second grid structure electrical isolation.
Preferably, described semiconductor device structure also comprises: clearance wall structure, described clearance wall structure is positioned at the both sides of described the first and second grid structures.
Preferably, described semiconductor device structure also comprises: grid masking layer, described grid masking layer is positioned on a part of top surface of described second grid structure, and wherein, described intraconnection layer by described clearance wall structure with described first grid structure electrical isolation, and by described clearance wall structure and described grid masking layer and with described second grid structure electrical isolation.
Preferably, described semiconductor device structure also comprises: interlayer dielectric layer, described interlayer dielectric layer is formed on described substrate, described the first and second grid structure tops, and in described interlayer dielectric layer, be formed with the source/drain region contact hole corresponding with described source/drain region, described source/drain region contact hole is electrically connected with described source/drain region via described intraconnection layer.
Preferably, in described interlayer dielectric layer, be also formed with the gate contact hole with described first grid structural correspondence.
In sum, the method according to this invention, can reduce for example, spacing between grid structure and isolation structure (, sti structure), thus the size of dwindling semiconductor device, and then improve the utilance of semiconductor wafer and reduce manufacturing cost.In addition, because the polysilicon gate construction of the illusory polysilicon gate construction on STI and active area forms in same processing step, thereby method of the present invention can with existing process compatible, and realize reliably online technology controlling and process.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In accompanying drawing:
Fig. 1 is for making according to an exemplary embodiment of the present the process chart of semiconductor device;
Fig. 2 A-2E is for making according to an exemplary embodiment of the present the schematic cross sectional view of the device that in semiconductor device technology flow process, each step obtains
Fig. 3 is according to the schematic cross sectional view of the semiconductor device structure that is equivalent to Fig. 2 E of prior art making; And
Fig. 4 is according to the part schematic cross sectional view of the semiconductor device structure after having formed SAB layer of the present invention.
Embodiment
Next, in connection with accompanying drawing, the present invention is more intactly described, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment will expose thoroughly and completely, and scope of the present invention is fully passed to those skilled in the art.In accompanying drawing, for the sake of clarity the size in ，Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other elements or when layer, it can directly be positioned at other elements or layer is upper, with it adjacent, connect or be coupled to other elements or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other elements or layer, there is not element or layer between two parties.
Fig. 1 shows the process chart of making according to an exemplary embodiment of the present semiconductor device, and Fig. 2 A-2E shows the schematic cross sectional view of making according to an exemplary embodiment of the present the device that in semiconductor device technology flow process, each step obtains.It should be noted in the discussion above that part of devices structure in semiconductor device can make flow process by CMOS and make, therefore before method of the present invention, among or can provide extra technique afterwards, and wherein some technique is only done simple description at this.Below in conjunction with accompanying drawing, describe exemplary embodiment of the present invention in detail.
First, execution step S101: substrate is provided, described substrate includes source region and isolated area, on described substrate, be formed with and be positioned at the first grid structure above described active area and be positioned at the second grid structure as dummy gate electrode structure above described isolated area, wherein, in described first grid structure both sides and described second grid structure both sides be formed with clearance wall structure, and at least on the top surface of described second grid structure, be formed with grid masking layer.
As shown in Figure 2 A, provide substrate 210.As example, the constituent material of substrate 210 can be not doped monocrystalline silicon, the monocrystalline silicon doped with N-type or p type impurity, polysilicon, germanium silicon or silicon-on-insulator (SOI) etc.Substrate 210 includes source region (not marking in figure) and isolated area 212.Herein, active area refers to the region except isolated area 212 in substrate 210, comprises source/drain region (not shown).Isolated area 212 for example can adopt shallow-trench isolation (STI) technique or selective oxidation silicon (LOCOS) isolation technology and form.Described source/drain region can be for example lightly doped drain (LDD) district, or can also comprise halo (halo) injection region, bag shape (pocket) injection region etc.
In addition, on substrate 210, be formed with the second grid structure as dummy gate electrode structure (being two shown in this example) that is positioned at the first grid structure (shown in this example being) above active area and is positioned at isolation channel 212 tops.As example, first grid structure comprises gate dielectric 222b and is positioned at the gate material layers 224b on gate dielectric 222b.One of them comprises second grid structure gate dielectric 222a and is positioned at the gate material layers 224a on gate dielectric 222a, and wherein another comprises gate dielectric 222c and is positioned at the gate material layers 224c on gate dielectric 222c.Here, what need be explained is, although in the present embodiment, first grid structure is depicted as one and second grid structure and is depicted as two, those skilled in the art will recognize that the number of the first and second grid structures is not limited in this, but can be selected according to actual needs.For example, first grid structure can be also two or more, and second grid structure can be three or more.As example, the constituent material of gate dielectric 222a, 222b and 222c can be a kind of such as in the such high k material of hafnium oxide, hafnium silicate, lanthana, zinc oxide, zinc silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanates, yittrium oxide, aluminium oxide, ferroelectric thin film, lead zinc niobate, lead titanates.The constituent material of gate material layers 224a, 224b and 224c can be for example polysilicon or metal aluminium (Al) for example.As example, in the present embodiment, gate material layers adopts polysilicon to form.Gate dielectric and gate material layers can adopt chemical vapor deposition (CVD) method to form, for example low temperature chemical vapor deposition (LTCVD) method, low-pressure chemical vapor deposition (LPCVD) method, fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), also can adopt physical vapor deposition (PVD) method or sputtering method to form.
In addition; in the first and second grid structure both sides, be formed with respectively clearance wall structure 226a, 226b and 226c; it is injury-free that it is mainly used in when being formed with source region by plasma injection technology grill-protected electrode structure, and effectively control the relative position relation between active area and grid structure.Here, need stress, be optional and nonessential, but in the present embodiment, clearance wall structure is essential at conventional CMOS technique intermediate gap wall construction, for carry out electrical isolation between intraconnection layer (describing after a while) and grid structure.As example, the constituent material of clearance wall structure 226a, 226b and 226c can be nitride, oxide or its combination.Clearance wall structure can be single layer structure or sandwich construction.
In addition, on the top surface of the first and second grid structures, be formed with grid masking layer 228a, 228b and 228c.The constituent material of grid masking layer 228a, 228b and 228c can be at least one in nitride, oxide and nitrogen oxide, and wherein SiN material is the most conventional.Described grid masking layer is mainly used in, when for example being formed grid structure and substrate is carried out to ion implantation technology with formation source/drain region by plasma dry etch process, the gate material layers of its below being protected in conventional CMOS technique.Conventionally, described grid masking layer is removed by wet etching (claiming again wet method to peel off) after grid structure and the formation of source/drain region, to be formed for reducing the self-aligned metal silicate layer of contact resistance on grid structure.But in the present embodiment, grid masking layer 228a, 228b and 228c will be retained, for carry out electrical isolation between intraconnection layer (describing after a while) and grid structure.
The how alternative structure of above-mentioned substrate, isolated area, grid structure, clearance wall structure and grid masking layer etc. and form accordingly process and condition is conventionally known to one of skill in the art, is not described in detail in this.
Then, execution step S102: form intraconnection material layer above described substrate, described the first and second grid structures.
As shown in Figure 2 B, above substrate 210, the first and second grid structures, form intraconnection material layer 232.Preferably, form intraconnection layer masking layer (not shown) on intraconnection material layer 232, its effect is similar to the hard mask layer in common process, will be described this after a while.The constituent material of intraconnection material layer 232 can be for example polysilicon or metal aluminium (Al) for example, and can adopt chemical vapor deposition (CVD) method to form, for example low temperature chemical vapor deposition (LTCVD) method, low-pressure chemical vapor deposition (LPCVD) method, fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), also can adopt physical vapor deposition (PVD) method or sputtering method to form.Preferably, constituent material of intraconnection material layer 232 and forming method thereof can be identical with above-mentioned gate material layers.For example, in the present embodiment, gate material layers 224a, 224b and 224c consist of polysilicon, and intraconnection material layer 232 also can consist of polysilicon.The benefit of doing is like this only need to be recycled and reused for the processing step that forms gate material layers can form intraconnection material layer, and without the new process menu of exploitation in addition, thereby can simplification of flowsheet and reduce manufacturing cost.In addition, while adopting polysilicon as the material of the intraconnection layer being connected with source/drain region (local interconnection layer), above-mentioned intraconnection layer can be considered as to the part in source/drain region, even can become independently source/drain region by techniques such as doping.And, for example, no matter be that (, Al) or polysilicon forms, it can be separately as one deck intraconnection layer with metal as the second grid structure of dummy gate electrode structure.
In addition, preferably, before forming intraconnection material layer 232, carry out prerinse (pre-clean) step.This pre-wash step can adopt reactive or non-reacted prerinse technique.For instance, Reactive Preclean technique is for example for adopting hydrogeneous isoionic plasma process, but not Reactive Preclean technique is for example for adopting the plasma process containing argon plasma.For example, can clean with SC-1 solution (mixed liquor of ammonia solution/hydrogenperoxide steam generator) and SC-2 solution (mixed liquor of hydrochloric acid/hydrogenperoxide steam generator), to remove the foreign matter remaining on substrate surface.
Then, execution step S103: at least etching is removed and to be positioned at the structural whole described intraconnection material layers of described first grid, to form the intraconnection layer with described the first and second grid structure electrical isolation.
As shown in Figure 2 C, for example by plasma dry etch process, to being positioned at intraconnection material layer 232 and the grid masking layer 228b of the first and second grid structure tops, carry out etching, to remove, be positioned at the structural totality interconnection material of first grid layer 232, thereby form intraconnection layer 232a and 232b as shown in the figure.Wherein, intraconnection layer 232a, 232b lay respectively at first grid structure and two second grid structures between one of them.As example, the whole grid masking layer 228b that are positioned at first grid superstructure are removed in etching, in this case, intraconnection layer 232a, 232b can be respectively by be positioned at first grid structure both sides clearance wall and with first grid structure electrical isolation, as shown in Fig. 2 C.
In addition, as example, be positioned at the also etched removal of a part of intraconnection material layer 232 and grid masking layer 228a, the 228c of second grid superstructure, as shown in the figure, but also can retain intraconnection material layer 232 and grid masking layer 228a, the 228c that is positioned at second grid superstructure completely.As shown in the figure, between intraconnection layer 232a and described second grid structure, remain part of grid pole masking layer 228a, and intraconnection layer 232a by this part of grid pole masking layer 228a and clearance wall structure 226a and with second grid structure electrical isolation.Between intraconnection layer 232b and described second grid structure, remain part of grid pole masking layer 228c, and intraconnection layer 232b by this part of grid pole masking layer 228c and clearance wall structure 226c and with another second grid structure electrical isolation.
As example, when having formed intraconnection layer masking layer (not shown) at step S102, first described etching specifically can comprise the following steps:, adopt new lay photoetching mask plate, using photoresist as mask and be aided with in step S102 formed intraconnection layer masking layer as hard mask, successively etching intraconnection material layer 232 and grid masking layer 228a, 228b and 228c; Afterwards, for example by wet etching process (peeling off also referred to as wet method), remove intraconnection layer masking layer.The concrete technology parameter of the dry method adopting in this step or wet etching process and condition are conventionally known to one of skill in the art, no longer describe in detail.But, no matter be dry method or wet etching process, all need those skilled in the art according to the actual constituent material of selecting, existing technological parameter and condition are selected and adjusted, by this to obtain optimised process result.
Then, execution step S104: formation source/drain region contact hole on described intraconnection layer.
After forming intraconnection layer 232a and 232b, can continue to carry out conventional interconnection process, such as interlayer dielectric layer deposition, contact etch and contact plunger formation etc.Particularly, as shown in Figure 2 D, above substrate 210, form interlayer dielectric layer 240.Then, as shown in Figure 2 E, in interlayer dielectric layer 240, form the source/drain region contact hole 242,244 corresponding with intraconnection layer 232a, 232b.Wherein, described source/drain region contact hole 242,244 is connected to via intraconnection layer 232a, 232b the source/drain region (not shown) that is arranged in above-mentioned active area respectively.And, when being in interlayer dielectric layer 240 formation source/drain region contact hole 242,244, in described interlayer dielectric layer, also form the gate contact hole (not shown) with first grid structural correspondence.Although gate contact hole is only depicted as and is formed in first grid structure in figure, it will be understood by those skilled in the art that also and can for example in the second grid structure as dummy gate electrode structure, form gate contact hole at other grid structures.Here, need be explained, because second grid structure is dummy gate electrode structure, therefore, the gate contact hole of the side of being located thereon is actual not as gate contact hole, but as the general contact hole for interconnecting.
By the final semiconductor device structure obtaining as shown in Figure 2 E of method step as above.As shown in the figure, described semiconductor device structure comprises substrate (210), first grid structure (222b and 224b), second grid structure (222a and 242a; 222c and 242c) and intraconnection layer (232a, 232b).Wherein, described substrate includes source region (not marking) and isolated area (212).Described first grid structure is positioned at top, described active area.Described second grid structure is positioned at described isolated area top, and is dummy gate electrode structure.Described intraconnection layer is electrically connected with being arranged in the source of described active area/drain region, and with described the first and second grid structure electrical isolation.As example, as shown in the figure, intraconnection layer 232a is between described first grid structure and a described second grid structure, and intraconnection layer 232b is in described first grid structure and described in another between second grid structure.
In addition, the semiconductor device structure shown in Fig. 2 E can also comprise clearance wall structure (226a, 226b, 226c) and grid masking layer (228a, 228b, 228c).Described clearance wall structure is formed on the both sides of described the first and second grid structures, described grid masking layer is formed on a part of top surface of described second grid structure, to guarantee all electrical isolation of described intraconnection layer and described first grid structure and described second grid structure.Because contact hole can partly be formed in described second grid structure, can partly be formed in isolated area simultaneously, therefore can shorten the spacing between first grid structure and isolated area.Wherein, described intraconnection layer by described clearance wall structure with described first grid structure electrical isolation, and by described clearance wall structure and described grid masking layer and with described second grid structure electrical isolation.For example, intraconnection layer 232b by clearance wall structure 226c and grid masking layer 228c and with second grid structure (right side in Fig. 2 E) electrical isolation.
In addition, the semiconductor device structure shown in Fig. 2 E can also comprise interlayer dielectric layer (240).Described interlayer dielectric layer is formed on described substrate, described the first and second grid structure tops, and in described interlayer dielectric layer, is formed with the source/drain region contact hole (242,244) corresponding with described source/drain region.Wherein, source/drain region contact hole 242,244 is electrically connected with described source/drain region via intraconnection layer 232a, 232b respectively.In addition, when adopting polycrystalline silicon material as the material of the intraconnection layer being connected with source/drain region, above-mentioned intraconnection layer can be considered as to the part in source/drain region, even can become independently source/drain region by operations such as doping.
Here; those skilled in the art will recognize that; the manufacture method of the semiconductor device structure shown in Fig. 2 E is not limited to above-mentioned step S101～S104; but can also adopt additive method, and adopt the semiconductor device structure shown in Fig. 2 E that additive method forms thereby also will fall within protection scope of the present invention.
Figure 3 shows that the schematic cross sectional view of the semiconductor device structure that is equivalent to Fig. 2 E of making according to prior art.And spacing (the four-headed arrow X in figure between the first grid structure shown in Fig. 3 in semiconductor device structure and the second grid structure in isolated area 312
2shown in) compare, the spacing in Fig. 2 E between first grid structure and the second grid structure in isolated area 212 (in figure shown in four-headed arrow X1) is all reduced.This is mainly because by the intraconnection layer being electrically connected with source/drain region with grid structure electrical isolation is provided, contact hole can be formed on to isolated area top, thereby make the spacing between grid structure and isolated area limited by the factors such as grid gap wall, contact hole-active area rule.
As mentioned above, intraconnection layer and the electrical isolation between the second grid structure above isolated area mainly rely on grid masking layer and clearance wall structure.In addition, it should be noted that, in Practical manufacturing process, the grid masking layer 428a that etching forms and the marginal portion exposed externally (as shown in Figure 4) of intraconnection layer 432a, especially when adopting wet etching process to come etching to remove grid masking layer and intraconnection material layer a part of, the edge of formed grid masking layer 428a may be with respect to the edge of intraconnection layer 432a and inside recessed sub-fraction (not explicitly shown in FIG.).But in outside, above-mentioned marginal portion, will form self-aligned metal silicate barrier layer (SAB) 450 afterwards, thereby can guarantee that second grid structure and intraconnection layer 432a isolate completely.Other effects of SAB and forming method thereof are known to those skilled in the art, no longer describe in detail.
In sum, the method according to this invention, can reduce for example, spacing between grid structure and isolated area (, sti structure), thereby dwindles the chip size of semiconductor device, and then improves the utilance of semiconductor wafer and reduce manufacturing cost.In addition, because the polysilicon gate construction of the illusory polysilicon gate construction on STI and active area forms in same processing step, thereby method of the present invention can with existing process compatible, simple and realize reliably online technology controlling and process.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition, it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (20)
1. for making a method for semiconductor device structure, comprising:
Substrate is provided, described substrate includes source region and isolated area, on described substrate, be formed with and be positioned at the first grid structure above described active area and be positioned at the second grid structure as dummy gate electrode structure above described isolated area, wherein, in described first grid structure both sides and described second grid structure both sides be formed with clearance wall structure, and at least on the top surface of described second grid structure, be formed with grid masking layer;
Above described substrate, described the first and second grid structures, form intraconnection material layer;
At least etching is removed and to be positioned at the structural whole described intraconnection material layers of described first grid, to form the intraconnection layer with described the first and second grid structure electrical isolation; And
Formation source/drain region contact hole on described intraconnection layer.
2. method according to claim 1, wherein, the step that forms described source/drain region contact hole comprises:
Above described substrate, form interlayer dielectric layer; And
In described interlayer dielectric layer, form the source/drain region contact hole corresponding with described intraconnection layer, described source/drain region contact hole is connected to via described intraconnection layer the source/drain region that is arranged in described active area.
3. method according to claim 2 wherein, when forming described source/drain region contact hole in described interlayer dielectric layer, forms the gate contact hole with described first grid structural correspondence in described interlayer dielectric layer.
4. method according to claim 1, wherein, described the first and second grid structures include gate dielectric and are positioned at the gate material layers on described gate dielectric.
5. method according to claim 4, wherein, the constituent material of described intraconnection material layer is identical with the constituent material of described gate material layers.
6. according to the method described in claim 4 or 5, wherein, the constituent material of described gate material layers is polysilicon.
7. method according to claim 1, wherein, the constituent material of described grid masking layer is at least one in nitride, oxide and nitrogen oxide.
8. method according to claim 1, wherein, described second grid structure is to adopt identical processing step to form with described first grid structure simultaneously.
9. method according to claim 1, wherein, the step that described intraconnection material layer and described grid masking layer are removed in etching comprises:
On described intraconnection material layer, form intraconnection layer masking layer;
Intraconnection layer masking layer, described intraconnection material layer and described grid masking layer described in etching successively, to form described intraconnection layer; And
Remove described intraconnection layer masking layer.
10. method according to claim 9, wherein, removes described intraconnection layer masking layer and adopts wet etching process.
11. methods according to claim 1, wherein, described isolated area adopts shallow grooved-isolation technique to form.
12. methods according to claim 1 wherein, also comprised pre-wash step before forming described intraconnection material layer above described substrate.
13. methods according to claim 1, wherein, remain the described grid masking layer of part between described intraconnection layer and described second grid structure.
14. methods according to claim 1, wherein, described second grid structure is as another intraconnection layer.
15. 1 kinds of semiconductor device structures, comprising:
Substrate, described substrate includes source region and isolated area;
First grid structure, described first grid structure is positioned at top, described active area;
Second grid structure, described second grid structure is positioned at described isolated area top, and is dummy gate electrode structure; With
Intraconnection layer, described intraconnection layer is electrically connected with being arranged in the source of described active area/drain region, and with described the first and second grid structure electrical isolation.
16. semiconductor device structures according to claim 15, also comprise:
Clearance wall structure, described clearance wall structure is positioned at the both sides of described the first and second grid structures.
17. semiconductor device structures according to claim 16, also comprise:
Grid masking layer, described grid masking layer is positioned on a part of top surface of described second grid structure, and
Wherein, described intraconnection layer by described clearance wall structure with described first grid structure electrical isolation, and by described clearance wall structure and described grid masking layer and with described second grid structure electrical isolation.
18. semiconductor device structures according to claim 15, also comprise:
Interlayer dielectric layer, described interlayer dielectric layer is formed on described substrate, described the first and second grid structure tops, and in described interlayer dielectric layer, be formed with the source/drain region contact hole corresponding with described source/drain region, described source/drain region contact hole is electrically connected with described source/drain region via described intraconnection layer.
19. semiconductor device structures according to claim 18 wherein, are also formed with the gate contact hole with described first grid structural correspondence in described interlayer dielectric layer.
20. semiconductor device structures according to claim 15, wherein, described second grid structure is as another intraconnection layer.
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| CN107464782A (en) * | 2016-06-03 | 2017-12-12 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN108807268A (en) * | 2017-04-26 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109872969A (en) * | 2017-12-01 | 2019-06-11 | 中芯国际集成电路制造(上海)有限公司 | Method, semi-conductor device manufacturing method and semiconductor devices |
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