CN101197290A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
- Publication number
- CN101197290A CN101197290A CNA2006101191707A CN200610119170A CN101197290A CN 101197290 A CN101197290 A CN 101197290A CN A2006101191707 A CNA2006101191707 A CN A2006101191707A CN 200610119170 A CN200610119170 A CN 200610119170A CN 101197290 A CN101197290 A CN 101197290A
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- grid
- substrate
- sidewall spacer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a method of manufacturing semiconductor devices which comprises the following steps of: providing a semiconductor substrate on the surface of which a grid is formed; forming a sidewall spacer on the two sides of the grid; forming a source and a drain between the substrates of the two sides of the sidewall spacer; forming a first dielectric layer on the surfaces of the substrate, the sidewall spacer and the grid; forming a second dielectric layer on the first layer; forming metal silicide on the surfaces of the grid, source and the drain; stripping the second dielectric layer with dry etching; and stripping the first dielectric layer with wet etching. The first dielectric layer is a rich silicon oxide layer and the second dielectric layer is silicon nitride, silicon oxynitride or their combination. The invention can avoid not only the damage of the substrate active region but also the dent of the lower part of the sidewall spacer effectively during the process of stripping the self-aligned barrier layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the manufacture method of particularly a kind of metal-oxide semiconductor (MOS) (MOS) device.
Background technology
Metal silicide plays important effect in the VLSI/ULSI device technology.Self-aligned silicide (Salicide) technology has become one of key manufacturing technology that forms metal silicide in the recent period in ultrahigh speed CMOS logic large scale integrated circuit.It provides many benefits for the manufacturing of programmable logic device.This technology has reduced the film resistor of source/drain electrode and gate electrode simultaneously, has reduced contact resistance, and has shortened the RC delay relevant with grid.In addition, it also allows to improve the device integrated level by increasing circuit package density.In self-aligned technology, on source, the drain region of the MOSFET that constitutes by the impurity diffusion layer that is formed on the Semiconductor substrate and the grid that constitutes by polysilicon, form metal and semiconductor for example the reaction product of silicon (Si) be metal silicide.Metal silicide can be used to provide the contact-making surface between metal wire and substrate contact region territory, for example the connection between source electrode on polysilicon gate, the silicon substrate and the drain electrode.Adopt metal silicide can access good low resistance contact, reduce the contact hole of upper layer interconnects structure and the contact resistance of each utmost point of transistor.
Need be when adopting self-registered technology on the surface of the sidewall spacer (offsetspacer) in substrate surface, the grid outside and the top portions of gates surface form the autoregistration barrier layer (Salicide Barrier, SAB).Sidewall spacer is to be included in silica that gate side forms and the ON structure of the silicon nitride that forms at this silicon oxide surface.Application number is that 200410076817.3 Chinese patent application has been introduced a kind of sidewall spacer structure of MOS device and the formation method of metal silicide.Fig. 1 to Fig. 6 forms the generalized section of metal silicide for the MOS device.As shown in Figure 1, have grid oxic horizon 101 and grid 106, the gate surface damage that when gate side is formed with the very thin oxide layer of one deck 105 with reparation etching grid, causes at substrate 100.Form the sidewall spacer of forming by silicon nitride 105, silica 103 and another layer silicon nitride 102 at oxide layer 105 outer surfaces.Wherein the material of silicon oxide layer 103 for deposit forms under lower temperature low temperature oxide (Low Temperature Oxide, LTO).
Then, as shown in Figure 2, deposit forms autoregistration barrier layer 107, and this layer covers substrate 100 surfaces, sidewall spacer surface and top portions of gates surface.By photoetching, the described autoregistration of etching technics patterning barrier layer 107, form the opening 110,120 and 130 of corresponding grid, source electrode and drain metal silicide position, as shown in Figure 3.Subsequently, as shown in Figure 4, plated metal and process thermal annealing form grid, source electrode and drain metal silicide 111,121 and 131 in opening.
Next as shown in Figure 5, behind the formation metal silicide, need to remove autoregistration barrier layer 107.Usually the thickness on autoregistration barrier layer 107 is 350
About, at first adopt dry etch process to etch away 250 when removing autoregistration barrier layer 107
About, remaining 100
About autoregistration barrier layer 107 utilizing hydrofluoric acid HF to carry out wet-cleaned.But,, make etch rate descend because in high-end technology, particularly at the following process node of 90nm, dry etching easily produces little loading effect (micro loading effect).If strengthen etching intensity, then very easily destroy the substrate active area (Active Area, AA); If do not strengthen etching intensity, then remaining autoregistration barrier layer 107 can be blocked up, certainly will need the longer wet-cleaned time.Because the material on autoregistration barrier layer 107 is the higher silicon rich oxide of density (silicon Rich Oxide, SRO), and the material of the silicon oxide layer 103 in the sidewall spacer is the relatively more loose LTO of quality, when utilizing the hydrofluoric acid corrosion, hydrofluoric acid is lower to the corrosion selectivity of above-mentioned two kinds of material LTO and SRO, is about 1: 5.Therefore when utilizing hydrofluoric acid to corrode autoregistration barrier layer 107 for a long time, very easily silicon oxide layer 103 is caused erosion, cause appearance depression 200 and 200 ' as shown in Figure 6 below sidewall spacer, influence the electric property of device.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of semiconductor device, in the process of removing the autoregistration barrier layer, not only can avoid destroying the substrate active area, and can prevent the generation of sidewall spacer below depression.
For achieving the above object the manufacture method of semiconductor device provided by the invention: comprise
Semi-conductive substrate is provided, forms grid at described substrate surface;
Form sidewall spacer in described grid both sides;
In the substrate of described sidewall spacer both sides, form source electrode and drain electrode;
Form first dielectric layer in described substrate, sidewall spacer and gate surface;
Form second dielectric layer on described first dielectric layer surface;
Form metal silicide in described grid, source electrode and drain surface;
Dry etching is removed described second dielectric layer;
Wet method is removed described first dielectric layer.
Described first dielectric layer is the silicon rich oxide layer, adopts chemical vapor deposition or thermal oxidation technology to form.
Described second dielectric layer is silicon nitride, silicon oxynitride or its combination.
The thickness of described second dielectric layer is 300-350
The thickness of described first dielectric layer is 50-70
The etching agent of described dry etching is fluoroform CHF
3
Adopt hydrofluoric acid to remove described first dielectric layer.
The present invention is corresponding to provide a kind of autoregistration barrier layer structure, comprising:
Oxide layer in described substrate, sidewall spacer and gate surface formation;
The nitration case that forms on described oxide layer surface.
Described oxide layer is the silicon rich oxide layer.
Described nitration case is silicon nitride, silicon oxynitride or its combination.
The thickness of described nitration case is 300-350
Described thickness of oxide layer is 50-70
Compared with prior art, the present invention has the following advantages:
Method, semi-conductor device manufacturing method of the present invention is the laminated construction of being made up of silicon rich oxide and silicon nitride (SRO+SIN) with the autoregistration barrier layer by existing individual layer silicon rich oxide (SRO) architecture advances, wherein, and thicker (about 300～350
) the SIN layer cover thin (about 50
) the SRO layer.Adopt lamination autoregistration barrier layer structure of the present invention, when dry etching is removed the autoregistration barrier layer, (the CHF for example because etching agent
3) SIN layer and SRO layer are had very high etching selection ratio (greater than 20), therefore the etching process can stop at the SRO laminar surface substantially after etching is finished thicker SIN layer, can not continue downward etching, thereby avoid the destruction of etching process to substrate AA.This high etching selection ratio by material decision itself has reduced the technology controlling and process requirement to etching process, thereby has simplified technology.In addition, when adopting HF to remove remaining SRO layer,, only have an appointment 50～70 because the SRO layer is thinner
So only need the very short time just the SRO layer can be removed, thereby avoided effectively because of the long-time depression that below sidewall spacer, produces of corroding.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing in proportion, focus on illustrating purport of the present invention.In the accompanying drawings, for cheer and bright, amplified the thickness in layer and zone.
Fig. 1 to Fig. 6 forms the device profile schematic diagram of metal silicide process for existing MOS device;
Fig. 7 to Figure 11 is the device profile schematic diagram of explanation according to the MOS device metal silicide forming process of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Semiconductor device provided by the invention and manufacture method thereof are specially adapted to characteristic size in 65nm and following semiconductor device and manufacturing thereof.Described semiconductor device is not only MOS transistor, can also be PMOS transistor and nmos pass transistor among the CMOS (complementary mos device).
Fig. 7 to Figure 11 is that the MOS device forms the device profile schematic diagram of metal silicide process according to the preferred embodiment of the invention, and described schematic diagram is an example, and it should excessively not limit the scope of protection of the invention at this.At first as shown in Figure 7, method, semi-conductor device manufacturing method of the present invention forms grid structure on Semiconductor substrate 100 surfaces, and grid structure is included in grid oxic horizon 101 and the grid 106 that Semiconductor substrate 100 surfaces form.Substrate 100 can be the silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, also can be silicon-on-insulator (SOI).The material that perhaps can also comprise other, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Though in these several examples of having described the material that can form substrate 100, any material that can be used as Semiconductor substrate all falls into the spirit and scope of the present invention.
Above-mentioned grid oxic horizon 101 can be silica (SiO2) or silicon oxynitride (SiNO).At the following process node of 65nm, the material of grid oxic horizon 110 is preferably high dielectric constant material, for example hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.Though in this a few examples of having described the material that can be used for forming grid oxic horizon 101, this layer can be formed by other material that reduces grid leakage current.The growing method of grid oxic horizon 101 can be any conventional vacuum coating technology, such as ald (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, be preferably ALD technology.In such technology, can form smooth atom interface between substrate 100 and the grid oxic horizon 101, can form the gate dielectric layer of ideal thickness.
The material of grid 106 is preferably polysilicon, can utilize PECVD or high-density plasma chemical vapor deposition (HDP-CVD) technology to deposit at substrate surface, polysilicon layer surface in deposition also need form a hard mask layer, for example silicon nitride adopts the pecvd process deposit to form above-mentioned silicon nitride usually.Be coated with photoresist and patterning photoresist position then, utilize photoresist and silicon nitride to form grid 106 subsequently as the described polysilicon layer of mask etching with the definition grid.Will remove remaining photoresist and hard mask silicon nitride in addition, cineration technics is adopted in the removal of photoresist, and hard mask silicon nitride adopts the phosphoric acid wet method to remove.
When forming grid 106, etch polysilicon can produce to a certain degree damage at grid 106 sidewalls, and need be for repairing this damage at grid 106 sidewall surfaces growth one deck silica 105.Usually utilize thermal oxidation or ISSG (generation of original position steam) to form said silicon oxide 105; Again in the thick silicon nitride layer 104 of above-mentioned silica 105 surface deposition one decks 7～10nm as the excessive layer between silica 105 and the sidewall spacer.Then, form the sidewall spacers of ON (silica-silicon nitride) structure in the both sides of described grid 150.In the present embodiment, sidewall spacers comprises cryogenic oxidation silicon (LTO) layer 103 and silicon nitride layer 102.The formation of sidewall spacers at first utilizes CVD process deposits LTO layer 103 at described substrate 100 and grid 106 surfaces; Utilize high-density plasma chemical vapor deposition method (PECVD) at described LTO surface deposition silicon nitride layer 102 subsequently; Adopt described oxide layer of plasma etching industrial etching and silicon nitride layer to form sidewall spacer.In ensuing processing step,, form source electrode and drain electrode (, not shown) for for simplicity to the substrate implanting impurity ion that is arranged in the sidewall spacers both sides by ion implantation technology.
Next, form dielectric layer 107 on substrate 100, grid 106 and sidewall spacer surface.This dielectric layer 107 covers substrate 100, grid 106, silicon oxide layer 105, silicon nitride layer 104 and comprises silicon oxide layer 103 and the sidewall spacer surface of silicon nitride layer 102.The material of dielectric layer 107 is preferably silicon rich oxide (SRO), adopts chemical vapor deposition or thermal oxidation technology to form, and thickness is 50～70
Subsequently, utilize pecvd process to deposit another dielectric layer 108 on dielectric layer 107 surfaces, this dielectric layer 108 is silicon nitride, silicon oxynitride or its combination, is preferably silicon nitride, and thickness is 300-350
In embodiments of the present invention, above-mentioned SRO dielectric layer 107 and silicon nitride layer 108 have constituted the autoregistration barrier layer jointly.In ensuing processing step, at autoregistration barrier layer surface coating photoresist and by described photoresist layers of photoetching process patterning such as development, photographic fixing.Then, as the described autoregistration of mask etching barrier layer, on the autoregistration barrier layer, form opening 110,120 and 130, as shown in Figure 8 with the photoresist of patterning.Opening 110,120 and 130 is the position of corresponding grid, source electrode and drain electrode respectively.
Then, in autoregistration barrier layer 107 and 108 and grid 150 surfaces, utilize the method plated metal nickel or the cobalt of physical sputtering, those skilled in the art can control the deposit of described metal according to common process.Because the effect of mask is played on the autoregistration barrier layer, therefore described metal can be deposited in the opening 170,180 and 190 and with grid, source electrode and drain surface and contact, and remaining metal only is covered in the surface on autoregistration barrier layer.Carry out thermal anneal process subsequently, preferred rapid thermal annealing (RTP) technology, the typical anneal temperature is between 500～550 ℃, so that the silicon generation silicification reaction of metal that contacts with grid, source electrode and drain surface and below, form the silicide 111,121 and 131 of nickel or cobalt, as shown in Figure 9.Next etch away remaining metal and substrate surface is cleaned.
Then, remove above-mentioned autoregistration barrier layer.The present invention with SRO layer 107 and silicon nitride layer 108 jointly as the autoregistration barrier layer.In the process of removing, at first with dry etching, the thicker silicon nitride layer 108 of the described thickness of plasma etching or reactive ion etching (RIE) technology etching for example.The embodiment of the invention adopts fluoroform CHF
3As etching agent, CHF
3 Silicon nitride layer 108 and SRO layer 107 had very high etching selection ratio (20～25), therefore the etching process can stop at SRO layer 107 surface substantially after the intact SIN layer 108 of etching, can not continue downward etching, as shown in figure 10, thereby avoid the destruction of etching process substrate AA.
After removing silicon nitride layer 108, only remained SRO layer 107, the embodiment of the invention utilizes wet-cleaned to remove described SRO layer 107, and corrosive agent adopts hydrofluoric acid HF, because these SRO layer 107 thinner thicknesses have only 50～70
Therefore the etching time of hydrofluoric acid HF is shortened greatly, thereby avoid effectively because of the long-time depression that below sidewall spacer, produces of corroding, as shown in figure 11.
The present invention is improved to the laminated construction of being made up of silicon rich oxide and silicon nitride (SRO+SIN) with the barrier layer structure of individual layer autoregistration in the past, and it is included in the silicon rich oxide layer 107 of described substrate 100, sidewall spacer and grid 106 surface formation and the silicon nitride layers 108 that form on described oxide layer 107 surfaces.The thickness of wherein said silicon nitride layer 108 is 300-350
The thickness of described silicon rich oxide layer 107 is 50-70
In the process of removing the autoregistration barrier layer, utilize the described silicon nitride layer 108 of fluoroform CHF3 etching, utilize hydrofluoric acid HF wet-cleaned silicon rich oxide layer 107, not only can avoid destroying the substrate active area, and can prevent the generation of sidewall spacer below depression.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (12)
1. the manufacture method of a semiconductor device: comprise
Semi-conductive substrate is provided, forms grid at described substrate surface;
Form sidewall spacer in described grid both sides;
In the substrate of described sidewall spacer both sides, form source electrode and drain electrode;
Form first dielectric layer in described substrate, sidewall spacer and gate surface;
Form second dielectric layer on described first dielectric layer surface;
Form metal silicide in described grid, source electrode and drain surface;
Dry etching is removed described second dielectric layer;
Wet method is removed described first dielectric layer.
2. the method for claim 1, it is characterized in that: described first dielectric layer is the silicon rich oxide layer, adopts chemical vapor deposition or thermal oxidation technology to form.
3. the method for claim 1, it is characterized in that: described second dielectric layer is silicon nitride, silicon oxynitride or its combination.
4. method as claimed in claim 3 is characterized in that: the thickness of described second dielectric layer is 300-350
5. method as claimed in claim 2 is characterized in that: the thickness of described first dielectric layer is 50-70
6. the method for claim 1, it is characterized in that: the etching agent of described dry etching is fluoroform CHF
3
7. the method for claim 1 is characterized in that: adopt hydrofluoric acid to remove described first dielectric layer.
8. autoregistration barrier layer structure comprises:
Oxide layer in Semiconductor substrate, sidewall spacer and gate surface formation;
The nitration case that forms on described oxide layer surface.
9. autoregistration barrier layer structure as claimed in claim 8 is characterized in that: described oxide layer is the silicon rich oxide layer.
10. autoregistration barrier layer structure as claimed in claim 8 is characterized in that: described nitration case is silicon nitride, silicon oxynitride or its combination.
11. autoregistration barrier layer structure as claimed in claim 10 is characterized in that: the thickness of described nitration case is 300-350
12. autoregistration as claimed in claim 9 barrier layer is characterized in that: described thickness of oxide layer is 50-70
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101191707A CN101197290A (en) | 2006-12-05 | 2006-12-05 | Manufacturing method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101191707A CN101197290A (en) | 2006-12-05 | 2006-12-05 | Manufacturing method for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101197290A true CN101197290A (en) | 2008-06-11 |
Family
ID=39547588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101191707A Pending CN101197290A (en) | 2006-12-05 | 2006-12-05 | Manufacturing method for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101197290A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270572A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Forming methods of side wall and MOS (metal oxide semiconductor) transistor |
| CN102270574A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming flank wall |
| CN102403197A (en) * | 2010-09-08 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Method for activating doping atoms |
| CN102446970A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Semiconductor device for preventing formation of acid tank cleaning cavity and preparation method thereof |
| CN102543735A (en) * | 2010-12-10 | 2012-07-04 | 武汉新芯集成电路制造有限公司 | Forming method for salicide block layer |
| CN102637604A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Side wall and method for forming side wall and semiconductor |
| CN103187277A (en) * | 2011-12-28 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN107123670A (en) * | 2016-02-25 | 2017-09-01 | 台湾积体电路制造股份有限公司 | Fin formula field effect transistor and forming method thereof |
| CN107403754A (en) * | 2016-05-18 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN108235203A (en) * | 2017-12-11 | 2018-06-29 | 钰太芯微电子科技（上海）有限公司 | A kind of method and microphone apparatus of adaptive tracing bias voltage |
| CN111244029A (en) * | 2020-01-17 | 2020-06-05 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN113451344A (en) * | 2021-07-01 | 2021-09-28 | 武汉新芯集成电路制造有限公司 | Backside illuminated image sensor and method of manufacturing the same |
| CN115295615A (en) * | 2022-10-08 | 2022-11-04 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116504717A (en) * | 2023-06-29 | 2023-07-28 | 合肥晶合集成电路股份有限公司 | Method for preparing metal silicide |
-
2006
- 2006-12-05 CN CNA2006101191707A patent/CN101197290A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270574A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming flank wall |
| CN102270572A (en) * | 2010-06-04 | 2011-12-07 | 中芯国际集成电路制造(上海)有限公司 | Forming methods of side wall and MOS (metal oxide semiconductor) transistor |
| CN102403197A (en) * | 2010-09-08 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Method for activating doping atoms |
| CN102403197B (en) * | 2010-09-08 | 2013-11-20 | 中芯国际集成电路制造(上海)有限公司 | Method for activating dopant atoms |
| CN102543735A (en) * | 2010-12-10 | 2012-07-04 | 武汉新芯集成电路制造有限公司 | Forming method for salicide block layer |
| CN102543735B (en) * | 2010-12-10 | 2015-03-18 | 武汉新芯集成电路制造有限公司 | Forming method for salicide block layer |
| CN102446970A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Semiconductor device for preventing formation of acid tank cleaning cavity and preparation method thereof |
| CN102446970B (en) * | 2011-08-29 | 2014-05-28 | 上海华力微电子有限公司 | Semiconductor device capable of preventing cavitation from forming during acid tank washing and manufacturing method of semiconductor device |
| CN103187277B (en) * | 2011-12-28 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor device |
| CN103187277A (en) * | 2011-12-28 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN102637604A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Side wall and method for forming side wall and semiconductor |
| CN102637604B (en) * | 2012-04-25 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | Side wall, formation side wall, the method for semiconductor devices |
| CN107123670A (en) * | 2016-02-25 | 2017-09-01 | 台湾积体电路制造股份有限公司 | Fin formula field effect transistor and forming method thereof |
| CN107403754A (en) * | 2016-05-18 | 2017-11-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN107403754B (en) * | 2016-05-18 | 2020-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN108235203A (en) * | 2017-12-11 | 2018-06-29 | 钰太芯微电子科技（上海）有限公司 | A kind of method and microphone apparatus of adaptive tracing bias voltage |
| CN111244029A (en) * | 2020-01-17 | 2020-06-05 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN113451344A (en) * | 2021-07-01 | 2021-09-28 | 武汉新芯集成电路制造有限公司 | Backside illuminated image sensor and method of manufacturing the same |
| CN115295615A (en) * | 2022-10-08 | 2022-11-04 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116504717A (en) * | 2023-06-29 | 2023-07-28 | 合肥晶合集成电路股份有限公司 | Method for preparing metal silicide |
| CN116504717B (en) * | 2023-06-29 | 2023-09-12 | 合肥晶合集成电路股份有限公司 | Method for preparing metal silicide |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101197290A (en) | Manufacturing method for semiconductor device | |
| US6706581B1 (en) | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices | |
| CN100590815C (en) | Method for manufacturing semiconductor device | |
| JP4767946B2 (en) | Complementary metal oxide semiconductor integrated circuit with NMOS and PMOS transistors using different gate dielectrics | |
| US7534671B2 (en) | Method for integrally forming an electrical fuse device and a MOS transistor | |
| CN100517618C (en) | Semiconductor device and its making method | |
| US7323419B2 (en) | Method of fabricating semiconductor device | |
| CN101123271A (en) | Semiconductor device and its making method | |
| JP4587774B2 (en) | Method for forming a semiconductor device | |
| CN102956459B (en) | Semiconductor device and manufacture method thereof | |
| US20090001477A1 (en) | Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures | |
| CN106298676B (en) | Method for manufacturing semiconductor element | |
| CN101207068A (en) | Method for manufacturing of semiconductor device metal connecting hole and semiconductor device | |
| US11735476B2 (en) | Semiconductor structure and fabrication method thereof | |
| JP2008021935A (en) | Electronic device and manufacturing method thereof | |
| US6939770B1 (en) | Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process | |
| US6677255B1 (en) | Method for removing fences without reduction of ONO film thickness | |
| GB2591472A (en) | Method of forming asymmetric differential spacers for optimized MOSFET performance and optimized mosfet and SONOS co-integration | |
| KR20040007949A (en) | Method of manufacture semiconductor device | |
| US20090085131A1 (en) | Semiconductor device and manufacturing method thereof | |
| KR20050023650A (en) | Method for fabricating semiconductor device having salicide | |
| KR100580581B1 (en) | Method for manufacturing a semiconductor device | |
| JP2008140977A (en) | Method for manufacturing semiconductor device | |
| JP2004273559A (en) | Semiconductor device and its manufacturing method | |
| JP2000150666A (en) | Semiconductor device and fabrication thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20080611 |