JP2004273559A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a duplicate sidewall structured semiconductor device which prevents surely erosion and deformation due to consecutive hydrofluoric acid cleaning treatment. <P>SOLUTION: The semiconductor device is provided with a semiconductor substrate, a gate electrode located on the substrate through a gate insulating film, and a duplicate sidewall covering a sidewall of the gate electrode. The duplicate sidewall is constituted of a first sidewall which is located on the sidewall of the gate electrode and lower than the height of the gate electrode, and a second sidewall of hydrofluoric acid-proof nature which covers continuously the whole surface of the first sidewall and an upper sidewall of the gate electrode protruding from the first sidewall. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOS semiconductor device having a double sidewall structure and a method of manufacturing the same.
[0002]
[Prior art]
In the process of manufacturing a fine CMOS device, a gate electrode is generally formed, a sidewall is formed by an insulating film on a side wall of the gate electrode, and then silicide is formed in source / drain regions to reduce contact resistance. Prior to the formation of silicide, a pretreatment for cleaning and removing a natural oxide film and a thermal oxide film existing on the source / drain is performed.
[0003]
As a material of the sidewall, a silicon oxide film (SiO ₂ ) And a silicon nitride film (SiN) are used, but the silicon oxide film is weak to a wet process using a hydrofluoric acid (HF) -based cleaning solution and is damaged in the cleaning process. On the other hand, a silicon nitride film is excellent in hydrofluoric acid resistance, but has strong internal stress, and if formed directly in an active region on a silicon substrate, it affects the reliability of device operation. In addition, hydrogen (H) present in the silicon nitride film affects the gate oxide film, which also causes a reduction in device operation reliability. In order for the sidewall to function as an etching stopper without affecting the reliability of the device, a configuration combining a silicon oxide film and a silicon nitride film is required.
[0004]
A method has also been proposed in which after forming a sidewall on the side wall of a gate electrode, an etching stopper film is separately formed on the entire surface, and the etching stopper film on the source / drain regions is dry-etched and removed in a later step (for example, Patent Document 1). 1 and 2). However, as the miniaturization progresses, the problem of misalignment becomes remarkable. Therefore, it is preferable that the etching stopper layer is also formed by a self-alignment process. Therefore, a double sidewall structure in which a silicon oxide film is arranged as a base of a silicon nitride film has been proposed.
[0005]
FIG. 1 is a diagram for explaining a conventional double sidewall structure and its problems. As shown in FIG. 1A, a gate electrode 103 is formed on a silicon substrate 101 with a gate oxide film 102 interposed therebetween. The silicon oxide film 105 is located on the side wall of the gate electrode 103 and a region of the silicon substrate 101 adjacent to the gate electrode 103, and the silicon nitride film 106 is located on the silicon oxide film 105. The silicon nitride film 106 extends from the upper end of the gate electrode 103 toward the silicon oxide film 105 on the silicon substrate 101 in a taper shape. The silicon oxide film 105 and the silicon nitride film 106 form a double sidewall 107.
[0006]
In such a structure, for example, after a relatively thin silicon oxide film is deposited on the entire surface to cover the silicon substrate 101 and the gate electrode 103, a relatively thick silicon nitride film is formed on the entire surface, and RIE or the like is used. It is obtained by etching back with anisotropic etching. The silicon nitride film 106 does not directly contact the silicon substrate 101, and prevents hydrogen or internal stress in the nitride film from affecting the reliability of the device.
[0007]
[Patent Document 1]
JP 2001-185505 A
[0008]
[Patent Document 2]
JP 2002-110930 A
[0009]
[Problems to be solved by the invention]
However, in the double sidewall structure 107 shown in FIG. 1A, the silicon oxide film 105 is exposed at the end of the double sidewall 107 as shown by circles A and B. For this reason, when pretreatment is performed with a hydrofluoric acid (HF) -based cleaning solution in the next step, etching proceeds from the exposed portion, and the silicon oxide film 105 recedes as shown in FIG. As a result, depressions 109 are formed at the base and the upper portion of the double side wall 107.
[0010]
In recent years, in particular, with the miniaturization of devices, a technique of raising a source / drain (Elevated-SD) on a substrate by selective epitaxial growth has attracted attention, but when performing selective epitaxial growth on a silicon substrate, It is necessary to perform hydrofluoric acid treatment longer than silicide formation. In this case, there is a problem that the retreat of the silicon oxide film 105 proceeds further, and in some cases, the sidewall structure is completely broken due to lift-off.
[0011]
[Means for Solving the Problems]
Therefore, the present invention provides a semiconductor device having a double side wall structure which is not deformed by hydrofluoric acid treatment after forming a side wall, and a method for manufacturing the same.
[0012]
According to a first aspect of the present invention, a semiconductor device includes a semiconductor substrate, a gate electrode located on the semiconductor substrate via a gate insulating film, and a double sidewall covering a side wall of the gate electrode. The wall is
(A) a first sidewall located on the side wall of the gate electrode and lower than the height of the gate electrode;
(B) a hydrofluoric acid-resistant second sidewall that continuously covers the entire surface of the first sidewall and the upper sidewall of the gate electrode protruding from the first sidewall;
It consists of.
[0013]
According to this configuration, the first sidewall is completely covered by the hydrofluoric acid-resistant second sidewall, and is not damaged by erosion or deformation due to the subsequent hydrofluoric acid treatment.
[0014]
The second sidewall extends from the upper end of the gate electrode along the upper sidewall, and further extends along the surface of the first sidewall to the semiconductor substrate.
[0015]
The first sidewall is formed of a silicon oxide film. The second sidewall is a silicon nitride film, a silicon oxynitride film, or another hydrofluoric acid-resistant insulating film.
[0016]
According to a second aspect of the present invention, a method for manufacturing a semiconductor device includes the following steps.
(A) forming a gate electrode on a semiconductor substrate;
(B) forming a first insulating film covering the gate electrode and the semiconductor substrate;
(C) forming a first sidewall lower than the height of the gate electrode on the sidewall of the gate electrode by etching and removing the first insulating film until the upper sidewall of the gate electrode is exposed;
(D) forming a hydrofluoric acid-resistant second sidewall that continuously covers the entire first sidewall and the upper sidewall of the gate electrode to form a double sidewall;
(E) washing the semiconductor substrate with a hydrofluoric acid-based treatment liquid;
[0017]
According to such a method of manufacturing a semiconductor device, it is possible to reliably prevent the double sidewall structure from being damaged by erosion, deformation, and the like due to the subsequent hydrofluoric acid treatment.
[0018]
The above-described manufacturing method further includes a step of forming a source / drain by selective epitaxial growth on the substrate after cleaning by hydrofluoric acid treatment. In order to perform selective epitaxial growth, it is necessary to sufficiently remove a natural oxide film, a thermal oxide film, and the like existing on the substrate surface to obtain a clean surface. Since it is protected, hydrofluoric acid cleaning can be sufficiently performed. As a result, a good selective epitaxial growth layer can be grown on the substrate.
[0019]
Alternatively, the method for manufacturing a semiconductor device further includes a step of forming silicide on the substrate after cleaning by hydrofluoric acid treatment.
[0020]
For example, when a source / drain is formed in a semiconductor substrate using a double sidewall as a mask, silicide is formed on the source / drain after forming the source / drain and cleaning the substrate.
[0021]
As described above, the method of the present invention can be applied to the manufacture of any semiconductor device including a process requiring hydrofluoric acid treatment as a pretreatment such as selective epitaxial growth or silicide formation.
[0022]
Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the drawings.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 2 is a diagram showing a basic structure of a semiconductor device having a double sidewall structure according to the present invention. The semiconductor device 1 has a gate electrode 13 located on a silicon substrate 11 via a gate oxide film 12, a source / drain impurity diffusion region 4 formed on the silicon substrate 11, and a double side covering the side wall of the gate electrode 13. A wall 22 is provided. The double sidewall 22 is
(A) a first side wall 18 located on the side wall of the gate electrode 13 and lower than the height of the gate electrode 13;
(B) It is composed of the entire surface of the first sidewall 18 and the hydrofluoric acid-resistant second sidewall 20 that continuously covers the upper sidewall 13 a of the gate electrode 13 protruding from the first sidewall 18.
[0024]
The second sidewall 20 extends from the upper end of the gate electrode 13 along the upper sidewall 13a, and further extends along the surface of the first sidewall 18 to the silicon substrate 11. In the configuration of the double side wall 22, the first side wall 18 is completely covered with the hydrofluoric acid-resistant second side wall 20, and even at the upper end portion (circle C) of the gate electrode 13, the silicon directly under the gate electrode 13 The first sidewall 18 is not exposed on the substrate 11 (circle D).
[0025]
The source / drain impurity diffusion region 4 includes an extension 2 located immediately below the double sidewall 22 and a source / drain 3 located outside the double sidewall 22. 3 is not located.
[0026]
The film thickness of the second sidewall 20 is set to １ ／ to の of the film thickness of the first sidewall 18. Accordingly, the first sidewall can be reliably protected from the hydrofluoric acid treatment, and the contact area with the extension 2 can be minimized.
[0027]
Such a double sidewall structure is applied to any semiconductor device manufactured through a process requiring hydrofluoric acid treatment for its pretreatment, such as selective epitaxial growth or silicide formation.
[0028]
3 to 5 show a manufacturing process of the semiconductor device according to the first embodiment of the present invention. In the first embodiment, an example will be described in which the double sidewall structure of FIG. 2 is applied to a MOS transistor having a raised source / drain.
[0029]
First, as shown in FIG. 3A, 100 nm of polysilicon is deposited on a silicon substrate 11 via a gate oxide film 12. A thin silicon nitride (SiN) cap layer is formed on the polysilicon film, and the gate is patterned and etched by photolithography. Thereby, the gate electrode 13 is formed. The SiN cap 14 remains on the gate electrode 13. Thereafter, using the gate electrode 13 and the SiN cap 14 as a mask, impurities are implanted in a self-aligned manner to form a shallow extension 15.
[0030]
Next, as shown in FIG. 3B, a silicon oxide film (SiO ₂ ) 17 is formed on the entire surface.
[0031]
Next, as shown in FIG. 3C, the silicon oxide film 17 is etched back by the RIE method. At this time, over-etching is performed so that the upper end of the silicon oxide film 17 remaining on the side wall of the gate electrode 13 is lower than the height of the gate electrode 13 by about 20 nm. Thereby, the first sidewall 18 having a taper shape is formed. In this state, the upper side wall 13 a of the gate electrode 13 is exposed without being covered by the first side wall 18.
[0032]
Next, as shown in FIG. 4D, a silicon nitride film (SiN) 19 is deposited on the entire surface by a CVD method to a thickness of 20 nm. Thereby, the upper side wall 13a of the gate electrode 13 and the surface of the silicon substrate 11 exposed in the previous step are covered. The SiN cap 14 formed on the gate electrode 13 is integrated with the silicon nitride film 19
Next, as shown in FIG. 4E, the silicon nitride film 19 is etched by anisotropic etching such as RIE. As a result, the silicon nitride film on the silicon substrate 11 and part of the silicon nitride film on the upper surface of the gate electrode 13 are removed, but the upper sidewall 13a of the gate electrode 13 and the first SiO 2 film are removed. ₂ The silicon nitride film remains on the side wall 18.
[0033]
As a result of the RIE, as shown in FIG. ₂ 2) A second sidewall (SiN) 20 that completely covers 18 is formed, and a double sidewall 22 is formed. On the gate electrode 13, a silicon nitride film 19a having the same thickness as the initial SiN cap remains. In this state, a natural oxide film or a thermal oxide film (not shown) equivalent to 10 nm on the silicon substrate 11 is etched away by hydrofluoric acid (HF) treatment. This hydrofluoric acid treatment is performed prior to the selective epitaxial growth in the next step, and is performed so that the oxide film existing on the extension 15 is surely removed. During the hydrofluoric acid treatment, the first sidewall 18 made of a silicon oxide film is completely covered with a second sidewall 20 made of a hydrofluoric acid-resistant silicon nitride film. Therefore, it is possible to reliably protect against erosion without changing the shape of the double side wall 22. At the lower end of the second sidewall 20, the silicon nitride film contacts a portion of the extension 15, but the benefit of sidewall protection is much greater. Further, since the contact width is at most about 20 nm (that is, about the thickness of the nitride film) and is apart from the gate oxide film 12, the influence of the nitride film on device operation is minimized.
[0034]
Next, as shown in FIG. 5G, using the silicon nitride film 19a on the gate electrode 13 and the second sidewall 20 as a mask, a silicon layer 23 is formed to a thickness of 20 nm on the exposed silicon substrate 11 by selective epitaxial growth. Form up to. Epitaxial growth is performed, for example, using SiH ₂ Cl ₂ And HCl to H ₂ It is supplied onto the silicon substrate 11 by a carrier gas, and is performed at a low temperature of 900 ° C. or less under reduced pressure. Since the natural oxide film of the silicon substrate 11 has been sufficiently cleaned and removed in the previous step, a good epitaxial growth layer can be formed.
[0035]
Next, as shown in FIG. 5H, ions are implanted into the selectively epitaxially grown silicon layer 23 in a self-aligned manner using the double side wall 22 and the nitride film 19a on the gate electrode 13 as a mask. Thereafter, a raised source / drain region 25 which rises to the side surface of the gate electrode 13 is formed by thermal diffusion. The raised source / drain region 25 and the extension 15 constitute a source / drain impurity diffusion region 29.
[0036]
In general, as devices become finer, the source / drain regions are also designed to be shallower in accordance with the scale reduction. Although the electric resistance increases when the source / drain region becomes shallower, the raised source / drain structure secures the dimension in the depth direction, prevents the electric resistance from increasing, and maintains the operation speed.
[0037]
Next, as shown in FIG. 5I, the thin silicon nitride film 19a on the gate electrode 13 is removed with phosphoric acid, and a silicide 27 is formed on the upper surface of the gate electrode 13 and the surface of the raised source / drain region 25. To form The silicide 27 is formed by performing a heat treatment after sputtering a metal or by a CVD method, and is formed of cobalt silicide (CoSi ₂ ), Platinum silicide (PtSi ₂ ), Titanium silicide (TiSi ₂ ) Can be used. Before forming the silicide 27, a light hydrofluoric acid (HF) treatment may be performed. Also at this time, the first sidewall 18 of the silicon oxide film is entirely protected by the second sidewall 20, so that the problem of erosion does not occur.
[0038]
Thereafter, although not shown, an interlayer insulating film is formed on the entire surface, a silicide 27 on the raised source / drain region 25 and a plug reaching the silicide 27 on the gate electrode 13 are formed, and a wiring is formed on the interlayer insulating film. Form a layer to form a logic circuit.
[0039]
FIG. 6 is a cross-sectional view of a logic region including a MOS transistor having a double sidewall according to the first embodiment. The PMOS transistor located in the n-type well of the semiconductor substrate 11 sandwiches the gate electrode 13 formed via the gate oxide film 12, the double sidewall 22 located on the side wall of the gate electrode 13, and the gate electrode 13. It has source / drain impurity diffusion regions 29 formed in the substrate region. As described above, the double side wall 22 has the first side wall 18 lower than the height of the gate electrode 13 and the second side wall continuously covering the front surface of the first side wall and the upper side wall of the protruding gate electrode 13. And a wall 20. The source / drain impurity diffusion region 29 includes a low concentration p-type impurity extension 15 located immediately below the double side wall 22 and a high concentration p-type impurity rising outside the double side wall 22. And a source / drain 25. The upper surface of the gate electrode 13 and the surfaces of the raised source / drain 25 are covered with silicide 27.
[0040]
Similarly, an NMOS transistor having the double side wall 22 is located in the p-type well with the element isolation region 51 interposed therebetween. The NMOS transistor has a source / drain impurity diffusion region 29 including an extension 15 into which a low concentration n-type impurity is implanted and a high concentration n-type raised source / drain 25.
[0041]
The raised source / drain 25 of the PMOS and NMOS transistors is connected to an upper wiring 55 via a plug 54 penetrating through an interlayer insulating film 53 to form a logic circuit. Although not shown, the gate electrode 13 is also connected to the upper wiring via the silicide 27 and the plug.
[0042]
In such a logic circuit, the gate structure can be surely protected from the cleaning step by the double sidewall formed by self-alignment. Therefore, the reliability of operation with a fine circuit configuration is maintained. In addition, the hydrofluoric acid-resistant second sidewall 18 is located away from the gate oxide film 12, and the area in contact with the active region is also minimized. Also in this respect, the reliability of the operation can be maintained.
[0043]
7 to 9 are views showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention. In the second embodiment, an example in which the present invention is applied to general silicide formation will be described.
[0044]
First, as shown in FIG. 7A, a polysilicon gate electrode 13 is formed on a silicon substrate 11 via a gate oxide film 12 by performing patterning and etching by a usual method. The height of the gate electrode is set to 100 nm as in the first embodiment. Using this gate electrode as a mask, a shallow extension 15 is formed by implanting impurities in a self-aligned manner. At this time, the impurity is also implanted into the polysilicon gate electrode 13.
[0045]
Next, as shown in FIG. 7B, a 50 nm-thick silicon oxide film (SiO ₂ ) 17 is formed.
[0046]
Next, as shown in FIG. 7C, the silicon oxide film 17 is etched back by RIE. At this time, over-etching is performed so that the upper end of the silicon oxide film 17 remaining on the side wall of the gate electrode 13 is lower than the height of the gate electrode 13 by about 20 nm. Thereby, the first sidewall 18 having a taper shape is formed. In this state, the upper side wall 13 a of the gate electrode 13 is exposed without being covered by the first side wall 18.
[0047]
Next, as shown in FIG. 8D, a silicon nitride film (SiN) 19 is deposited on the entire surface by a CVD method to a thickness of 20 nm. Thus, the upper surface of the gate electrode 13 exposed in the previous step, the upper side wall 13a, and the surface of the silicon substrate 11 are all covered.
[0048]
Next, as shown in FIG. 8E, the silicon nitride film 19 is etched by anisotropic etching such as RIE. Thereby, the silicon nitride film on the silicon substrate 11 and the silicon nitride film on the upper surface of the gate electrode 13 are removed, but the upper sidewall 13a of the gate electrode 13 and the first SiO 2 ₂ The silicon nitride film remains on the side wall 18.
[0049]
As a result of the RIE, as shown in FIG. ₂ 2) A second sidewall (SiN) 20 that completely covers 18 is formed, and a double sidewall 22 is formed. The source / drain 35 is formed by performing ion implantation using the double side wall 22 as a mask. The source / drain impurity diffusion region 39 is constituted by the extension 15 immediately below the double sidewall 22 and the source / drain 35.
[0050]
Next, as shown in FIG. 9G, the natural oxide film and the thermal oxide film on the silicon substrate 11 and the gate electrode 13 are removed by washing with hydrofluoric acid, and the source and drain 35 and the gate electrode 13 are removed. A silicide 37 is formed. During the hydrofluoric acid treatment, the silicon oxide film forming the first side wall 18 is completely covered with the second side wall, so that the silicon oxide film can be sufficiently cleaned and removed without fear of erosion. Therefore, silicide can be favorably formed on the cleaned surface.
[0051]
In the above-described embodiment, the description has been made using the example in which the double sidewall structure is applied to the logic circuit. However, the double sidewall structure of the present invention is also applied to the access transistor of the memory cell. When the memory region and the logic region are formed on the same chip, the double sidewall of the access transistor of the memory cell and the double sidewall of the MOS transistor of the logic region can be formed at the same time.
[0052]
Further, the present invention is directed to protection of a side wall of a stacked control gate in a MONOS (Metal Oxide Nitride Semiconductor) type or SONOS (Poly-Silicon Oxide Nitride Oxide Silicon) type non-volatile semiconductor memory having a charge trapping insulating film in a gate stacked insulating film. Is preferably used. In particular, in MONOS and SONOS memories, it is important to trap charges at the interface of the nitride film sandwiched between the oxide films, and the need for a double sidewall that can reliably protect the gate laminated insulating structure from the cleaning process is required. Is expensive.
[0053]
In the above-described embodiment, the silicon oxide film is used for the first sidewall and the silicon nitride film is used for the second sidewall. However, the second sidewall is made of silicon oxynitride (SiON) or the like. It can be formed of any acidic material.
[0054]
Finally, with regard to the above description, the following supplementary notes are disclosed.
(Supplementary Note 1) A semiconductor substrate,
A gate electrode located on a semiconductor substrate via a gate insulating film,
A double sidewall covering the side wall of the gate electrode;
Comprising, the double sidewall,
A first sidewall located on a side wall of the gate electrode and lower than the height of the gate electrode;
A hydrofluoric acid-resistant second sidewall that continuously covers the entire surface of the first sidewall and the upper sidewall of the gate electrode protruding from the first sidewall;
A semiconductor device comprising:
(Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the thickness of the second sidewall is １ ／ to の of the thickness of the first sidewall.
(Supplementary Note 3) The semiconductor device according to supplementary note 1, wherein the second sidewall is formed of a silicon nitride film, a silicon oxynitride film, or any other hydrofluoric acid-resistant insulating film.
(Supplementary Note 4) a step of forming a gate electrode on the semiconductor substrate;
Forming a first insulating film covering the gate electrode and the semiconductor substrate;
Etching the first insulating film until the upper sidewall of the gate electrode is exposed, forming a first sidewall lower than the height of the gate electrode on the sidewall of the gate electrode;
Forming a hydrofluoric acid-resistant second sidewall that continuously covers the entire first sidewall and the upper sidewall of the gate electrode to form a double sidewall;
Cleaning the semiconductor substrate with a hydrofluoric acid-based processing solution;
A method for manufacturing a semiconductor device including:
(Supplementary Note 5) The method of manufacturing a semiconductor device according to Supplementary Note 4, further comprising: forming a raised source / drain by selective epitaxial growth on the semiconductor substrate after the cleaning.
(Supplementary Note 6) The method for manufacturing a semiconductor device according to supplementary note 4, further comprising a step of forming a silicide on the semiconductor substrate after the cleaning.
(Supplementary Note 7) The method according to Supplementary Note 6, further comprising forming a source / drain on the semiconductor substrate using a double sidewall as a mask, wherein the silicide is formed on the source / drain of the semiconductor substrate after cleaning. 13. The method for manufacturing a semiconductor device according to item 5.
(Supplementary Note 8) The method of manufacturing a semiconductor device according to Supplementary Note 5, further comprising a step of forming a silicide on the elevated source / drain.
(Supplementary Note 9) The method for manufacturing a semiconductor device according to Supplementary Note 8, wherein cleaning by hydrofluoric acid treatment is further performed prior to formation of the silicide on the raised source / drain.
(Supplementary Note 10) The method according to Supplementary Note 4, wherein the second sidewall is formed of a silicon nitride film, a silicon oxynitride film, or any other hydrofluoric acid-resistant insulating film.
[0055]
【The invention's effect】
As described above, according to the present invention, the double sidewalls do not erode the sidewall structure even when hydrofluoric acid treatment is performed in a subsequent step. Further, since the double sidewall can be formed in a self-alignment manner, it is possible to sufficiently cope with miniaturization.
[0056]
Since the hydrofluoric acid treatment can be sufficiently performed by the stable double sidewall structure, selective epitaxial growth and silicide formation can be favorably performed.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the structure of a conventional double sidewall and its problems.
FIG. 2 is a diagram showing a basic structure of a semiconductor device having a double sidewall structure according to the present invention.
FIG. 3 is a diagram (part 1) illustrating a step of manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 4 is a diagram (part 2) illustrating a step of manufacturing the semiconductor device according to the first embodiment of the present invention, illustrating a step following the step illustrated in FIG. 3 (c);
FIG. 5 is a diagram (part 3) illustrating a step of manufacturing the semiconductor device according to the first embodiment of the present invention, which is a view illustrating a step subsequent to FIG. 4 (f).
FIG. 6 is a configuration diagram of a logic circuit including a semiconductor device having a double sidewall according to the first embodiment.
FIG. 7 is a diagram (part 1) illustrating a step of manufacturing a semiconductor device according to the second embodiment of the present invention;
FIG. 8 is a diagram (part 2) illustrating a step of manufacturing the semiconductor device according to the second embodiment of the present invention, which is a view illustrating a step following the step in FIG. 7 (c).
FIG. 9 is a diagram (part 3) illustrating a step of manufacturing the semiconductor device according to the second embodiment of the present invention, which is a view illustrating a step following FIG. 8 (f).
[Explanation of symbols]
1 Semiconductor devices
2,15 extensions
3,35 source / drain
4, 29, 39 Source / drain impurity diffusion regions
11 Silicon substrate (semiconductor substrate)
12 Gate oxide film (gate insulating film)
13 Gate electrode
13a Gate electrode upper side wall
14 cap
17 Silicon oxide film
18 1st sidewall
19 Silicon nitride film
20 Second sidewall
22 Double sidewall
25 Source / Drain
27, 37 Silicide

Claims (5)

A semiconductor substrate;
A gate electrode located on the semiconductor substrate via a gate insulating film,
A double sidewall covering a side wall of the gate electrode, wherein the double sidewall comprises:
A first sidewall located on the side wall of the gate electrode and lower than the height of the gate electrode;
A semiconductor device comprising: a hydrofluoric acid-resistant second sidewall that continuously covers an entire surface of the first sidewall and an upper sidewall of a gate electrode protruding from the first sidewall. Forming a gate electrode on the semiconductor substrate;
Forming a first insulating film covering the gate electrode and the semiconductor substrate;
Removing the first insulating film by etching until an upper sidewall of the gate electrode is exposed, and forming a first sidewall lower than the height of the gate electrode on the sidewall of the gate electrode;
Forming a double side wall by forming a hydrofluoric acid-resistant second side wall that continuously covers the entire surface of the first side wall and the upper side wall of the gate electrode;
Cleaning the semiconductor substrate with a hydrofluoric acid-based treatment liquid. 3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming a raised source / drain by selective epitaxial growth on the semiconductor substrate after the cleaning. 3. The method according to claim 2, further comprising forming a silicide on the semiconductor substrate after the cleaning. The method according to claim 4, further comprising forming a source / drain on the semiconductor substrate using the double sidewall as a mask, wherein the silicide is formed on the source / drain of the semiconductor substrate after cleaning. The manufacturing method of the semiconductor device described in the above.

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