JP2009283863A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device by which a pattern is stably formed with high precision. <P>SOLUTION: A first inorganic film HU which consists of a first inorganic material, and a second inorganic film HD which consists of a second inorganic material and is located between the first inorganic film HU and a film PS to be processed are formed on the film PS to be processed. The first inorganic film HU is etched using a first photoresist mask R1 on the first inorganic film HU as a mask. A second photoresist mask R2 is formed on the second inorganic film HD. The second inorganic film HD is etched using the second photoresist mask R2 and the first inorganic film HU as masks. The film PS to be processed is etched using the second inorganic film HD as a mask. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a photoresist mask.

  In the patterning of the 45 nm node, it is considered that the conventional immersion lithography technique can be applied. However, in the 32 nm node (half pitch 45 nm), it is difficult to simply apply the conventional immersion lithography without drastically improving the immersion technique or shortening the wavelength of the light source using extreme ultraviolet rays. It is. In view of this, studies have been made to combine a double patterning technique with a conventional immersion lithography technique. Double patterning is a technique in which one pattern is divided into two low-density patterns that can be transferred by an exposure machine and exposed. By combining the two patterns, the density of the finally obtained pattern can be increased.

  For example, in Japanese Patent Laid-Open No. 2005-129761 (Patent Document 1), an array of a plurality of holes is formed at intervals equal to or less than the resolution of the exposure apparatus by the following steps.

  First, a first resist film is applied to the base film. A plurality of first resist opening patterns arranged at intervals between adjacent openings having a resolution or higher are formed in the first resist film. A first hole pattern is formed in the base film by etching using the first resist opening pattern. After removing the first resist film, a second resist film is newly applied on the base film. A second resist opening pattern is formed in the second resist film between the first resist opening patterns. A second hole pattern is formed in the base film by etching using the second resist opening pattern.

  In Japanese Patent Application Laid-Open No. 2004-296930 (Patent Document 2), a fine pattern having a resolution equal to or higher than the resist resolution is formed on a workpiece by the following steps.

First, a mask layer and a sparse pitch resist pattern are formed on a workpiece. Next, the mask layer is etched using this resist pattern as a mask, and the film thickness of a part of the mask layer is reduced. The next resist pattern is formed so as to cover a part of this region, and etching is performed again. Thereby, a fine pattern is formed in the mask layer. The member to be processed is etched using the mask layer on which the fine pattern is formed as a hard mask.
JP 2005-129761 A JP 2004-296930 A

  In the technique disclosed in Japanese Patent Laid-Open No. 2005-129761 (Patent Document 1), when the second resist film for forming the second hole pattern is applied, the first hole is formed in the base film (processed film). A pattern has already been formed. That is, the film to be processed already has a step of the first hole pattern. For this reason, when the film thickness of the film to be processed is thick, for example, as a gate electrode film of a semiconductor device, the second resist film is applied to a surface having a large step. Since the exposure accuracy is lowered on the surface having such a large step, there is a problem that it is difficult to pattern the film to be processed with high accuracy.

  In the technique of Japanese Patent Application Laid-Open No. 2004-296930 (Patent Document 2), in order to form a hard mask, it is necessary to partially etch a mask layer, that is, one layer by a predetermined depth in the thickness direction. However, the actual etching depth is affected by the process variation of the etching rate and the surface step. Therefore, since the dimensional variation of the formed hard mask becomes large, patterning of a film to be processed using this hard mask has a problem that the reproducibility is lowered.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device manufacturing method capable of stably forming a pattern with high accuracy.

The manufacturing method of the semiconductor device according to the present embodiment includes the following steps.
A film to be processed is formed on the semiconductor substrate. A first inorganic film made of a first inorganic material and a second inorganic film made of a second inorganic material different from the first inorganic material and positioned between the first inorganic film and the processed film on the film to be processed; Is formed. A first photoresist mask having a first pattern is formed on the first inorganic film by photolithography. In order to transfer the first pattern to the first inorganic film, selectively using the first photoresist mask as a mask under etching conditions in which the etching rate of the first inorganic material is larger than the etching rate of the second inorganic material. The first inorganic film is etched. After the step of etching the first inorganic film, a second photoresist mask having a second pattern different from the first pattern is formed on the second inorganic film by photolithography. In order to transfer the composite pattern in which the first pattern and the second pattern are combined to the second inorganic film, the second photoresist is etched under an etching condition in which the etching rate of the second inorganic material is larger than the etching rate of the first inorganic material. The second inorganic film is selectively etched using the mask and the first inorganic film as a mask. After the step of etching the second inorganic film, the processed film is selectively etched using the second inorganic film as a mask in order to transfer the composite pattern to the processed film.

  According to the semiconductor device manufacturing method of the present embodiment, the first and second photoresist masks are exposed before the patterning of the film to be processed is started. Therefore, exposure is performed without being affected by the step caused by the pattern shape of the film to be processed. For this reason, since the exposure accuracy can be increased, the pattern of the film to be processed can be formed with high accuracy.

  In the etching for transferring the first pattern to the first inorganic film, the second inorganic film is used as an etching stopper. For this reason, since the reproducibility of the etching depth is high as compared with the case where the etching stopper is not used, the film to be processed can be stably patterned.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a plan view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. 2 is a schematic cross-sectional view (A) along the line IIA-IIA in FIG. 1 and a schematic cross-sectional view (B) along the line IIB-IIB.

  With reference to FIG. 1 and FIG. 2, the schematic structure of semiconductor device SD1 of this Embodiment is demonstrated first. The semiconductor device SD1 is an embedded microcomputer on which a nonvolatile memory is mounted, for example, and has a logic area LR and a memory area MR. The logic region LR includes, for example, an MPU (Micro Processing Unit) region, an I / O (Input / Output) region, and a ROM control region, and the wiring patterns WR1 to WR3 having a relatively complicated shape are used as gate electrodes. It contains a lot as a film. The memory region MR has, for example, a ROM (Read Only Memory) region and a RAM (Random Access Memory) region. A wiring pattern WR4 having a regular shape as compared with the wiring patterns WR1 to WR3 is used as a gate electrode. Includes as a membrane.

  Next, details of the configuration of the semiconductor device SD1 will be described. The semiconductor device SD1 includes a silicon substrate SB, a polysilicon film PS, and an oxide film OX. The oxide film OX is provided on the silicon substrate SB. The polysilicon film PS is provided on the oxide film OX. Wiring patterns WR1 to WR4 (FIG. 1) are formed by the polysilicon film PS.

  The wiring pattern WR1 is a line pattern having a bend A1. The wiring pattern WR1 has a width dimension W and a spacing dimension S. The spacing dimension S is smaller than the minimum spacing dimension of the pattern that can be formed by a single exposure by the exposure apparatus used for manufacturing the semiconductor device SD1. The wiring pattern WR1 is formed by patterning that includes a step of bending two patterns and connecting them at A1.

  The wiring pattern WR2 is a plurality of line patterns, and the line patterns form the abutments A2a and A2b with the interval dimension S. In the butt A2a, the ends of the pair of wiring patterns WR2 face each other. In the butt A2b, the other end portion is arranged near one intermediate portion of the pair of wiring patterns WR2.

  The wiring pattern WR3 is a pair of patterns that run parallel to each other with an interval dimension S therebetween. An isolated space A3 is formed in the region where the spacing dimension S is spaced.

  The wiring pattern WR4 is a line and space pattern having a pitch dimension P, a spacing dimension S, and a width dimension G. The pitch dimension P is smaller than the minimum pitch dimension Pmin of a pattern that can be formed by a single exposure by an exposure apparatus used for manufacturing the semiconductor device SD1, for example, P = Pmin / 2. The width dimension G corresponds to the gate length dimension of the gate electrode film of the semiconductor device SD1.

  Next, a method for manufacturing the semiconductor device SD1 of the present embodiment will be described. FIG. 3 is a plan view schematically showing a first step of the method for manufacturing the semiconductor device in the first embodiment of the present invention. 4 to 10 are diagrams showing the first to seventh steps of the semiconductor device manufacturing method according to the first embodiment of the present invention in the order of steps, and are schematic cross-sectional views corresponding to line IVA-IVA in FIG. It is a schematic sectional drawing (B) corresponding to A) and line IVB-IVB.

  Referring mainly to FIGS. 3 and 4, a polysilicon film PS (film to be processed) is formed on silicon substrate SB (semiconductor substrate) via oxide film OX. A lower hard mask film HD and an upper hard mask film HU are sequentially formed on the polysilicon film PS. That is, an upper hard mask film HU (first inorganic film) and a lower hard mask film HD (second inorganic film) positioned between the upper hard mask film HU and the polysilicon film PS are formed on the polysilicon film PS. A laminated film is formed. The upper hard mask film HU is made of silicon oxide (first inorganic material). The lower hard mask film HD is made of silicon nitride (second inorganic material) which is a material different from the material of the upper hard mask film HU. The thicknesses of the polysilicon film PS, the lower hard mask film HD, and the upper hard mask film HU are, for example, 100 nm, 50 nm, and 35 nm.

  A first photoresist mask R1 having a first pattern (solid line pattern in FIG. 3) is formed on the upper hard mask film HU by photolithography. That is, the photoresist is applied onto the upper hard mask film HU and the exposure corresponding to the first pattern is performed. This first pattern corresponds to a part of the patterns of the wiring patterns WR1 to WR4. The first photoresist mask R1 includes a solid line pattern on the right side of FIG. 3 and a line and space pattern as shown in FIG. 4B. The line and space pattern has a pitch dimension 2P that is twice the pitch dimension P of the wiring pattern WR4. The pitch dimension 2P corresponds to the minimum pitch dimension of the line and space pattern that can be formed by photolithography of the first photoresist mask R1.

  4A and 4B, the wiring patterns WR1 and WR4 shown by the two-dot chain line are shown for easy viewing of the arrangement of the first photoresist mask R1, and are not yet patterned. Absent.

Next, the upper hard mask film HU is selectively etched by anisotropic etching using the first photoresist mask R1 as a mask under etching conditions in which the etching rate of silicon oxide is higher than the etching rate of silicon nitride. This etching is, for example, RIE (Reactive Ion Etching) using a mixed gas of C ₄ F ₈ and Ar as a process gas. After the etching is completed, the first photoresist mask R1 is removed.

  Referring to FIG. 5, the first pattern is transferred to upper hard mask film HU by the above-described processing steps.

  Referring mainly to FIG. 6, antireflection film BC is applied on lower hard mask film HD. The antireflection film BC functions as a BARC (Bottom Antireflection Coating) film to prevent reflection during exposure. The antireflection film BC also has a function as a buried film that fills the etched region of the upper hard mask film HU. Thereby, the uneven shape due to the upper hard mask film HU on the lower hard mask film HD is relaxed, and a flat surface of the antireflection film BC is formed.

  A second photoresist mask R2 having a second pattern different from the first pattern is formed on the lower hard mask film HD by photolithography. That is, the application of the photoresist onto the antireflection film BC and the exposure corresponding to the second pattern are performed. This 2nd pattern is a pattern shown with the dashed-two dotted line of FIG. 3, and respond | corresponds to some of the patterns of wiring patterns WR1-WR4. The first pattern and the second pattern have overlapping portions as shown in the upper left portion of FIG. The second photoresist mask R2 includes a two-dot chain line pattern on the right side of FIG. 3 and a line and space pattern as shown in FIG. 6B. The line and space pattern has a pitch dimension 2P that is twice the pitch dimension P of the wiring pattern WR4. The pitch dimension 2P corresponds to the minimum pitch dimension of the line and space pattern that can be formed by photolithography of the second photoresist mask R2.

  Note that the wiring pattern WR1 indicated by a two-dot chain line in FIG. 6A is shown to make the arrangement of the second photoresist mask R2 and the upper hard mask film HU easier to see, and has not been patterned yet.

Referring to FIG. 7, the lower hard mask film is selectively used by using second photoresist mask R2 and upper hard mask film HU as a mask under etching conditions in which the etching speed of silicon nitride is higher than the etching speed of silicon oxide. HD is etched. This etching is RIE using a mixed gas composed of, for example, C ₄ F ₈ , CH ₂ F ₂ , CF ₄ , O ₂ and Ar as a process gas. In this etching, the portion of the antireflection film BC that is not covered with the second photoresist mask R2 is also etched. As a result, a combined pattern in which the first pattern and the second pattern are combined is transferred to the lower hard mask film HD. Next, the second photoresist mask R2 is removed.

  Referring to FIG. 8, antireflection film BC is removed. Next, the upper hard mask film HU is removed. The removal of the upper hard mask film HU is performed by etching the upper hard mask film HU under an etching condition in which the etching rate of silicon oxide is higher than the etching rate of silicon nitride. Specifically, for example, wet etching with hydrofluoric acid is performed.

Referring to FIG. 9, polysilicon film PS is selectively etched using lower hard mask film HD as a mask under etching conditions in which the etching rate of polysilicon is higher than the etching rates of silicon nitride and silicon oxide. . This etching is RIE using, for example, a mixed gas composed of HBr, Cl ₂ , O _{2 and the} like as a process gas.

  Referring to FIG. 10, a synthetic pattern in which the first pattern and the second pattern are combined is transferred to polysilicon film PS by the etching. Next, the lower hard mask film HD and the exposed portion of the oxide film OX are removed.

Thus, the semiconductor device SD1 (FIGS. 1 and 2) of the present embodiment is manufactured.
According to the present embodiment, before the patterning of the polysilicon film PS (FIG. 10) is started, the exposure of the first photoresist mask R1 (FIG. 4) and the exposure of the second photoresist mask R2 (FIG. 6). Is done. Therefore, the second photoresist mask R2 in addition to the first photoresist mask R1 is exposed without being affected by the level difference due to the pattern shape (FIG. 2) of the polysilicon film PS. For this reason, since the exposure accuracy of the second photoresist mask R2 can be increased, the pattern of the film to be processed can be formed with high accuracy.

  Unlike the present embodiment, when the second photoresist mask R2 is exposed after the pattern of the first photoresist mask R1 is transferred to the polysilicon film PS, the second photoresist mask R2 is polysilicon having a pattern. Since it is formed on the film PS, the exposure accuracy of the second photoresist mask R2 is lowered.

  Further, according to the present embodiment, the lower hard mask film HD is used as an etching stopper in the etching for transferring the first pattern to the upper hard mask film HU (FIG. 4). For this reason, since the reproducibility of the etching depth is higher than when no etching stopper is used, the upper hard mask film HU can be patterned with high reproducibility. Therefore, the reproducibility of the patterning (FIG. 8) of the lower hard mask film HD using the upper hard mask film HU can be improved.

  Further, a portion of the polysilicon film PS that is covered with at least one of the first photoresist mask R1 and the second photoresist mask R2 remains as a pattern. Therefore, in the pattern finally formed on the polysilicon film PS, the portion patterned by one of the first photoresist mask R1 and the second photoresist mask R2 is the first photoresist mask R1 and the second photoresist mask. Since it is not affected by the overlay error between R2, it has high dimensional accuracy.

  For example, the plurality of wiring patterns WR4 (FIG. 1) have the width dimension G with high dimensional accuracy even when the above overlay error exists. This is because, as shown in FIG. 3, the overlay error of the error dimension d acts to change the interval dimension between the adjacent wiring patterns WR4 from S to S + d or S-d (FIG. 3). This is because it does not act on G. Therefore, since the dimensional accuracy of the width dimension G, that is, the gate length can be increased, variation in characteristics of the semiconductor element having the wiring pattern WR4 as the gate electrode film can be suppressed.

  Etching of the lower hard mask film HD is performed under etching conditions in which the etching rate of silicon nitride is higher than the etching rate of silicon oxide. Therefore, since the upper hard mask film HU made of silicon oxide is difficult to be etched, even when the upper hard mask film HU is thin, the shape of the upper hard mask film HU is not changed during the etching of the lower hard mask film HD (FIG. 7). Retained. Therefore, since the thin upper hard mask film HU can be used, the surface step caused by the upper hard mask film HU when the second photoresist mask R2 (FIG. 6) is formed is reduced. Therefore, since the second photoresist mask R2 is formed on a flatter surface, the second photoresist mask R2 can be formed with high accuracy.

  The pitch dimension P of the line and space pattern of the wiring pattern WR4 is the line and space pattern that can be formed by photolithography in each of the step of forming the first photoresist mask R1 and the step of forming the second photoresist mask R2. It is smaller than the minimum pitch dimension 2P. Therefore, a denser line and space pattern can be formed than a line and space pattern that can be formed by a single photolithography.

  As shown in the upper left of FIG. 3, the first pattern, which is the pattern of the first photoresist mask R1, and the second pattern, which is the pattern of the second photoresist mask R2, have portions that overlap each other. ing. As a result, a pattern having a bent shape in which the first pattern and the second pattern are connected can be formed. Further, the bent portion is formed by being divided into a first pattern and a second pattern. For this reason, it is possible to prevent the corners of the bent portions from being rounded and to connect the first pattern and the second pattern with a sharp shape.

  Further, as shown in FIG. 6, since the antireflection film BC filling the region where the upper hard mask film HU is etched is formed, the second photoresist mask R2 can be formed on a flatter surface. Therefore, a sufficient DOF (Depth of Focus) can be ensured, so that the exposure accuracy of the second photoresist mask R2 is improved.

  8 and 9, the upper hard mask film HU is formed after the step of etching the lower hard mask film HD (FIG. 7) and before the step of etching the polysilicon film PS (FIG. 10). Removed. Thereby, as shown in FIG. 10, the polysilicon film PS can be patterned using the lower hard mask film HD without being affected by the upper hard mask film HU. Further, the thickness of the lower hard mask film HD remaining after patterning of the polysilicon film PS can be made uniform. In addition, it is possible to prevent the generation of foreign matters due to the upper hard mask film HU in the downstream process.

  Further, since the upper hard mask film HU is made of silicon oxide and the lower hard mask film HD is made of silicon nitride, it is possible to easily ensure the etching selectivity between the upper hard mask film HU and the lower hard mask film HD. it can.

(Embodiment 2)
FIG. 11 is a cross sectional view schematically showing a configuration of the semiconductor device in the second embodiment of the present invention.

  With reference to FIG. 11, a schematic configuration of the semiconductor device SD2 of the present embodiment will be described first. The semiconductor device SD2 has a CMOS (Complementary Metal Oxide Semiconductor) structure. That is, the semiconductor device SD2 has an NMOS (N-channel Metal Oxide Semiconductor) region NR and a PMOS (P-channel Metal Oxide Semiconductor) region PR. Each of the NMOS region NR and the PMOS region PR has a gate wiring pattern WRg having a polysilicon film PS.

  Next, the configuration of the semiconductor device SD2 will be described more specifically. The semiconductor device SD2 includes an epitaxial region EP, an isolation buried film IL, a sidewall protective film 7, a pFET (Field Effect Transistor) extension region 15, an nFET extension region 16, an oxide film 17, a sidewall film 18, It has a silicide layer 19 and nFET source / drain regions 21.

  The epitaxial region EP is a source / drain region in the PMOS region PR, and is epitaxially formed on the silicon substrate SB with a material different from the material of the silicon substrate SB. The material of the epitaxial region EP is, for example, silicon germanium (SiGe). The nFET source / drain region 21 is a source / drain region in the NMOS region NR.

  The isolation buried film IL is an insulating film for electrically isolating semiconductor elements and can be formed by an STI (Shallow Trench Isolation) method. Side wall protective film 7 and oxide film 17 are insulating films, and are made of, for example, silicon oxide. The sidewall film 18 is an insulating film and is made of, for example, silicon nitride.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  Next, a method for manufacturing the semiconductor device SD2 of the present embodiment will be described. 12 to 20 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

  Referring mainly to FIG. 12, a gate wiring pattern having polysilicon film PS is obtained by substantially the same steps up to the seventh step (FIG. 10B) of the method of manufacturing semiconductor device SD1 in the first embodiment. WRg is formed. However, in this embodiment, a thin oxide film 5 is formed on the polysilicon film PS before the formation of the lower hard mask film HD (FIG. 4).

  Referring to FIG. 13, side wall protective film 7 is formed on the side surface of polysilicon film PS and substrate protective film 8 is formed on silicon substrate SB by oxidation of the exposed surfaces of polysilicon film PS and silicon substrate SB. .

  Referring to FIG. 14, sidewall film 9 made of silicon nitride is deposited on silicon substrate SB.

  Referring to FIG. 15, resist film 10 is formed so as to cover NMOS region NR and expose PMOS region PR. A part of the sidewall film 9 is etched in the PMOS region PR by anisotropic etching. By this etching, a sidewall is formed on the side surface of the polysilicon film PS via the sidewall protective film 7 in the PMOS region PR. The resist film 10 is removed.

  Referring to FIG. 16, silicon substrate SB is partially etched in the thickness direction using lower hard mask film HD and sidewall film 9 as a mask. By this etching, in the PMOS region PR, a recess portion 11 that is a concave portion of the silicon substrate SB is formed. Next, the surface of the recess 11 is cleaned with hydrofluoric acid. Thereby, the natural oxide film on the surface of the recess portion 11 is removed.

  Referring to FIG. 17, epitaxial region EP is formed so as to fill recess portion 11 by epitaxial growth on silicon substrate SB. Specifically, for example, an epitaxial film made of SiGe having a thickness of 40 to 100 nm is formed, and then an epitaxial film made of Si having a thickness of 5 to 20 nm is formed on this film. Next, a silicon oxide film 14 is formed by surface oxidation of the epitaxial region EP. Next, the lower hard mask film HD and the sidewall film 9 are etched under an etching condition in which the etching rate of silicon nitride is higher than the etching rate of silicon oxide.

  Referring mainly to FIG. 18, oxide film 5 and substrate protective film 8 are exposed by the etching described above. Next, an implantation process and a cleaning process for forming the pFET extension region 15 and the nFET extension region 16 (FIG. 11) are performed. Note that the oxide film 5 and the substrate protective film 8 disappear during the implantation process and the cleaning process.

  Referring to FIG. 19, pFET extension region 15 and nFET extension region 16 are formed on silicon substrate SB by the above-described implantation step.

  Referring to FIG. 20, oxide film 17 and sidewall film 18 are sequentially deposited on silicon substrate SB. Next, a part of the oxide film 17 and the sidewall film 18 is removed by anisotropic etching.

  Referring to FIG. 11 again, this etching forms a sidewall having sidewall film 18 on the side surface of polysilicon film PS. Next, nFET source / drain regions 21 are formed by ion implantation in the NMOS region NR. Next, a silicide layer 19 is formed by silicidation of the surface of the polysilicon film PS, the epitaxial region EP, and the nFET source / drain region 21.

Thus, the semiconductor device SD2 of the present embodiment is manufactured.
According to the present embodiment, since the lower hard mask film HD is made of silicon nitride, it is less likely to be eroded by hydrofluoric acid for cleaning the surface of the recess 11 (FIG. 16). Therefore, the polysilicon film PS can be reliably protected from hydrofluoric acid. If the polysilicon film PS is protected only by a film made of silicon oxide, the silicon oxide is easily eroded by hydrofluoric acid, so that the protection of the polysilicon film PS may be insufficient.

  Further, before the recess 11 (FIG. 16) is formed by etching, the upper hard mask film HU (FIG. 8) on the lower hard mask film HD is removed by the etching described in the first embodiment. Therefore, the upper hard mask film HU is not lifted off during the etching of the lower hard mask film HD (FIG. 17). Therefore, the generation of foreign matter due to the lift-off can be prevented.

(Embodiment 3)
FIG. 21 is a plan view schematically showing the configuration of the semiconductor device according to the third embodiment of the present invention. 22 is a schematic cross-sectional view (A) along the line XXIIA-XXIIA in FIG. 21 and a schematic cross-sectional view (B) along the line XXIIB-XXIIB.

  Referring to FIGS. 21 and 22, this semiconductor device SD3 has a logic region LR and a memory region MR, similarly to semiconductor device SD1 (FIG. 1). The logic region LR includes active regions AC1 to AC3 having a relatively complicated shape and a non-active region NA. The memory region MR has an active region AC4 having a regular shape as compared with the active regions AC1 to AC3, and a non-active region NA. In the inactive region NA, an isolation buried film IL is formed on the silicon substrate SB.

  The active region AC1 is a line pattern having a bend A1. The active region AC1 has a width dimension W and a spacing dimension S. The spacing dimension S is smaller than the minimum spacing dimension of the pattern that can be formed by a single exposure by the exposure apparatus used for manufacturing the semiconductor device SD1. The active region AC1 is formed by patterning including a step of bending two patterns and connecting them at A1.

  The active region AC2 is a plurality of line patterns, and the line patterns form the abutments A2a and A2b with the interval dimension S. In the butt A2a, the ends of the pair of active regions AC2 face each other. In butt | matching A2b, the other edge part is distribute | arranged near one intermediate part of one pair of active region AC2.

  The active region AC3 is a pair of patterns that run parallel to each other with an interval dimension S therebetween. An isolated space A3 is formed in the region where the spacing dimension S is spaced.

  The active region AC4 is a line and space pattern having a pitch dimension P and a spacing dimension S. The pitch dimension P is smaller than the minimum pitch dimension Pmin of a pattern that can be formed by a single exposure by an exposure apparatus used for manufacturing the semiconductor device SD3. For example, P = Pmin / 2.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
FIG. 23 is a plan view schematically showing a first step of the method of manufacturing a semiconductor device in the third embodiment of the present invention. 24 to 34 are views showing the first to eleventh steps of the method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps, and are schematic cross-sectional views corresponding to the line XXIVA-XXIVA in FIG. ) And a schematic sectional view (B) corresponding to the line XXIVB-XXIVB.

  Referring mainly to FIGS. 23 and 24, the surface of silicon substrate SB (semiconductor substrate) is oxidized to form pad layer PD made of silicon oxide on silicon substrate SB. The thickness of the pad layer PD is, for example, 10 nm.

  On this pad layer PD, the stopper layer ST, the fourth hard mask film Ha4, the third hard mask film Ha3 (film to be processed), the second hard mask film Ha2 (second inorganic film), and the first hard film A mask film Ha1 (first inorganic film) is sequentially formed. The stopper layer ST is a film made of silicon nitride and having a thickness of about 90 nm. The fourth hard mask film Ha4 is a film made of silicon oxide having a thickness of about 30 nm. The third hard mask film Ha3 is a film made of polysilicon having a thickness of about 200 nm. The second hard mask film Ha2 is a film made of silicon nitride and having a thickness of about 50 nm. The first hard mask film Ha1 is a film made of silicon oxide and having a thickness of about 35 nm.

  On the first hard mask film Ha1, a first photoresist mask R1 having a first pattern (solid line pattern in FIG. 23) is formed by photolithography. That is, the photoresist is applied onto the first hard mask film Ha1 and the exposure corresponding to the first pattern is performed. This first pattern corresponds to a part of the patterns of the active regions AC1 to AC4. The first photoresist mask R1 includes a solid line pattern on the right side of FIG. 23 and a line and space pattern as shown in FIG. The line and space pattern has a pitch dimension 2P that is twice the pitch dimension P of the active region AC4. The pitch dimension 2P corresponds to the minimum pitch dimension of the line and space pattern that can be formed by photolithography of the first photoresist mask R1.

  Note that the active regions AC1 and AC4 indicated by two-dot chain lines in each of FIGS. 24A and 24B are illustrated to make the arrangement of the first photoresist mask R1 easier to see and have not yet been patterned. Absent.

Next, the first hard mask film Ha1 is selectively etched by anisotropic etching using the first photoresist mask R1 as a mask under etching conditions in which the etching rate of silicon oxide is higher than the etching rate of silicon nitride. The This etching is, for example, RIE (Reactive Ion Etching) using a mixed gas of C ₄ F ₈ and Ar as a process gas. After the etching is completed, the first photoresist mask R1 is removed.

  Referring to FIG. 25, the first pattern is transferred to first hard mask film Ha1 through the above-described processing steps.

  Referring mainly to FIG. 26, an antireflection film BC is applied on the second hard mask film Ha2. The antireflection film BC has a function of preventing reflection during exposure as a BARC film. The antireflection film BC also has a function as a buried film that fills the region where the first hard mask film Ha1 is etched. Thereby, the uneven shape of the first hard mask film Ha1 on the second hard mask film Ha2 is relaxed, and a flat surface of the antireflection film BC is formed.

  A second photoresist mask R2 having a second pattern different from the first pattern is formed on the second hard mask film Ha2 by photolithography. That is, the application of the photoresist onto the antireflection film BC and the exposure corresponding to the second pattern are performed.

  This 2nd pattern is a pattern shown with the dashed-two dotted line of FIG. 23, and respond | corresponds to a part of patterns of active region AC1-AC4. As shown in the upper left part of FIG. 23, the first pattern and the second pattern have overlapping portions. The second photoresist mask R2 includes a two-dot chain line pattern on the right side of FIG. 23 and a line and space pattern as shown in FIG. The line and space pattern has a pitch dimension 2P that is twice the pitch dimension P of the active region AC4. The pitch dimension 2P corresponds to the minimum pitch dimension of the line and space pattern that can be formed by photolithography of the second photoresist mask R2.

  In FIG. 26A, the active region AC1 indicated by a two-dot chain line is shown for easy viewing of the arrangement of the second photoresist mask R2 and the first hard mask film Ha1, and has not been patterned yet. .

Referring to FIG. 27, the second hard mask is selectively used as a mask under the etching conditions in which the etching rate of silicon nitride is higher than that of silicon oxide, using second photoresist mask R2 and first hard mask film Ha1 as a mask. The mask film Ha2 is etched. This etching is RIE using a mixed gas composed of, for example, C ₄ F ₈ , CH ₂ F ₂ , CF ₄ , O ₂ and Ar as a process gas. In this etching, the portion of the antireflection film BC that is not covered with the second photoresist mask R2 is also etched. As a result, a combined pattern in which the first pattern and the second pattern are combined is transferred to the second hard mask film Ha2. Next, the second photoresist mask R2 is removed.

  Referring to FIG. 28, antireflection film BC is removed. Note that the removal process of the antireflection film BC may not be performed.

Referring to FIG. 29, the third hard mask film Ha3 is selectively formed using the second hard mask film Ha2 as a mask under an etching condition in which the etching rate of polysilicon is higher than the etching rates of silicon nitride and silicon oxide. Etched. This etching is RIE using, for example, a mixed gas composed of HBr, Cl ₂ , O _{2 and the} like as a process gas. By this etching, a combined pattern in which the first pattern and the second pattern are combined is transferred to the third hard mask film Ha3. In FIG. 28, when the removal process of the antireflection film BC is not performed, the antireflection film BC is removed by this etching.

  Referring to FIG. 30, the fourth hard mask film Ha4, the stopper layer ST, and the pad layer PD are selectively etched using the third hard mask film Ha3 as a mask. As a result, the pattern of the third hard mask film Ha3 is transferred to the fourth hard mask film Ha4.

  Referring mainly to FIG. 31, silicon substrate SB is selectively etched using fourth hard mask film Ha4 as a mask under etching conditions in which the etching rate of polysilicon is higher than the etching rate of silicon oxide. During this etching, the third hard mask film Ha3 (FIG. 30) disappears. By this etching, the pattern of the third hard mask film Ha3 is transferred to the side of the silicon substrate SB where the third hard mask film Ha3 has been formed. That is, a groove is formed on the side of the silicon substrate SB where the third hard mask film Ha3 is formed (upper side in the figure). The depth of the groove is, for example, 250 to 300 nm.

  Referring to FIG. 32, isolation buried film IL is formed on silicon substrate SB so as to fill the groove.

  Referring to FIG. 33, the isolation buried film IL other than the trench is removed by chemical mechanical polishing (CMP). CMP is stopped halfway in the thickness direction of the stopper layer ST. Next, the stopper layer ST is removed by etching.

  Referring to FIG. 34, pad layer PD is exposed by this etching. Next, the pad layer PD is removed by etching.

Thus, the semiconductor device SD3 (FIGS. 21 and 22) of the present embodiment is manufactured.
Next, a method for manufacturing a semiconductor device of a comparative example will be described.

  35 to 41 are views showing the manufacturing method of the semiconductor device in the comparative example in the order of steps, and are schematic cross-sectional views at positions corresponding to line XXIVB-XXIVB in FIG.

  Referring mainly to FIG. 35, the stopper layer ST and the pad layer PD are formed using the third hard mask film Ha3 by a method similar to the method up to the seventh step (FIG. 30B) of the present embodiment. Selective etching is performed. As a difference from the present embodiment, in this comparative example, the fourth hard mask film Ha4 (FIG. 30B) is not provided between the third hard mask film Ha3 and the stopper layer ST. Next, selective etching of the silicon substrate SB is started using the third hard mask film Ha3.

  Referring to FIG. 36, during etching of silicon substrate SB, the thin portion of third hard mask film Ha3 disappears first, and stopper layer ST covered with this portion is exposed. Subsequently, other portions of the third hard mask film Ha3 are also lost, and the entire stopper layer ST is exposed.

  Referring to FIG. 37, the selective etching of silicon substrate SB is completed. Since the timing at which the stopper layer ST is exposed varies depending on the position as described above, the height of the stopper layer ST varies. Next, an isolation buried film IL is formed on the silicon substrate SB so as to fill the groove of the silicon substrate SB.

  Referring to FIG. 38, the isolation buried film IL other than the trench is removed by chemical mechanical polishing (CMP). CMP is stopped halfway in the thickness direction of the stopper layer ST. Since the height of the stopper layer ST varies as described above, irregularities are generated on the surface of the isolation buried film IL corresponding to the variation. Next, the stopper layer ST is removed by etching. Next, the pad layer PD is removed by etching.

  Referring to FIG. 39, isolation embedding film IL obtained by the above-described CMP and etching has large surface irregularities as compared with the present embodiment (FIG. 22B).

  Referring to FIG. 40, oxide film OX and polysilicon film PS are formed. The polysilicon film PS has a thickness dimension Hr in the vicinity of the concave portion of the isolation buried film IL, and has a thickness dimension Hp in the vicinity of the convex portion of the isolation buried film IL. The thickness dimension Hr and the thickness dimension Hp are different from each other due to the influence of the surface irregularities.

  Referring to FIG. 41, a polysilicon film PS is patterned to form a gate electrode film. A gate electrode film having a gate length dimension Lr is formed from a portion having a thickness dimension Hr of the polysilicon film PS, and a gate electrode film having a gate length dimension Lp is formed from a portion having a thickness dimension Hp of the polysilicon film PS. During patterning of the polysilicon film PS, the thickness dimension of the polysilicon film PS affects the dimension of the formed pattern as a planar pattern. For this reason, the gate length dimensions Lr and Lp of the formed gate electrode film have different values. That is, the gate length dimension of the formed gate electrode film varies. As a result, the semiconductor element having this gate electrode film has characteristic variations.

  According to the present embodiment, as shown in FIG. 31, the stopper layer ST is protected by the fourth hard mask film Ha4 when the silicon substrate SB is etched. Therefore, since the variation in the height of the stopper layer ST is suppressed as compared with the comparative example (FIG. 37), as shown in FIG. 33, the surface height of the isolation buried film IL can be made uniform. Therefore, since the variation in the thickness of the gate electrode film formed thereafter can be suppressed, unlike the comparative example (FIG. 41), the variation in the gate length can be suppressed. As a result, a semiconductor device SD3 with small characteristic variation can be obtained.

  Before the patterning of the third hard mask film Ha3 (FIG. 29) is started, the exposure of the first photoresist mask R1 (FIG. 24) and the exposure of the second photoresist mask R2 (FIG. 26) are performed. Therefore, the second photoresist mask R2 in addition to the first photoresist mask R1 is exposed without being affected by the step of the third hard mask film Ha3. For this reason, since the exposure accuracy of the second photoresist mask R2 can be increased, the pattern of the film to be processed can be formed with high accuracy.

  In the etching (FIG. 24) for transferring the first pattern to the first hard mask film Ha1, the second hard mask film Ha2 is used as an etching stopper. For this reason, since the reproducibility of the etching depth is higher than when the etching stopper is not used, the first hard mask film Ha1 can be patterned with high reproducibility. Therefore, the reproducibility of the patterning (FIG. 27) of the second hard mask film Ha2 using the first hard mask film Ha1 can be improved.

  The etching of the second hard mask film Ha2 is performed under the etching conditions in which the etching rate of silicon nitride is higher than the etching rate of silicon oxide. Accordingly, since the first hard mask film Ha1 made of silicon oxide is difficult to be etched, even if the first hard mask film Ha1 is thin, the first hard mask film Ha2 is etched during the etching of the second hard mask film Ha2 (FIG. 27). The shape of Ha1 is maintained. Therefore, since the thin first hard mask film Ha1 can be used, the surface step due to the first hard mask film Ha1 when the second photoresist mask R2 (FIG. 26) is formed is reduced. Therefore, since the second photoresist mask R2 is formed on a flatter surface, the second photoresist mask R2 can be formed with high accuracy.

  The pitch dimension P of the line and space pattern in the active region AC4 is the line and space pattern that can be formed by photolithography in each of the step of forming the first photoresist mask R1 and the step of forming the second photoresist mask R2. It is smaller than the minimum pitch dimension 2P. Accordingly, it is possible to form the active region AC4 having a denser line and space pattern than a line and space pattern that can be formed by a single photolithography.

  As shown in the upper left of FIG. 23, the first pattern, which is the pattern of the first photoresist mask R1, and the second pattern, which is the pattern of the second photoresist mask R2, have portions that overlap each other. ing. Accordingly, the active region AC1 (FIG. 21) having a bent pattern in which the first pattern and the second pattern are connected can be formed. Further, the bent portion is formed by being divided into a first pattern and a second pattern. For this reason, it is possible to prevent the corners of the bent portions from being rounded and to connect the first pattern and the second pattern with a sharp shape.

  In addition, as shown in FIG. 26, since the antireflection film BC is formed to fill the region where the first hard mask film Ha1 is etched, the second photoresist mask R2 can be formed on a flatter surface. . Therefore, a sufficient DOF (Depth of Focus) can be ensured, so that the exposure accuracy of the second photoresist mask R2 is improved.

  Also, since the first hard mask film Ha1 is made of silicon oxide and the second hard mask film Ha2 is made of silicon nitride, the etching selectivity between the first hard mask film Ha1 and the second hard mask film Ha2 can be easily made. Can be secured.

  Further, as shown in FIG. 30, the fourth hard mask film Ha4, the stopper layer ST and the pad layer PD are etched using the third hard mask film Ha3. Therefore, even when the material of the second hard mask film Ha2 and the material of any of the fourth hard mask film Ha4, the stopper layer ST, and the pad layer PD are the same or similar, the material of the third hard mask film Ha3 is appropriate. By selecting such that a selective ratio can be obtained, consumption of the mask during the etching can be suppressed. If the above etching is performed using the second hard mask film Ha2, the material of the second hard mask film Ha2 and the material of the stopper layer ST are the same, so that the etching selectivity cannot be ensured.

  In addition, since the third hard mask film Ha3 is made of polysilicon, it is possible to ensure a selection ratio between silicon oxide and silicon nitride, which are the respective materials of the fourth hard mask film Ha4 and the stopper layer ST. Further, the third hard mask film Ha3 can be formed by an inorganic CVD method.

(Embodiment 4)
The semiconductor device of the present embodiment has the same configuration (FIGS. 21 and 22) as that of the above-described third embodiment, but the manufacturing method is different. 42 to 48 are views showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps, and are a schematic cross-sectional view (A) corresponding to line XXIVA-XXIVA in FIG. 23 and a line XXIVB-XXIVB. It is a schematic sectional drawing (B) corresponding to these. Elements identical or corresponding to those of the semiconductor device manufacturing method (FIGS. 21 to 34) in the third embodiment are denoted by the same reference numerals, and description thereof will not be repeated.

  Referring to FIG. 42, stopper layer ST, third hard mask film Hb3 (film to be processed), second hard mask film Hb2 (second inorganic film), and first hard mask film are formed on pad layer PD. Hb1 (first inorganic film) is sequentially formed. The third hard mask film Hb3 is a film made of silicon oxide having a thickness of about 30 nm. The second hard mask film Hb2 is a film made of polysilicon having a thickness of about 200 nm. The first hard mask film Hb1 is a film made of silicon oxide and having a thickness of about 35 nm. A first photoresist mask R1 is formed on the first hard mask film Hb1.

  The first hard mask film Hb1 is selectively etched by anisotropic etching using the first photoresist mask R1 as a mask under etching conditions in which the etching rate of silicon oxide is higher than the etching rate of polysilicon. After the etching is completed, the first photoresist mask R1 is removed.

  Referring to FIG. 43, the first pattern is transferred to first hard mask film Hb1 through the above-described processing steps.

  Referring to FIG. 44, antireflection film BC is applied on second hard mask film Hb2. The antireflection film BC also has a function as a buried film that fills the region where the first hard mask film Hb1 is etched. Thereby, the uneven shape by the first hard mask film Hb1 on the second hard mask film Hb2 is relaxed, and a flat surface of the antireflection film BC is formed. Next, a second photoresist mask R2 is formed on the second hard mask film Hb2.

  Referring to FIG. 45, the second hard mask is selectively used by using second photoresist mask R2 and first hard mask film Hb1 as a mask under the etching conditions in which the etching rate of polysilicon is higher than the etching rate of silicon oxide. Mask film Hb2 is etched. In this etching, the portion of the antireflection film BC that is not covered with the second photoresist mask R2 is also etched. As a result, a combined pattern in which the first pattern and the second pattern are combined is transferred to the second hard mask film Hb2. Next, the second photoresist mask R2 is removed.

  Referring to FIG. 46, antireflection film BC is removed. Note that the removal process of the antireflection film BC may not be performed.

  Referring to FIG. 47, the third hard mask film Ha3 is selectively used using the second hard mask film Hb2 as a mask under the etching conditions in which the etching rate of polysilicon is higher than the etching rates of silicon nitride and silicon oxide. The stopper layer ST and the pad layer PD are etched. As a result, a combined pattern in which the first pattern and the second pattern are combined is transferred to the third hard mask film Hb3. In FIG. 28, when the removal process of the antireflection film BC is not performed, the antireflection film BC is removed by this etching.

  Referring to FIG. 48, silicon substrate SB is selectively etched using third hard mask film Hb3 as a mask under an etching condition in which the etching rate of polysilicon is higher than the etching rate of silicon oxide. By this etching, the pattern of the third hard mask film Hb3 is transferred to the third hard mask film Hb3 side of the silicon substrate SB. That is, a groove is formed on the third hard mask film Hb3 side (upper side in the drawing) of the silicon substrate SB.

  Next, isolation buried film IL is formed while removing stopper layer ST and pad layer PD by the same method as in FIGS. 32 to 34 of the third embodiment. Thereby, the semiconductor device of the present embodiment is manufactured.

  According to the present embodiment, as shown in FIG. 48, the stopper layer ST is protected by the third hard mask film Hb3 when the silicon substrate SB is etched. Therefore, as in the third embodiment, a semiconductor device with small characteristic variation can be obtained by suppressing variation in gate length.

  Before the patterning of the third hard mask film Hb3 (FIG. 46) is started, the second photoresist mask R2 is exposed (FIG. 44). Therefore, similarly to the third embodiment, by increasing the exposure accuracy of both of the second photoresist masks R2, the film to be processed can be patterned with high accuracy.

  In the etching (FIG. 42) for transferring the first pattern to the first hard mask film Hb1, the second hard mask film Hb2 is used as an etching stopper. For this reason, since the reproducibility of the etching depth is higher than when no etching stopper is used, the first hard mask film Hb1 can be patterned with high reproducibility. Therefore, the reproducibility of the patterning (FIG. 45) of the second hard mask film Hb2 using the first hard mask film Hb1 can be improved.

  In the etching of the second hard mask film Hb2 (FIG. 45), the third hard mask film Hb3 is used as an etching stopper. For this reason, since the reproducibility of the etching depth is higher than when no etching stopper is used, the second hard mask film Hb2 can be patterned with high reproducibility. Therefore, the reproducibility of the patterning (FIG. 47) of the third hard mask film Hb3 using the second hard mask film Hb2 can be improved.

  The etching of the second hard mask film Hb2 is performed under the etching conditions in which the polysilicon etching rate is higher than the silicon oxide etching rate. Accordingly, since the first hard mask film Hb1 made of silicon oxide is difficult to be etched, even if the first hard mask film Hb1 is thin, the first hard mask film Hb2 is etched during the etching of the second hard mask film Hb2 (FIG. 45). The shape of Hb1 is maintained. Therefore, since the thin first hard mask film Hb1 can be used, the surface step due to the first hard mask film Hb1 when the second photoresist mask R2 (FIG. 44) is formed is reduced. Therefore, since the second photoresist mask R2 is formed on a flatter surface, the second photoresist mask R2 can be formed with high accuracy.

  Further, since the first hard mask film Hb1 is made of silicon oxide and the second hard mask film Hb2 is made of polysilicon, the etching selectivity between the first hard mask film Hb1 and the second hard mask film Hb2 can be easily made. Can be secured.

  Further, as shown in FIG. 44, since the antireflection film BC filling the region where the first hard mask film Hb1 is etched is formed, the second photoresist mask R2 can be formed on a flatter surface. . Therefore, a sufficient DOF (Depth of Focus) can be ensured, so that the exposure accuracy of the second photoresist mask R2 is improved.

  Further, as shown in FIG. 47, the third hard mask film Hb3, the stopper layer ST, and the pad layer PD are patterned using the second hard mask film Hb2. Therefore, even when the material of the first hard mask film Hb1 and the material of the third hard mask film Hb3, the stopper layer ST, and the pad layer PD are the same or similar, the material of the second hard mask film Hb2 is appropriate. By selecting such that a selective ratio can be obtained, consumption of the mask during the etching can be suppressed.

  If the etching is performed using the first hard mask film Hb1, the material of the first hard mask film Hb1 is the same as that of the third hard mask film Hb3 and the stopper layer ST. The etching selectivity cannot be ensured.

  Further, according to the present embodiment, since the third hard mask film Hb3 is made of silicon oxide, it is possible to ensure the selection ratio between silicon nitride and silicon, which are the materials of the stopper layer ST and the silicon substrate SB, respectively. The pad layer PD is made of the same material as the third hard mask film Hb3, but is sufficiently thinner than the third hard mask film Hb3. Therefore, the pad layer PD can be etched using the third hard mask film Hb3 as a mask.

  As in the third embodiment, according to the present embodiment, the active region AC4 (FIG. 21) having a denser line and space pattern than the line and space pattern that can be formed by a single photolithography is formed. can do. Further, the active region AC1 (FIG. 21) having a bent pattern in which the first pattern and the second pattern are connected can be formed. Further, the bent portion is formed by being divided into a first pattern and a second pattern. For this reason, it is possible to prevent the corners of the bent portions from being rounded and to connect the first pattern and the second pattern with a sharp shape.

Subsequently, a modification of the present embodiment will be described.
Referring mainly to FIG. 42, in this modification, silicon nitride is used instead of silicon oxide as the material of first hard mask film Hb1. The first hard mask film Hb1 is selectively etched by anisotropic etching using the first photoresist mask R1 as a mask under etching conditions in which the etching rate of silicon nitride is higher than the etching rate of polysilicon. After the etching is completed, the first photoresist mask R1 is removed. Next, the steps of FIGS. 43 and 44 are performed in the same manner as in the present embodiment.

  Referring to FIG. 45, using the second photoresist mask R2 and the first hard mask film Hb1 as a mask under etching conditions in which the etching rate of polysilicon is higher than the etching rates of silicon nitride and silicon oxide, The second hard mask film Hb2 is selectively etched. Thereafter, the same steps as in the present embodiment are performed.

  According to this modification, the etching of the second hard mask film Hb2 is performed under the etching conditions that the etching rate of polysilicon is higher than the etching rate of silicon nitride. Therefore, since the first hard mask film Hb1 made of silicon nitride is difficult to be etched, even if the first hard mask film Hb1 is thin, the first hard mask film Hb2 is etched during the etching of the second hard mask film Hb2 (FIG. 45). The shape of Hb1 is maintained. Therefore, since the thin first hard mask film Hb1 can be used, the surface step due to the first hard mask film Hb1 when the second photoresist mask R2 (FIG. 44) is formed is reduced. Therefore, since the second photoresist mask R2 is formed on a flatter surface, the second photoresist mask R2 can be formed with high accuracy.

  In addition, since the first hard mask film Hb1 is made of silicon nitride and the second hard mask film Hb2 is made of polysilicon, the etching selectivity between the first hard mask film Hb1 and the second hard mask film Hb2 can be easily made. Can be secured.

  Further, as shown in FIG. 47, the third hard mask film Hb3, the stopper layer ST, and the pad layer PD are patterned using the second hard mask film Hb2. Therefore, even when the material of the first hard mask film Hb1 and the material of the third hard mask film Hb3, the stopper layer ST, and the pad layer PD are the same or similar, the material of the second hard mask film Hb2 is appropriate. By selecting such that a selective ratio can be obtained, consumption of the mask during the etching can be suppressed.

  If the etching is performed using the first hard mask film Hb1, the material of the first hard mask film Hb1 is the same as that of the third hard mask film Hb3 and the stopper layer ST. The etching selectivity cannot be ensured.

  In each of the above embodiments, the case where an inorganic material not containing carbon is used as the material of each of the hard mask films HU, HD, Ha1 to Ha4, and Hb1 to Hb3, but the present invention is limited to this. It is not a thing. Instead of the inorganic material not containing carbon, an inorganic material containing inorganic carbon such as graphite may be used.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a method of manufacturing a semiconductor device using a photoresist mask.

It is the top view which showed typically the structure of the semiconductor device in Embodiment 1 of this invention. 2 is a schematic cross-sectional view (A) along the line IIA-IIA in FIG. 1 and a schematic cross-sectional view (B) along the line IIB-IIB. It is a top view which shows schematically the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. FIG. 4A is a diagram showing a first step of the method for manufacturing a semiconductor device in the first embodiment of the present invention, and is a schematic cross-sectional view corresponding to line IVA-IVA in FIG. 3A and a schematic cross-section corresponding to line IVB-IVB. It is a figure (B). It is a figure which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is schematic sectional drawing (A) corresponding to line IVA-IVA of FIG. 3, and schematic sectional corresponding to line IVB-IVB It is a figure (B). It is a figure which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is schematic sectional drawing (A) corresponding to line IVA-IVA of FIG. 3, and schematic sectional corresponding to line IVB-IVB It is a figure (B). It is a figure which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is schematic sectional drawing (A) corresponding to line IVA-IVA of FIG. 3, and schematic sectional corresponding to line IVB-IVB It is a figure (B). It is a figure which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is schematic sectional drawing (A) corresponding to line IVA-IVA of FIG. 3, and schematic sectional corresponding to line IVB-IVB It is a figure (B). It is a figure which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is schematic sectional drawing (A) corresponding to line IVA-IVA of FIG. 3, and schematic sectional corresponding to line IVB-IVB It is a figure (B). It is a figure which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention, and is schematic sectional drawing (A) corresponding to line IVA-IVA of FIG. 3, and schematic sectional corresponding to line IVB-IVB It is a figure (B). It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is the top view which showed typically the structure of the semiconductor device in Embodiment 3 of this invention. FIG. 22 is a schematic cross-sectional view (A) along the line XXIIA-XXIIA in FIG. 21 and a schematic cross-sectional view (B) along the line XXIIB-XXIIB. It is a top view which shows roughly the 1st process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. FIG. 24 is a diagram showing a first step of the method of manufacturing a semiconductor device in the third embodiment of the present invention, a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23, and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24 is a diagram showing a second step of the method for manufacturing a semiconductor device in the third embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24 is a diagram showing a third step of the method for manufacturing a semiconductor device in the third embodiment of the present invention, a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23, and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24A is a diagram showing a fourth step of the method for manufacturing a semiconductor device in the third embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24A is a diagram showing a fifth step of the method for manufacturing a semiconductor device in the third embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24A is a diagram showing a sixth step of the method for manufacturing the semiconductor device in the third embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). It is a figure which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention, and is schematic sectional drawing (A) corresponding to line XXIVA-XXIVA of FIG. 23, and schematic sectional drawing corresponding to line XXIVB-XXIVB It is a figure (B). It is a figure which shows the 8th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention, and is schematic sectional drawing (A) corresponding to the line XXIVA-XXIVA of FIG. 23, and schematic sectional corresponding to the line XXIVB-XXIVB It is a figure (B). It is a figure which shows the 9th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention, and is schematic sectional drawing (A) corresponding to line XXIVA-XXIVA of FIG. 23, and schematic sectional drawing corresponding to line XXIVB-XXIVB It is a figure (B). It is a figure which shows the 10th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention, and is schematic sectional drawing (A) corresponding to the line XXIVA-XXIVA of FIG. 23, and schematic sectional corresponding to the line XXIVB-XXIVB It is a figure (B). It is a figure which shows the 11th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention, and is schematic sectional drawing (A) corresponding to line XXIVA-XXIVA of FIG. 23, and schematic sectional drawing corresponding to line XXIVB-XXIVB It is a figure (B). It is a figure which shows the 1st process of the manufacturing method of the semiconductor device in a comparative example, and is a schematic sectional drawing of the position corresponding to the line XXIVB-XXIVB of FIG. It is a figure which shows the 2nd process of the manufacturing method of the semiconductor device in a comparative example, and is a schematic sectional drawing of the position corresponding to the line XXIVB-XXIVB of FIG. It is a figure which shows the 3rd process of the manufacturing method of the semiconductor device in a comparative example, and is a schematic sectional drawing of the position corresponding to the line XXIVB-XXIVB of FIG. It is a figure which shows the 4th process of the manufacturing method of the semiconductor device in a comparative example, and is a schematic sectional drawing of the position corresponding to the line XXIVB-XXIVB of FIG. FIG. 24 is a diagram showing a fifth step of the method of manufacturing a semiconductor device in the comparative example, and is a schematic cross-sectional view at a position corresponding to line XXIVB-XXIVB in FIG. 23. It is a figure which shows the 6th process of the manufacturing method of the semiconductor device in a comparative example, and is a schematic sectional drawing of the position corresponding to the line XXIVB-XXIVB of FIG. It is a figure which shows the 7th process of the manufacturing method of the semiconductor device in a comparative example, and is a schematic sectional drawing of the position corresponding to the line XXIVB-XXIVB of FIG. FIG. 24 is a diagram showing a first step in the method of manufacturing a semiconductor device in the fourth embodiment of the present invention, a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23, and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24 is a diagram showing a second step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24A is a diagram showing a third step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24A is a diagram showing a fourth step of the method for manufacturing a semiconductor device in the fourth embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24A is a diagram showing a fifth step of the method of manufacturing a semiconductor device in the fourth embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). FIG. 24A is a diagram showing a sixth step of the method for manufacturing the semiconductor device in the fourth embodiment of the present invention, and is a schematic cross-sectional view corresponding to line XXIVA-XXIVA in FIG. 23 and a schematic cross-section corresponding to line XXIVB-XXIVB It is a figure (B). It is a figure which shows the 7th process of the manufacturing method of the semiconductor device in Embodiment 4 of this invention, and is schematic sectional drawing (A) corresponding to the line XXIVA-XXIVA of FIG. 23, and schematic sectional corresponding to the line XXIVB-XXIVB It is a figure (B).

Explanation of symbols

  BC antireflection film, EP epitaxial region, Ha1, Hb1 first hard mask film (first inorganic film), Ha2, Hb2 second hard mask film (second inorganic film), Ha3, Hb3 third hard mask film (third Inorganic film), Ha4 fourth hard mask film (fourth inorganic film), HD lower layer hard mask film (second inorganic film), HU upper layer hard mask film (first inorganic film), IL separation buried film, PD pad layer, PS polysilicon film (processed film), R1 first photoresist mask, R2 second photoresist mask, SB silicon substrate, ST stopper layer.

Claims (17)

Forming a film to be processed on a semiconductor substrate;
A first inorganic film made of a first inorganic material and a second inorganic material different from the first inorganic material and located between the first inorganic film and the processed film on the processed film. 2 forming an inorganic film;
Forming a first photoresist mask having a first pattern on the first inorganic film by photolithography;
In order to transfer the first pattern to the first inorganic film, the first photoresist mask is used as a mask under an etching condition in which an etching rate of the first inorganic material is higher than an etching rate of the second inorganic material. And selectively etching the first inorganic film using,
Forming a second photoresist mask having a second pattern different from the first pattern by photolithography on the second inorganic film after the step of etching the first inorganic film;
In order to transfer the composite pattern in which the first pattern and the second pattern are combined to the second inorganic film, the etching condition of the second inorganic material is higher than the etching speed of the first inorganic material. Selectively etching the second inorganic film using the second photoresist mask and the first inorganic film as a mask;
A step of selectively etching the processed film using the second inorganic film as a mask in order to transfer the composite pattern to the processed film after the step of etching the second inorganic film; A method for manufacturing a semiconductor device. The composite pattern includes a line and space pattern;
The pitch dimension of the line and space pattern is smaller than the minimum pitch dimension of the line and space pattern that can be formed by photolithography in each of the step of forming the first photoresist mask and the step of forming the second photoresist mask. The method for manufacturing a semiconductor device according to claim 1, wherein the method is small.   The method of manufacturing a semiconductor device according to claim 1, wherein the first pattern and the second pattern have portions that overlap each other.   After the step of etching the first inorganic film and before the step of forming the second photoresist mask, the method further includes the step of forming a buried film that fills the region where the first inorganic film is etched, The manufacturing method of the semiconductor device in any one of Claims 1-3.   After the step of etching the second inorganic film and before the step of etching the film to be processed, an etching condition in which an etching rate of the first inorganic material is larger than an etching rate of the second inorganic material, The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the first inorganic film.   The method of manufacturing a semiconductor device according to claim 1, wherein the first inorganic material includes silicon oxide, and the second inorganic material includes silicon nitride.   The method for manufacturing a semiconductor device according to claim 1, wherein the film to be processed includes a gate electrode film. The step of etching the film to be processed includes the step of leaving at least a part of the second inorganic film on the film to be processed,
A step of removing a natural oxide film on the surface of the semiconductor substrate after the step of etching the film to be processed;
The method of manufacturing a semiconductor device according to claim 7, further comprising a step of epitaxially forming source / drain regions on the surface after the step of removing the natural oxide film.   The method of manufacturing a semiconductor device according to claim 8, wherein the second inorganic film includes silicon nitride, and the step of removing the natural oxide film includes a step of cleaning the semiconductor substrate with hydrofluoric acid. The first inorganic film includes silicon oxide;
After the step of etching the second inorganic film and before the step of cleaning the semiconductor substrate, the first inorganic material is etched at an etching rate that is higher than the etching rate of the second inorganic material. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of removing one inorganic film. A step of forming a groove on the processed film side of the semiconductor substrate by transferring a pattern of the processed film to the processed film side of the semiconductor substrate after the step of etching the processed film;
Forming an insulating film on the semiconductor substrate so as to fill the groove,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the insulating film outside the groove by chemical mechanical polishing. The film to be processed includes a third inorganic film made of a third inorganic material different from the second inorganic material,
The step of forming the film to be processed includes the step of forming a fourth inorganic film made of a fourth inorganic material different from the third inorganic material on the semiconductor substrate, and the third inorganic film on the fourth inorganic film. Forming a step,
The step of forming the groove portion includes the step of using the third inorganic film as a mask to transfer the pattern of the third inorganic film to the fourth inorganic film after the step of etching the film to be processed. 12. The method according to claim 11, comprising: a step of etching the fourth inorganic film; and a step of selectively etching the semiconductor substrate using the fourth inorganic film as a mask after the step of etching the fourth inorganic film. Semiconductor device manufacturing method.   The method of manufacturing a semiconductor device according to claim 12, wherein the third inorganic material includes polycrystalline silicon.   The method for manufacturing a semiconductor device according to claim 12, wherein the fourth inorganic material includes silicon oxide.   The method of manufacturing a semiconductor device according to claim 11, wherein the film to be processed includes silicon oxide.   The method of manufacturing a semiconductor device according to claim 15, wherein the second inorganic material includes polycrystalline silicon.   The method of manufacturing a semiconductor device according to claim 15, wherein the first inorganic material includes at least one of silicon oxide and silicon nitride.

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